xref: /openbmc/linux/arch/arm/Kconfig (revision 97da55fc)
1config ARM
2	bool
3	default y
4	select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6	select ARCH_HAVE_CUSTOM_GPIO_H
7	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8	select ARCH_WANT_IPC_PARSE_VERSION
9	select BUILDTIME_EXTABLE_SORT if MMU
10	select CPU_PM if (SUSPEND || CPU_IDLE)
11	select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14	select GENERIC_IRQ_PROBE
15	select GENERIC_IRQ_SHOW
16	select GENERIC_PCI_IOMAP
17	select GENERIC_SMP_IDLE_THREAD
18	select GENERIC_STRNCPY_FROM_USER
19	select GENERIC_STRNLEN_USER
20	select HARDIRQS_SW_RESEND
21	select HAVE_AOUT
22	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23	select HAVE_ARCH_KGDB
24	select HAVE_ARCH_SECCOMP_FILTER
25	select HAVE_ARCH_TRACEHOOK
26	select HAVE_BPF_JIT
27	select HAVE_C_RECORDMCOUNT
28	select HAVE_DEBUG_KMEMLEAK
29	select HAVE_DMA_API_DEBUG
30	select HAVE_DMA_ATTRS
31	select HAVE_DMA_CONTIGUOUS if MMU
32	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36	select HAVE_GENERIC_DMA_COHERENT
37	select HAVE_GENERIC_HARDIRQS
38	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39	select HAVE_IDE if PCI || ISA || PCMCIA
40	select HAVE_KERNEL_GZIP
41	select HAVE_KERNEL_LZMA
42	select HAVE_KERNEL_LZO
43	select HAVE_KERNEL_XZ
44	select HAVE_KPROBES if !XIP_KERNEL
45	select HAVE_KRETPROBES if (HAVE_KPROBES)
46	select HAVE_MEMBLOCK
47	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48	select HAVE_PERF_EVENTS
49	select HAVE_REGS_AND_STACK_ACCESS_API
50	select HAVE_SYSCALL_TRACEPOINTS
51	select HAVE_UID16
52	select VIRT_TO_BUS
53	select KTIME_SCALAR
54	select PERF_USE_VMALLOC
55	select RTC_LIB
56	select SYS_SUPPORTS_APM_EMULATION
57	select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58	select MODULES_USE_ELF_REL
59	select CLONE_BACKWARDS
60	select OLD_SIGSUSPEND3
61	select OLD_SIGACTION
62	help
63	  The ARM series is a line of low-power-consumption RISC chip designs
64	  licensed by ARM Ltd and targeted at embedded applications and
65	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
66	  manufactured, but legacy ARM-based PC hardware remains popular in
67	  Europe.  There is an ARM Linux project with a web page at
68	  <http://www.arm.linux.org.uk/>.
69
70config ARM_HAS_SG_CHAIN
71	bool
72
73config NEED_SG_DMA_LENGTH
74	bool
75
76config ARM_DMA_USE_IOMMU
77	bool
78	select ARM_HAS_SG_CHAIN
79	select NEED_SG_DMA_LENGTH
80
81if ARM_DMA_USE_IOMMU
82
83config ARM_DMA_IOMMU_ALIGNMENT
84	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
85	range 4 9
86	default 8
87	help
88	  DMA mapping framework by default aligns all buffers to the smallest
89	  PAGE_SIZE order which is greater than or equal to the requested buffer
90	  size. This works well for buffers up to a few hundreds kilobytes, but
91	  for larger buffers it just a waste of address space. Drivers which has
92	  relatively small addressing window (like 64Mib) might run out of
93	  virtual space with just a few allocations.
94
95	  With this parameter you can specify the maximum PAGE_SIZE order for
96	  DMA IOMMU buffers. Larger buffers will be aligned only to this
97	  specified order. The order is expressed as a power of two multiplied
98	  by the PAGE_SIZE.
99
100endif
101
102config HAVE_PWM
103	bool
104
105config MIGHT_HAVE_PCI
106	bool
107
108config SYS_SUPPORTS_APM_EMULATION
109	bool
110
111config GENERIC_GPIO
112	bool
113
114config HAVE_TCM
115	bool
116	select GENERIC_ALLOCATOR
117
118config HAVE_PROC_CPU
119	bool
120
121config NO_IOPORT
122	bool
123
124config EISA
125	bool
126	---help---
127	  The Extended Industry Standard Architecture (EISA) bus was
128	  developed as an open alternative to the IBM MicroChannel bus.
129
130	  The EISA bus provided some of the features of the IBM MicroChannel
131	  bus while maintaining backward compatibility with cards made for
132	  the older ISA bus.  The EISA bus saw limited use between 1988 and
133	  1995 when it was made obsolete by the PCI bus.
134
135	  Say Y here if you are building a kernel for an EISA-based machine.
136
137	  Otherwise, say N.
138
139config SBUS
140	bool
141
142config STACKTRACE_SUPPORT
143	bool
144	default y
145
146config HAVE_LATENCYTOP_SUPPORT
147	bool
148	depends on !SMP
149	default y
150
151config LOCKDEP_SUPPORT
152	bool
153	default y
154
155config TRACE_IRQFLAGS_SUPPORT
156	bool
157	default y
158
159config RWSEM_GENERIC_SPINLOCK
160	bool
161	default y
162
163config RWSEM_XCHGADD_ALGORITHM
164	bool
165
166config ARCH_HAS_ILOG2_U32
167	bool
168
169config ARCH_HAS_ILOG2_U64
170	bool
171
172config ARCH_HAS_CPUFREQ
173	bool
174	help
175	  Internal node to signify that the ARCH has CPUFREQ support
176	  and that the relevant menu configurations are displayed for
177	  it.
178
179config GENERIC_HWEIGHT
180	bool
181	default y
182
183config GENERIC_CALIBRATE_DELAY
184	bool
185	default y
186
187config ARCH_MAY_HAVE_PC_FDC
188	bool
189
190config ZONE_DMA
191	bool
192
193config NEED_DMA_MAP_STATE
194       def_bool y
195
196config ARCH_HAS_DMA_SET_COHERENT_MASK
197	bool
198
199config GENERIC_ISA_DMA
200	bool
201
202config FIQ
203	bool
204
205config NEED_RET_TO_USER
206	bool
207
208config ARCH_MTD_XIP
209	bool
210
211config VECTORS_BASE
212	hex
213	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214	default DRAM_BASE if REMAP_VECTORS_TO_RAM
215	default 0x00000000
216	help
217	  The base address of exception vectors.
218
219config ARM_PATCH_PHYS_VIRT
220	bool "Patch physical to virtual translations at runtime" if EMBEDDED
221	default y
222	depends on !XIP_KERNEL && MMU
223	depends on !ARCH_REALVIEW || !SPARSEMEM
224	help
225	  Patch phys-to-virt and virt-to-phys translation functions at
226	  boot and module load time according to the position of the
227	  kernel in system memory.
228
229	  This can only be used with non-XIP MMU kernels where the base
230	  of physical memory is at a 16MB boundary.
231
232	  Only disable this option if you know that you do not require
233	  this feature (eg, building a kernel for a single machine) and
234	  you need to shrink the kernel to the minimal size.
235
236config NEED_MACH_GPIO_H
237	bool
238	help
239	  Select this when mach/gpio.h is required to provide special
240	  definitions for this platform. The need for mach/gpio.h should
241	  be avoided when possible.
242
243config NEED_MACH_IO_H
244	bool
245	help
246	  Select this when mach/io.h is required to provide special
247	  definitions for this platform.  The need for mach/io.h should
248	  be avoided when possible.
249
250config NEED_MACH_MEMORY_H
251	bool
252	help
253	  Select this when mach/memory.h is required to provide special
254	  definitions for this platform.  The need for mach/memory.h should
255	  be avoided when possible.
256
257config PHYS_OFFSET
258	hex "Physical address of main memory" if MMU
259	depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260	default DRAM_BASE if !MMU
261	help
262	  Please provide the physical address corresponding to the
263	  location of main memory in your system.
264
265config GENERIC_BUG
266	def_bool y
267	depends on BUG
268
269source "init/Kconfig"
270
271source "kernel/Kconfig.freezer"
272
273menu "System Type"
274
275config MMU
276	bool "MMU-based Paged Memory Management Support"
277	default y
278	help
279	  Select if you want MMU-based virtualised addressing space
280	  support by paged memory management. If unsure, say 'Y'.
281
282#
283# The "ARM system type" choice list is ordered alphabetically by option
284# text.  Please add new entries in the option alphabetic order.
285#
286choice
287	prompt "ARM system type"
288	default ARCH_VERSATILE if !MMU
289	default ARCH_MULTIPLATFORM if MMU
290
291config ARCH_MULTIPLATFORM
292	bool "Allow multiple platforms to be selected"
293	depends on MMU
294	select ARM_PATCH_PHYS_VIRT
295	select AUTO_ZRELADDR
296	select COMMON_CLK
297	select MULTI_IRQ_HANDLER
298	select SPARSE_IRQ
299	select USE_OF
300
301config ARCH_INTEGRATOR
302	bool "ARM Ltd. Integrator family"
303	select ARCH_HAS_CPUFREQ
304	select ARM_AMBA
305	select COMMON_CLK
306	select COMMON_CLK_VERSATILE
307	select GENERIC_CLOCKEVENTS
308	select HAVE_TCM
309	select ICST
310	select MULTI_IRQ_HANDLER
311	select NEED_MACH_MEMORY_H
312	select PLAT_VERSATILE
313	select SPARSE_IRQ
314	select VERSATILE_FPGA_IRQ
315	help
316	  Support for ARM's Integrator platform.
317
318config ARCH_REALVIEW
319	bool "ARM Ltd. RealView family"
320	select ARCH_WANT_OPTIONAL_GPIOLIB
321	select ARM_AMBA
322	select ARM_TIMER_SP804
323	select COMMON_CLK
324	select COMMON_CLK_VERSATILE
325	select GENERIC_CLOCKEVENTS
326	select GPIO_PL061 if GPIOLIB
327	select ICST
328	select NEED_MACH_MEMORY_H
329	select PLAT_VERSATILE
330	select PLAT_VERSATILE_CLCD
331	help
332	  This enables support for ARM Ltd RealView boards.
333
334config ARCH_VERSATILE
335	bool "ARM Ltd. Versatile family"
336	select ARCH_WANT_OPTIONAL_GPIOLIB
337	select ARM_AMBA
338	select ARM_TIMER_SP804
339	select ARM_VIC
340	select CLKDEV_LOOKUP
341	select GENERIC_CLOCKEVENTS
342	select HAVE_MACH_CLKDEV
343	select ICST
344	select PLAT_VERSATILE
345	select PLAT_VERSATILE_CLCD
346	select PLAT_VERSATILE_CLOCK
347	select VERSATILE_FPGA_IRQ
348	help
349	  This enables support for ARM Ltd Versatile board.
350
351config ARCH_AT91
352	bool "Atmel AT91"
353	select ARCH_REQUIRE_GPIOLIB
354	select CLKDEV_LOOKUP
355	select HAVE_CLK
356	select IRQ_DOMAIN
357	select NEED_MACH_GPIO_H
358	select NEED_MACH_IO_H if PCCARD
359	select PINCTRL
360	select PINCTRL_AT91 if USE_OF
361	help
362	  This enables support for systems based on Atmel
363	  AT91RM9200 and AT91SAM9* processors.
364
365config ARCH_BCM2835
366	bool "Broadcom BCM2835 family"
367	select ARCH_REQUIRE_GPIOLIB
368	select ARM_AMBA
369	select ARM_ERRATA_411920
370	select ARM_TIMER_SP804
371	select CLKDEV_LOOKUP
372	select CLKSRC_OF
373	select COMMON_CLK
374	select CPU_V6
375	select GENERIC_CLOCKEVENTS
376	select MULTI_IRQ_HANDLER
377	select PINCTRL
378	select PINCTRL_BCM2835
379	select SPARSE_IRQ
380	select USE_OF
381	help
382	  This enables support for the Broadcom BCM2835 SoC. This SoC is
383	  use in the Raspberry Pi, and Roku 2 devices.
384
385config ARCH_CNS3XXX
386	bool "Cavium Networks CNS3XXX family"
387	select ARM_GIC
388	select CPU_V6K
389	select GENERIC_CLOCKEVENTS
390	select MIGHT_HAVE_CACHE_L2X0
391	select MIGHT_HAVE_PCI
392	select PCI_DOMAINS if PCI
393	help
394	  Support for Cavium Networks CNS3XXX platform.
395
396config ARCH_CLPS711X
397	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398	select ARCH_REQUIRE_GPIOLIB
399	select AUTO_ZRELADDR
400	select CLKDEV_LOOKUP
401	select COMMON_CLK
402	select CPU_ARM720T
403	select GENERIC_CLOCKEVENTS
404	select MULTI_IRQ_HANDLER
405	select NEED_MACH_MEMORY_H
406	select SPARSE_IRQ
407	help
408	  Support for Cirrus Logic 711x/721x/731x based boards.
409
410config ARCH_GEMINI
411	bool "Cortina Systems Gemini"
412	select ARCH_REQUIRE_GPIOLIB
413	select ARCH_USES_GETTIMEOFFSET
414	select CPU_FA526
415	help
416	  Support for the Cortina Systems Gemini family SoCs
417
418config ARCH_SIRF
419	bool "CSR SiRF"
420	select ARCH_REQUIRE_GPIOLIB
421	select AUTO_ZRELADDR
422	select COMMON_CLK
423	select GENERIC_CLOCKEVENTS
424	select GENERIC_IRQ_CHIP
425	select MIGHT_HAVE_CACHE_L2X0
426	select NO_IOPORT
427	select PINCTRL
428	select PINCTRL_SIRF
429	select USE_OF
430	help
431	  Support for CSR SiRFprimaII/Marco/Polo platforms
432
433config ARCH_EBSA110
434	bool "EBSA-110"
435	select ARCH_USES_GETTIMEOFFSET
436	select CPU_SA110
437	select ISA
438	select NEED_MACH_IO_H
439	select NEED_MACH_MEMORY_H
440	select NO_IOPORT
441	help
442	  This is an evaluation board for the StrongARM processor available
443	  from Digital. It has limited hardware on-board, including an
444	  Ethernet interface, two PCMCIA sockets, two serial ports and a
445	  parallel port.
446
447config ARCH_EP93XX
448	bool "EP93xx-based"
449	select ARCH_HAS_HOLES_MEMORYMODEL
450	select ARCH_REQUIRE_GPIOLIB
451	select ARCH_USES_GETTIMEOFFSET
452	select ARM_AMBA
453	select ARM_VIC
454	select CLKDEV_LOOKUP
455	select CPU_ARM920T
456	select NEED_MACH_MEMORY_H
457	help
458	  This enables support for the Cirrus EP93xx series of CPUs.
459
460config ARCH_FOOTBRIDGE
461	bool "FootBridge"
462	select CPU_SA110
463	select FOOTBRIDGE
464	select GENERIC_CLOCKEVENTS
465	select HAVE_IDE
466	select NEED_MACH_IO_H if !MMU
467	select NEED_MACH_MEMORY_H
468	help
469	  Support for systems based on the DC21285 companion chip
470	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
471
472config ARCH_MXS
473	bool "Freescale MXS-based"
474	select ARCH_REQUIRE_GPIOLIB
475	select CLKDEV_LOOKUP
476	select CLKSRC_MMIO
477	select COMMON_CLK
478	select GENERIC_CLOCKEVENTS
479	select HAVE_CLK_PREPARE
480	select MULTI_IRQ_HANDLER
481	select PINCTRL
482	select SPARSE_IRQ
483	select USE_OF
484	help
485	  Support for Freescale MXS-based family of processors
486
487config ARCH_NETX
488	bool "Hilscher NetX based"
489	select ARM_VIC
490	select CLKSRC_MMIO
491	select CPU_ARM926T
492	select GENERIC_CLOCKEVENTS
493	help
494	  This enables support for systems based on the Hilscher NetX Soc
495
496config ARCH_H720X
497	bool "Hynix HMS720x-based"
498	select ARCH_USES_GETTIMEOFFSET
499	select CPU_ARM720T
500	select ISA_DMA_API
501	help
502	  This enables support for systems based on the Hynix HMS720x
503
504config ARCH_IOP13XX
505	bool "IOP13xx-based"
506	depends on MMU
507	select ARCH_SUPPORTS_MSI
508	select CPU_XSC3
509	select NEED_MACH_MEMORY_H
510	select NEED_RET_TO_USER
511	select PCI
512	select PLAT_IOP
513	select VMSPLIT_1G
514	help
515	  Support for Intel's IOP13XX (XScale) family of processors.
516
517config ARCH_IOP32X
518	bool "IOP32x-based"
519	depends on MMU
520	select ARCH_REQUIRE_GPIOLIB
521	select CPU_XSCALE
522	select NEED_MACH_GPIO_H
523	select NEED_RET_TO_USER
524	select PCI
525	select PLAT_IOP
526	help
527	  Support for Intel's 80219 and IOP32X (XScale) family of
528	  processors.
529
530config ARCH_IOP33X
531	bool "IOP33x-based"
532	depends on MMU
533	select ARCH_REQUIRE_GPIOLIB
534	select CPU_XSCALE
535	select NEED_MACH_GPIO_H
536	select NEED_RET_TO_USER
537	select PCI
538	select PLAT_IOP
539	help
540	  Support for Intel's IOP33X (XScale) family of processors.
541
542config ARCH_IXP4XX
543	bool "IXP4xx-based"
544	depends on MMU
545	select ARCH_HAS_DMA_SET_COHERENT_MASK
546	select ARCH_REQUIRE_GPIOLIB
547	select CLKSRC_MMIO
548	select CPU_XSCALE
549	select DMABOUNCE if PCI
550	select GENERIC_CLOCKEVENTS
551	select MIGHT_HAVE_PCI
552	select NEED_MACH_IO_H
553	help
554	  Support for Intel's IXP4XX (XScale) family of processors.
555
556config ARCH_DOVE
557	bool "Marvell Dove"
558	select ARCH_REQUIRE_GPIOLIB
559	select CPU_V7
560	select GENERIC_CLOCKEVENTS
561	select MIGHT_HAVE_PCI
562	select PINCTRL
563	select PINCTRL_DOVE
564	select PLAT_ORION_LEGACY
565	select USB_ARCH_HAS_EHCI
566	help
567	  Support for the Marvell Dove SoC 88AP510
568
569config ARCH_KIRKWOOD
570	bool "Marvell Kirkwood"
571	select ARCH_REQUIRE_GPIOLIB
572	select CPU_FEROCEON
573	select GENERIC_CLOCKEVENTS
574	select PCI
575	select PCI_QUIRKS
576	select PINCTRL
577	select PINCTRL_KIRKWOOD
578	select PLAT_ORION_LEGACY
579	help
580	  Support for the following Marvell Kirkwood series SoCs:
581	  88F6180, 88F6192 and 88F6281.
582
583config ARCH_MV78XX0
584	bool "Marvell MV78xx0"
585	select ARCH_REQUIRE_GPIOLIB
586	select CPU_FEROCEON
587	select GENERIC_CLOCKEVENTS
588	select PCI
589	select PLAT_ORION_LEGACY
590	help
591	  Support for the following Marvell MV78xx0 series SoCs:
592	  MV781x0, MV782x0.
593
594config ARCH_ORION5X
595	bool "Marvell Orion"
596	depends on MMU
597	select ARCH_REQUIRE_GPIOLIB
598	select CPU_FEROCEON
599	select GENERIC_CLOCKEVENTS
600	select PCI
601	select PLAT_ORION_LEGACY
602	help
603	  Support for the following Marvell Orion 5x series SoCs:
604	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
605	  Orion-2 (5281), Orion-1-90 (6183).
606
607config ARCH_MMP
608	bool "Marvell PXA168/910/MMP2"
609	depends on MMU
610	select ARCH_REQUIRE_GPIOLIB
611	select CLKDEV_LOOKUP
612	select GENERIC_ALLOCATOR
613	select GENERIC_CLOCKEVENTS
614	select GPIO_PXA
615	select IRQ_DOMAIN
616	select NEED_MACH_GPIO_H
617	select PINCTRL
618	select PLAT_PXA
619	select SPARSE_IRQ
620	help
621	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
622
623config ARCH_KS8695
624	bool "Micrel/Kendin KS8695"
625	select ARCH_REQUIRE_GPIOLIB
626	select CLKSRC_MMIO
627	select CPU_ARM922T
628	select GENERIC_CLOCKEVENTS
629	select NEED_MACH_MEMORY_H
630	help
631	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
632	  System-on-Chip devices.
633
634config ARCH_W90X900
635	bool "Nuvoton W90X900 CPU"
636	select ARCH_REQUIRE_GPIOLIB
637	select CLKDEV_LOOKUP
638	select CLKSRC_MMIO
639	select CPU_ARM926T
640	select GENERIC_CLOCKEVENTS
641	help
642	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
643	  At present, the w90x900 has been renamed nuc900, regarding
644	  the ARM series product line, you can login the following
645	  link address to know more.
646
647	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
648		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
649
650config ARCH_LPC32XX
651	bool "NXP LPC32XX"
652	select ARCH_REQUIRE_GPIOLIB
653	select ARM_AMBA
654	select CLKDEV_LOOKUP
655	select CLKSRC_MMIO
656	select CPU_ARM926T
657	select GENERIC_CLOCKEVENTS
658	select HAVE_IDE
659	select HAVE_PWM
660	select USB_ARCH_HAS_OHCI
661	select USE_OF
662	help
663	  Support for the NXP LPC32XX family of processors
664
665config ARCH_TEGRA
666	bool "NVIDIA Tegra"
667	select ARCH_HAS_CPUFREQ
668	select ARCH_REQUIRE_GPIOLIB
669	select CLKDEV_LOOKUP
670	select CLKSRC_MMIO
671	select CLKSRC_OF
672	select COMMON_CLK
673	select GENERIC_CLOCKEVENTS
674	select HAVE_CLK
675	select HAVE_SMP
676	select MIGHT_HAVE_CACHE_L2X0
677	select SPARSE_IRQ
678	select USE_OF
679	help
680	  This enables support for NVIDIA Tegra based systems (Tegra APX,
681	  Tegra 6xx and Tegra 2 series).
682
683config ARCH_PXA
684	bool "PXA2xx/PXA3xx-based"
685	depends on MMU
686	select ARCH_HAS_CPUFREQ
687	select ARCH_MTD_XIP
688	select ARCH_REQUIRE_GPIOLIB
689	select ARM_CPU_SUSPEND if PM
690	select AUTO_ZRELADDR
691	select CLKDEV_LOOKUP
692	select CLKSRC_MMIO
693	select GENERIC_CLOCKEVENTS
694	select GPIO_PXA
695	select HAVE_IDE
696	select MULTI_IRQ_HANDLER
697	select NEED_MACH_GPIO_H
698	select PLAT_PXA
699	select SPARSE_IRQ
700	help
701	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
702
703config ARCH_MSM
704	bool "Qualcomm MSM"
705	select ARCH_REQUIRE_GPIOLIB
706	select CLKDEV_LOOKUP
707	select GENERIC_CLOCKEVENTS
708	select HAVE_CLK
709	help
710	  Support for Qualcomm MSM/QSD based systems.  This runs on the
711	  apps processor of the MSM/QSD and depends on a shared memory
712	  interface to the modem processor which runs the baseband
713	  stack and controls some vital subsystems
714	  (clock and power control, etc).
715
716config ARCH_SHMOBILE
717	bool "Renesas SH-Mobile / R-Mobile"
718	select CLKDEV_LOOKUP
719	select GENERIC_CLOCKEVENTS
720	select HAVE_CLK
721	select HAVE_MACH_CLKDEV
722	select HAVE_SMP
723	select MIGHT_HAVE_CACHE_L2X0
724	select MULTI_IRQ_HANDLER
725	select NEED_MACH_MEMORY_H
726	select NO_IOPORT
727	select PINCTRL
728	select PM_GENERIC_DOMAINS if PM
729	select SPARSE_IRQ
730	help
731	  Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
732
733config ARCH_RPC
734	bool "RiscPC"
735	select ARCH_ACORN
736	select ARCH_MAY_HAVE_PC_FDC
737	select ARCH_SPARSEMEM_ENABLE
738	select ARCH_USES_GETTIMEOFFSET
739	select FIQ
740	select HAVE_IDE
741	select HAVE_PATA_PLATFORM
742	select ISA_DMA_API
743	select NEED_MACH_IO_H
744	select NEED_MACH_MEMORY_H
745	select NO_IOPORT
746	help
747	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
748	  CD-ROM interface, serial and parallel port, and the floppy drive.
749
750config ARCH_SA1100
751	bool "SA1100-based"
752	select ARCH_HAS_CPUFREQ
753	select ARCH_MTD_XIP
754	select ARCH_REQUIRE_GPIOLIB
755	select ARCH_SPARSEMEM_ENABLE
756	select CLKDEV_LOOKUP
757	select CLKSRC_MMIO
758	select CPU_FREQ
759	select CPU_SA1100
760	select GENERIC_CLOCKEVENTS
761	select HAVE_IDE
762	select ISA
763	select NEED_MACH_GPIO_H
764	select NEED_MACH_MEMORY_H
765	select SPARSE_IRQ
766	help
767	  Support for StrongARM 11x0 based boards.
768
769config ARCH_S3C24XX
770	bool "Samsung S3C24XX SoCs"
771	select ARCH_HAS_CPUFREQ
772	select ARCH_USES_GETTIMEOFFSET
773	select CLKDEV_LOOKUP
774	select HAVE_CLK
775	select HAVE_S3C2410_I2C if I2C
776	select HAVE_S3C2410_WATCHDOG if WATCHDOG
777	select HAVE_S3C_RTC if RTC_CLASS
778	select NEED_MACH_GPIO_H
779	select NEED_MACH_IO_H
780	help
781	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
782	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
783	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
784	  Samsung SMDK2410 development board (and derivatives).
785
786config ARCH_S3C64XX
787	bool "Samsung S3C64XX"
788	select ARCH_HAS_CPUFREQ
789	select ARCH_REQUIRE_GPIOLIB
790	select ARCH_USES_GETTIMEOFFSET
791	select ARM_VIC
792	select CLKDEV_LOOKUP
793	select CPU_V6
794	select HAVE_CLK
795	select HAVE_S3C2410_I2C if I2C
796	select HAVE_S3C2410_WATCHDOG if WATCHDOG
797	select HAVE_TCM
798	select NEED_MACH_GPIO_H
799	select NO_IOPORT
800	select PLAT_SAMSUNG
801	select S3C_DEV_NAND
802	select S3C_GPIO_TRACK
803	select SAMSUNG_CLKSRC
804	select SAMSUNG_GPIOLIB_4BIT
805	select SAMSUNG_IRQ_VIC_TIMER
806	select USB_ARCH_HAS_OHCI
807	help
808	  Samsung S3C64XX series based systems
809
810config ARCH_S5P64X0
811	bool "Samsung S5P6440 S5P6450"
812	select CLKDEV_LOOKUP
813	select CLKSRC_MMIO
814	select CPU_V6
815	select GENERIC_CLOCKEVENTS
816	select HAVE_CLK
817	select HAVE_S3C2410_I2C if I2C
818	select HAVE_S3C2410_WATCHDOG if WATCHDOG
819	select HAVE_S3C_RTC if RTC_CLASS
820	select NEED_MACH_GPIO_H
821	help
822	  Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
823	  SMDK6450.
824
825config ARCH_S5PC100
826	bool "Samsung S5PC100"
827	select ARCH_USES_GETTIMEOFFSET
828	select CLKDEV_LOOKUP
829	select CPU_V7
830	select HAVE_CLK
831	select HAVE_S3C2410_I2C if I2C
832	select HAVE_S3C2410_WATCHDOG if WATCHDOG
833	select HAVE_S3C_RTC if RTC_CLASS
834	select NEED_MACH_GPIO_H
835	help
836	  Samsung S5PC100 series based systems
837
838config ARCH_S5PV210
839	bool "Samsung S5PV210/S5PC110"
840	select ARCH_HAS_CPUFREQ
841	select ARCH_HAS_HOLES_MEMORYMODEL
842	select ARCH_SPARSEMEM_ENABLE
843	select CLKDEV_LOOKUP
844	select CLKSRC_MMIO
845	select CPU_V7
846	select GENERIC_CLOCKEVENTS
847	select HAVE_CLK
848	select HAVE_S3C2410_I2C if I2C
849	select HAVE_S3C2410_WATCHDOG if WATCHDOG
850	select HAVE_S3C_RTC if RTC_CLASS
851	select NEED_MACH_GPIO_H
852	select NEED_MACH_MEMORY_H
853	help
854	  Samsung S5PV210/S5PC110 series based systems
855
856config ARCH_EXYNOS
857	bool "Samsung EXYNOS"
858	select ARCH_HAS_CPUFREQ
859	select ARCH_HAS_HOLES_MEMORYMODEL
860	select ARCH_SPARSEMEM_ENABLE
861	select CLKDEV_LOOKUP
862	select CPU_V7
863	select GENERIC_CLOCKEVENTS
864	select HAVE_CLK
865	select HAVE_S3C2410_I2C if I2C
866	select HAVE_S3C2410_WATCHDOG if WATCHDOG
867	select HAVE_S3C_RTC if RTC_CLASS
868	select NEED_MACH_GPIO_H
869	select NEED_MACH_MEMORY_H
870	help
871	  Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
872
873config ARCH_SHARK
874	bool "Shark"
875	select ARCH_USES_GETTIMEOFFSET
876	select CPU_SA110
877	select ISA
878	select ISA_DMA
879	select NEED_MACH_MEMORY_H
880	select PCI
881	select ZONE_DMA
882	help
883	  Support for the StrongARM based Digital DNARD machine, also known
884	  as "Shark" (<http://www.shark-linux.de/shark.html>).
885
886config ARCH_U300
887	bool "ST-Ericsson U300 Series"
888	depends on MMU
889	select ARCH_REQUIRE_GPIOLIB
890	select ARM_AMBA
891	select ARM_PATCH_PHYS_VIRT
892	select ARM_VIC
893	select CLKDEV_LOOKUP
894	select CLKSRC_MMIO
895	select COMMON_CLK
896	select CPU_ARM926T
897	select GENERIC_CLOCKEVENTS
898	select HAVE_TCM
899	select SPARSE_IRQ
900	help
901	  Support for ST-Ericsson U300 series mobile platforms.
902
903config ARCH_U8500
904	bool "ST-Ericsson U8500 Series"
905	depends on MMU
906	select ARCH_HAS_CPUFREQ
907	select ARCH_REQUIRE_GPIOLIB
908	select ARM_AMBA
909	select CLKDEV_LOOKUP
910	select CPU_V7
911	select GENERIC_CLOCKEVENTS
912	select HAVE_SMP
913	select MIGHT_HAVE_CACHE_L2X0
914	select SPARSE_IRQ
915	help
916	  Support for ST-Ericsson's Ux500 architecture
917
918config ARCH_NOMADIK
919	bool "STMicroelectronics Nomadik"
920	select ARCH_REQUIRE_GPIOLIB
921	select ARM_AMBA
922	select ARM_VIC
923	select CLKSRC_NOMADIK_MTU
924	select COMMON_CLK
925	select CPU_ARM926T
926	select GENERIC_CLOCKEVENTS
927	select MIGHT_HAVE_CACHE_L2X0
928	select USE_OF
929	select PINCTRL
930	select PINCTRL_STN8815
931	select SPARSE_IRQ
932	help
933	  Support for the Nomadik platform by ST-Ericsson
934
935config PLAT_SPEAR
936	bool "ST SPEAr"
937	select ARCH_HAS_CPUFREQ
938	select ARCH_REQUIRE_GPIOLIB
939	select ARM_AMBA
940	select CLKDEV_LOOKUP
941	select CLKSRC_MMIO
942	select COMMON_CLK
943	select GENERIC_CLOCKEVENTS
944	select HAVE_CLK
945	help
946	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
947
948config ARCH_DAVINCI
949	bool "TI DaVinci"
950	select ARCH_HAS_HOLES_MEMORYMODEL
951	select ARCH_REQUIRE_GPIOLIB
952	select CLKDEV_LOOKUP
953	select GENERIC_ALLOCATOR
954	select GENERIC_CLOCKEVENTS
955	select GENERIC_IRQ_CHIP
956	select HAVE_IDE
957	select NEED_MACH_GPIO_H
958	select USE_OF
959	select ZONE_DMA
960	help
961	  Support for TI's DaVinci platform.
962
963config ARCH_OMAP1
964	bool "TI OMAP1"
965	depends on MMU
966	select ARCH_HAS_CPUFREQ
967	select ARCH_HAS_HOLES_MEMORYMODEL
968	select ARCH_OMAP
969	select ARCH_REQUIRE_GPIOLIB
970	select CLKDEV_LOOKUP
971	select CLKSRC_MMIO
972	select GENERIC_CLOCKEVENTS
973	select GENERIC_IRQ_CHIP
974	select HAVE_CLK
975	select HAVE_IDE
976	select IRQ_DOMAIN
977	select NEED_MACH_IO_H if PCCARD
978	select NEED_MACH_MEMORY_H
979	help
980	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
981
982endchoice
983
984menu "Multiple platform selection"
985	depends on ARCH_MULTIPLATFORM
986
987comment "CPU Core family selection"
988
989config ARCH_MULTI_V4
990	bool "ARMv4 based platforms (FA526, StrongARM)"
991	depends on !ARCH_MULTI_V6_V7
992	select ARCH_MULTI_V4_V5
993
994config ARCH_MULTI_V4T
995	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
996	depends on !ARCH_MULTI_V6_V7
997	select ARCH_MULTI_V4_V5
998
999config ARCH_MULTI_V5
1000	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1001	depends on !ARCH_MULTI_V6_V7
1002	select ARCH_MULTI_V4_V5
1003
1004config ARCH_MULTI_V4_V5
1005	bool
1006
1007config ARCH_MULTI_V6
1008	bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1009	select ARCH_MULTI_V6_V7
1010	select CPU_V6
1011
1012config ARCH_MULTI_V7
1013	bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1014	default y
1015	select ARCH_MULTI_V6_V7
1016	select ARCH_VEXPRESS
1017	select CPU_V7
1018
1019config ARCH_MULTI_V6_V7
1020	bool
1021
1022config ARCH_MULTI_CPU_AUTO
1023	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1024	select ARCH_MULTI_V5
1025
1026endmenu
1027
1028#
1029# This is sorted alphabetically by mach-* pathname.  However, plat-*
1030# Kconfigs may be included either alphabetically (according to the
1031# plat- suffix) or along side the corresponding mach-* source.
1032#
1033source "arch/arm/mach-mvebu/Kconfig"
1034
1035source "arch/arm/mach-at91/Kconfig"
1036
1037source "arch/arm/mach-bcm/Kconfig"
1038
1039source "arch/arm/mach-clps711x/Kconfig"
1040
1041source "arch/arm/mach-cns3xxx/Kconfig"
1042
1043source "arch/arm/mach-davinci/Kconfig"
1044
1045source "arch/arm/mach-dove/Kconfig"
1046
1047source "arch/arm/mach-ep93xx/Kconfig"
1048
1049source "arch/arm/mach-footbridge/Kconfig"
1050
1051source "arch/arm/mach-gemini/Kconfig"
1052
1053source "arch/arm/mach-h720x/Kconfig"
1054
1055source "arch/arm/mach-highbank/Kconfig"
1056
1057source "arch/arm/mach-integrator/Kconfig"
1058
1059source "arch/arm/mach-iop32x/Kconfig"
1060
1061source "arch/arm/mach-iop33x/Kconfig"
1062
1063source "arch/arm/mach-iop13xx/Kconfig"
1064
1065source "arch/arm/mach-ixp4xx/Kconfig"
1066
1067source "arch/arm/mach-kirkwood/Kconfig"
1068
1069source "arch/arm/mach-ks8695/Kconfig"
1070
1071source "arch/arm/mach-msm/Kconfig"
1072
1073source "arch/arm/mach-mv78xx0/Kconfig"
1074
1075source "arch/arm/mach-imx/Kconfig"
1076
1077source "arch/arm/mach-mxs/Kconfig"
1078
1079source "arch/arm/mach-netx/Kconfig"
1080
1081source "arch/arm/mach-nomadik/Kconfig"
1082
1083source "arch/arm/plat-omap/Kconfig"
1084
1085source "arch/arm/mach-omap1/Kconfig"
1086
1087source "arch/arm/mach-omap2/Kconfig"
1088
1089source "arch/arm/mach-orion5x/Kconfig"
1090
1091source "arch/arm/mach-picoxcell/Kconfig"
1092
1093source "arch/arm/mach-pxa/Kconfig"
1094source "arch/arm/plat-pxa/Kconfig"
1095
1096source "arch/arm/mach-mmp/Kconfig"
1097
1098source "arch/arm/mach-realview/Kconfig"
1099
1100source "arch/arm/mach-sa1100/Kconfig"
1101
1102source "arch/arm/plat-samsung/Kconfig"
1103
1104source "arch/arm/mach-socfpga/Kconfig"
1105
1106source "arch/arm/plat-spear/Kconfig"
1107
1108source "arch/arm/mach-s3c24xx/Kconfig"
1109
1110if ARCH_S3C64XX
1111source "arch/arm/mach-s3c64xx/Kconfig"
1112endif
1113
1114source "arch/arm/mach-s5p64x0/Kconfig"
1115
1116source "arch/arm/mach-s5pc100/Kconfig"
1117
1118source "arch/arm/mach-s5pv210/Kconfig"
1119
1120source "arch/arm/mach-exynos/Kconfig"
1121
1122source "arch/arm/mach-shmobile/Kconfig"
1123
1124source "arch/arm/mach-sunxi/Kconfig"
1125
1126source "arch/arm/mach-prima2/Kconfig"
1127
1128source "arch/arm/mach-tegra/Kconfig"
1129
1130source "arch/arm/mach-u300/Kconfig"
1131
1132source "arch/arm/mach-ux500/Kconfig"
1133
1134source "arch/arm/mach-versatile/Kconfig"
1135
1136source "arch/arm/mach-vexpress/Kconfig"
1137source "arch/arm/plat-versatile/Kconfig"
1138
1139source "arch/arm/mach-virt/Kconfig"
1140
1141source "arch/arm/mach-vt8500/Kconfig"
1142
1143source "arch/arm/mach-w90x900/Kconfig"
1144
1145source "arch/arm/mach-zynq/Kconfig"
1146
1147# Definitions to make life easier
1148config ARCH_ACORN
1149	bool
1150
1151config PLAT_IOP
1152	bool
1153	select GENERIC_CLOCKEVENTS
1154
1155config PLAT_ORION
1156	bool
1157	select CLKSRC_MMIO
1158	select COMMON_CLK
1159	select GENERIC_IRQ_CHIP
1160	select IRQ_DOMAIN
1161
1162config PLAT_ORION_LEGACY
1163	bool
1164	select PLAT_ORION
1165
1166config PLAT_PXA
1167	bool
1168
1169config PLAT_VERSATILE
1170	bool
1171
1172config ARM_TIMER_SP804
1173	bool
1174	select CLKSRC_MMIO
1175	select HAVE_SCHED_CLOCK
1176
1177source arch/arm/mm/Kconfig
1178
1179config ARM_NR_BANKS
1180	int
1181	default 16 if ARCH_EP93XX
1182	default 8
1183
1184config IWMMXT
1185	bool "Enable iWMMXt support"
1186	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1187	default y if PXA27x || PXA3xx || ARCH_MMP
1188	help
1189	  Enable support for iWMMXt context switching at run time if
1190	  running on a CPU that supports it.
1191
1192config XSCALE_PMU
1193	bool
1194	depends on CPU_XSCALE
1195	default y
1196
1197config MULTI_IRQ_HANDLER
1198	bool
1199	help
1200	  Allow each machine to specify it's own IRQ handler at run time.
1201
1202if !MMU
1203source "arch/arm/Kconfig-nommu"
1204endif
1205
1206config ARM_ERRATA_326103
1207	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1208	depends on CPU_V6
1209	help
1210	  Executing a SWP instruction to read-only memory does not set bit 11
1211	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1212	  treat the access as a read, preventing a COW from occurring and
1213	  causing the faulting task to livelock.
1214
1215config ARM_ERRATA_411920
1216	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1217	depends on CPU_V6 || CPU_V6K
1218	help
1219	  Invalidation of the Instruction Cache operation can
1220	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1221	  It does not affect the MPCore. This option enables the ARM Ltd.
1222	  recommended workaround.
1223
1224config ARM_ERRATA_430973
1225	bool "ARM errata: Stale prediction on replaced interworking branch"
1226	depends on CPU_V7
1227	help
1228	  This option enables the workaround for the 430973 Cortex-A8
1229	  (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1230	  interworking branch is replaced with another code sequence at the
1231	  same virtual address, whether due to self-modifying code or virtual
1232	  to physical address re-mapping, Cortex-A8 does not recover from the
1233	  stale interworking branch prediction. This results in Cortex-A8
1234	  executing the new code sequence in the incorrect ARM or Thumb state.
1235	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1236	  and also flushes the branch target cache at every context switch.
1237	  Note that setting specific bits in the ACTLR register may not be
1238	  available in non-secure mode.
1239
1240config ARM_ERRATA_458693
1241	bool "ARM errata: Processor deadlock when a false hazard is created"
1242	depends on CPU_V7
1243	depends on !ARCH_MULTIPLATFORM
1244	help
1245	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1246	  erratum. For very specific sequences of memory operations, it is
1247	  possible for a hazard condition intended for a cache line to instead
1248	  be incorrectly associated with a different cache line. This false
1249	  hazard might then cause a processor deadlock. The workaround enables
1250	  the L1 caching of the NEON accesses and disables the PLD instruction
1251	  in the ACTLR register. Note that setting specific bits in the ACTLR
1252	  register may not be available in non-secure mode.
1253
1254config ARM_ERRATA_460075
1255	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1256	depends on CPU_V7
1257	depends on !ARCH_MULTIPLATFORM
1258	help
1259	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1260	  erratum. Any asynchronous access to the L2 cache may encounter a
1261	  situation in which recent store transactions to the L2 cache are lost
1262	  and overwritten with stale memory contents from external memory. The
1263	  workaround disables the write-allocate mode for the L2 cache via the
1264	  ACTLR register. Note that setting specific bits in the ACTLR register
1265	  may not be available in non-secure mode.
1266
1267config ARM_ERRATA_742230
1268	bool "ARM errata: DMB operation may be faulty"
1269	depends on CPU_V7 && SMP
1270	depends on !ARCH_MULTIPLATFORM
1271	help
1272	  This option enables the workaround for the 742230 Cortex-A9
1273	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1274	  between two write operations may not ensure the correct visibility
1275	  ordering of the two writes. This workaround sets a specific bit in
1276	  the diagnostic register of the Cortex-A9 which causes the DMB
1277	  instruction to behave as a DSB, ensuring the correct behaviour of
1278	  the two writes.
1279
1280config ARM_ERRATA_742231
1281	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1282	depends on CPU_V7 && SMP
1283	depends on !ARCH_MULTIPLATFORM
1284	help
1285	  This option enables the workaround for the 742231 Cortex-A9
1286	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1287	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1288	  accessing some data located in the same cache line, may get corrupted
1289	  data due to bad handling of the address hazard when the line gets
1290	  replaced from one of the CPUs at the same time as another CPU is
1291	  accessing it. This workaround sets specific bits in the diagnostic
1292	  register of the Cortex-A9 which reduces the linefill issuing
1293	  capabilities of the processor.
1294
1295config PL310_ERRATA_588369
1296	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1297	depends on CACHE_L2X0
1298	help
1299	   The PL310 L2 cache controller implements three types of Clean &
1300	   Invalidate maintenance operations: by Physical Address
1301	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1302	   They are architecturally defined to behave as the execution of a
1303	   clean operation followed immediately by an invalidate operation,
1304	   both performing to the same memory location. This functionality
1305	   is not correctly implemented in PL310 as clean lines are not
1306	   invalidated as a result of these operations.
1307
1308config ARM_ERRATA_720789
1309	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1310	depends on CPU_V7
1311	help
1312	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1313	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1314	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1315	  As a consequence of this erratum, some TLB entries which should be
1316	  invalidated are not, resulting in an incoherency in the system page
1317	  tables. The workaround changes the TLB flushing routines to invalidate
1318	  entries regardless of the ASID.
1319
1320config PL310_ERRATA_727915
1321	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1322	depends on CACHE_L2X0
1323	help
1324	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1325	  operation (offset 0x7FC). This operation runs in background so that
1326	  PL310 can handle normal accesses while it is in progress. Under very
1327	  rare circumstances, due to this erratum, write data can be lost when
1328	  PL310 treats a cacheable write transaction during a Clean &
1329	  Invalidate by Way operation.
1330
1331config ARM_ERRATA_743622
1332	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1333	depends on CPU_V7
1334	depends on !ARCH_MULTIPLATFORM
1335	help
1336	  This option enables the workaround for the 743622 Cortex-A9
1337	  (r2p*) erratum. Under very rare conditions, a faulty
1338	  optimisation in the Cortex-A9 Store Buffer may lead to data
1339	  corruption. This workaround sets a specific bit in the diagnostic
1340	  register of the Cortex-A9 which disables the Store Buffer
1341	  optimisation, preventing the defect from occurring. This has no
1342	  visible impact on the overall performance or power consumption of the
1343	  processor.
1344
1345config ARM_ERRATA_751472
1346	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1347	depends on CPU_V7
1348	depends on !ARCH_MULTIPLATFORM
1349	help
1350	  This option enables the workaround for the 751472 Cortex-A9 (prior
1351	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1352	  completion of a following broadcasted operation if the second
1353	  operation is received by a CPU before the ICIALLUIS has completed,
1354	  potentially leading to corrupted entries in the cache or TLB.
1355
1356config PL310_ERRATA_753970
1357	bool "PL310 errata: cache sync operation may be faulty"
1358	depends on CACHE_PL310
1359	help
1360	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1361
1362	  Under some condition the effect of cache sync operation on
1363	  the store buffer still remains when the operation completes.
1364	  This means that the store buffer is always asked to drain and
1365	  this prevents it from merging any further writes. The workaround
1366	  is to replace the normal offset of cache sync operation (0x730)
1367	  by another offset targeting an unmapped PL310 register 0x740.
1368	  This has the same effect as the cache sync operation: store buffer
1369	  drain and waiting for all buffers empty.
1370
1371config ARM_ERRATA_754322
1372	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1373	depends on CPU_V7
1374	help
1375	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1376	  r3p*) erratum. A speculative memory access may cause a page table walk
1377	  which starts prior to an ASID switch but completes afterwards. This
1378	  can populate the micro-TLB with a stale entry which may be hit with
1379	  the new ASID. This workaround places two dsb instructions in the mm
1380	  switching code so that no page table walks can cross the ASID switch.
1381
1382config ARM_ERRATA_754327
1383	bool "ARM errata: no automatic Store Buffer drain"
1384	depends on CPU_V7 && SMP
1385	help
1386	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1387	  r2p0) erratum. The Store Buffer does not have any automatic draining
1388	  mechanism and therefore a livelock may occur if an external agent
1389	  continuously polls a memory location waiting to observe an update.
1390	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1391	  written polling loops from denying visibility of updates to memory.
1392
1393config ARM_ERRATA_364296
1394	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1395	depends on CPU_V6 && !SMP
1396	help
1397	  This options enables the workaround for the 364296 ARM1136
1398	  r0p2 erratum (possible cache data corruption with
1399	  hit-under-miss enabled). It sets the undocumented bit 31 in
1400	  the auxiliary control register and the FI bit in the control
1401	  register, thus disabling hit-under-miss without putting the
1402	  processor into full low interrupt latency mode. ARM11MPCore
1403	  is not affected.
1404
1405config ARM_ERRATA_764369
1406	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1407	depends on CPU_V7 && SMP
1408	help
1409	  This option enables the workaround for erratum 764369
1410	  affecting Cortex-A9 MPCore with two or more processors (all
1411	  current revisions). Under certain timing circumstances, a data
1412	  cache line maintenance operation by MVA targeting an Inner
1413	  Shareable memory region may fail to proceed up to either the
1414	  Point of Coherency or to the Point of Unification of the
1415	  system. This workaround adds a DSB instruction before the
1416	  relevant cache maintenance functions and sets a specific bit
1417	  in the diagnostic control register of the SCU.
1418
1419config PL310_ERRATA_769419
1420	bool "PL310 errata: no automatic Store Buffer drain"
1421	depends on CACHE_L2X0
1422	help
1423	  On revisions of the PL310 prior to r3p2, the Store Buffer does
1424	  not automatically drain. This can cause normal, non-cacheable
1425	  writes to be retained when the memory system is idle, leading
1426	  to suboptimal I/O performance for drivers using coherent DMA.
1427	  This option adds a write barrier to the cpu_idle loop so that,
1428	  on systems with an outer cache, the store buffer is drained
1429	  explicitly.
1430
1431config ARM_ERRATA_775420
1432       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1433       depends on CPU_V7
1434       help
1435	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1436	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1437	 operation aborts with MMU exception, it might cause the processor
1438	 to deadlock. This workaround puts DSB before executing ISB if
1439	 an abort may occur on cache maintenance.
1440
1441endmenu
1442
1443source "arch/arm/common/Kconfig"
1444
1445menu "Bus support"
1446
1447config ARM_AMBA
1448	bool
1449
1450config ISA
1451	bool
1452	help
1453	  Find out whether you have ISA slots on your motherboard.  ISA is the
1454	  name of a bus system, i.e. the way the CPU talks to the other stuff
1455	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1456	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1457	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1458
1459# Select ISA DMA controller support
1460config ISA_DMA
1461	bool
1462	select ISA_DMA_API
1463
1464config ARCH_NO_VIRT_TO_BUS
1465	def_bool y
1466	depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1467
1468# Select ISA DMA interface
1469config ISA_DMA_API
1470	bool
1471
1472config PCI
1473	bool "PCI support" if MIGHT_HAVE_PCI
1474	help
1475	  Find out whether you have a PCI motherboard. PCI is the name of a
1476	  bus system, i.e. the way the CPU talks to the other stuff inside
1477	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1478	  VESA. If you have PCI, say Y, otherwise N.
1479
1480config PCI_DOMAINS
1481	bool
1482	depends on PCI
1483
1484config PCI_NANOENGINE
1485	bool "BSE nanoEngine PCI support"
1486	depends on SA1100_NANOENGINE
1487	help
1488	  Enable PCI on the BSE nanoEngine board.
1489
1490config PCI_SYSCALL
1491	def_bool PCI
1492
1493# Select the host bridge type
1494config PCI_HOST_VIA82C505
1495	bool
1496	depends on PCI && ARCH_SHARK
1497	default y
1498
1499config PCI_HOST_ITE8152
1500	bool
1501	depends on PCI && MACH_ARMCORE
1502	default y
1503	select DMABOUNCE
1504
1505source "drivers/pci/Kconfig"
1506
1507source "drivers/pcmcia/Kconfig"
1508
1509endmenu
1510
1511menu "Kernel Features"
1512
1513config HAVE_SMP
1514	bool
1515	help
1516	  This option should be selected by machines which have an SMP-
1517	  capable CPU.
1518
1519	  The only effect of this option is to make the SMP-related
1520	  options available to the user for configuration.
1521
1522config SMP
1523	bool "Symmetric Multi-Processing"
1524	depends on CPU_V6K || CPU_V7
1525	depends on GENERIC_CLOCKEVENTS
1526	depends on HAVE_SMP
1527	depends on MMU
1528	select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1529	select USE_GENERIC_SMP_HELPERS
1530	help
1531	  This enables support for systems with more than one CPU. If you have
1532	  a system with only one CPU, like most personal computers, say N. If
1533	  you have a system with more than one CPU, say Y.
1534
1535	  If you say N here, the kernel will run on single and multiprocessor
1536	  machines, but will use only one CPU of a multiprocessor machine. If
1537	  you say Y here, the kernel will run on many, but not all, single
1538	  processor machines. On a single processor machine, the kernel will
1539	  run faster if you say N here.
1540
1541	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1542	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1543	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1544
1545	  If you don't know what to do here, say N.
1546
1547config SMP_ON_UP
1548	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1549	depends on SMP && !XIP_KERNEL
1550	default y
1551	help
1552	  SMP kernels contain instructions which fail on non-SMP processors.
1553	  Enabling this option allows the kernel to modify itself to make
1554	  these instructions safe.  Disabling it allows about 1K of space
1555	  savings.
1556
1557	  If you don't know what to do here, say Y.
1558
1559config ARM_CPU_TOPOLOGY
1560	bool "Support cpu topology definition"
1561	depends on SMP && CPU_V7
1562	default y
1563	help
1564	  Support ARM cpu topology definition. The MPIDR register defines
1565	  affinity between processors which is then used to describe the cpu
1566	  topology of an ARM System.
1567
1568config SCHED_MC
1569	bool "Multi-core scheduler support"
1570	depends on ARM_CPU_TOPOLOGY
1571	help
1572	  Multi-core scheduler support improves the CPU scheduler's decision
1573	  making when dealing with multi-core CPU chips at a cost of slightly
1574	  increased overhead in some places. If unsure say N here.
1575
1576config SCHED_SMT
1577	bool "SMT scheduler support"
1578	depends on ARM_CPU_TOPOLOGY
1579	help
1580	  Improves the CPU scheduler's decision making when dealing with
1581	  MultiThreading at a cost of slightly increased overhead in some
1582	  places. If unsure say N here.
1583
1584config HAVE_ARM_SCU
1585	bool
1586	help
1587	  This option enables support for the ARM system coherency unit
1588
1589config HAVE_ARM_ARCH_TIMER
1590	bool "Architected timer support"
1591	depends on CPU_V7
1592	select ARM_ARCH_TIMER
1593	help
1594	  This option enables support for the ARM architected timer
1595
1596config HAVE_ARM_TWD
1597	bool
1598	depends on SMP
1599	help
1600	  This options enables support for the ARM timer and watchdog unit
1601
1602choice
1603	prompt "Memory split"
1604	default VMSPLIT_3G
1605	help
1606	  Select the desired split between kernel and user memory.
1607
1608	  If you are not absolutely sure what you are doing, leave this
1609	  option alone!
1610
1611	config VMSPLIT_3G
1612		bool "3G/1G user/kernel split"
1613	config VMSPLIT_2G
1614		bool "2G/2G user/kernel split"
1615	config VMSPLIT_1G
1616		bool "1G/3G user/kernel split"
1617endchoice
1618
1619config PAGE_OFFSET
1620	hex
1621	default 0x40000000 if VMSPLIT_1G
1622	default 0x80000000 if VMSPLIT_2G
1623	default 0xC0000000
1624
1625config NR_CPUS
1626	int "Maximum number of CPUs (2-32)"
1627	range 2 32
1628	depends on SMP
1629	default "4"
1630
1631config HOTPLUG_CPU
1632	bool "Support for hot-pluggable CPUs"
1633	depends on SMP && HOTPLUG
1634	help
1635	  Say Y here to experiment with turning CPUs off and on.  CPUs
1636	  can be controlled through /sys/devices/system/cpu.
1637
1638config ARM_PSCI
1639	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1640	depends on CPU_V7
1641	help
1642	  Say Y here if you want Linux to communicate with system firmware
1643	  implementing the PSCI specification for CPU-centric power
1644	  management operations described in ARM document number ARM DEN
1645	  0022A ("Power State Coordination Interface System Software on
1646	  ARM processors").
1647
1648config LOCAL_TIMERS
1649	bool "Use local timer interrupts"
1650	depends on SMP
1651	default y
1652	select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1653	help
1654	  Enable support for local timers on SMP platforms, rather then the
1655	  legacy IPI broadcast method.  Local timers allows the system
1656	  accounting to be spread across the timer interval, preventing a
1657	  "thundering herd" at every timer tick.
1658
1659# The GPIO number here must be sorted by descending number. In case of
1660# a multiplatform kernel, we just want the highest value required by the
1661# selected platforms.
1662config ARCH_NR_GPIO
1663	int
1664	default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1665	default 512 if SOC_OMAP5
1666	default 355 if ARCH_U8500
1667	default 288 if ARCH_VT8500 || ARCH_SUNXI
1668	default 264 if MACH_H4700
1669	default 0
1670	help
1671	  Maximum number of GPIOs in the system.
1672
1673	  If unsure, leave the default value.
1674
1675source kernel/Kconfig.preempt
1676
1677config HZ
1678	int
1679	default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1680		ARCH_S5PV210 || ARCH_EXYNOS4
1681	default AT91_TIMER_HZ if ARCH_AT91
1682	default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1683	default 100
1684
1685config SCHED_HRTICK
1686	def_bool HIGH_RES_TIMERS
1687
1688config THUMB2_KERNEL
1689	bool "Compile the kernel in Thumb-2 mode"
1690	depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1691	select AEABI
1692	select ARM_ASM_UNIFIED
1693	select ARM_UNWIND
1694	help
1695	  By enabling this option, the kernel will be compiled in
1696	  Thumb-2 mode. A compiler/assembler that understand the unified
1697	  ARM-Thumb syntax is needed.
1698
1699	  If unsure, say N.
1700
1701config THUMB2_AVOID_R_ARM_THM_JUMP11
1702	bool "Work around buggy Thumb-2 short branch relocations in gas"
1703	depends on THUMB2_KERNEL && MODULES
1704	default y
1705	help
1706	  Various binutils versions can resolve Thumb-2 branches to
1707	  locally-defined, preemptible global symbols as short-range "b.n"
1708	  branch instructions.
1709
1710	  This is a problem, because there's no guarantee the final
1711	  destination of the symbol, or any candidate locations for a
1712	  trampoline, are within range of the branch.  For this reason, the
1713	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1714	  relocation in modules at all, and it makes little sense to add
1715	  support.
1716
1717	  The symptom is that the kernel fails with an "unsupported
1718	  relocation" error when loading some modules.
1719
1720	  Until fixed tools are available, passing
1721	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1722	  code which hits this problem, at the cost of a bit of extra runtime
1723	  stack usage in some cases.
1724
1725	  The problem is described in more detail at:
1726	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1727
1728	  Only Thumb-2 kernels are affected.
1729
1730	  Unless you are sure your tools don't have this problem, say Y.
1731
1732config ARM_ASM_UNIFIED
1733	bool
1734
1735config AEABI
1736	bool "Use the ARM EABI to compile the kernel"
1737	help
1738	  This option allows for the kernel to be compiled using the latest
1739	  ARM ABI (aka EABI).  This is only useful if you are using a user
1740	  space environment that is also compiled with EABI.
1741
1742	  Since there are major incompatibilities between the legacy ABI and
1743	  EABI, especially with regard to structure member alignment, this
1744	  option also changes the kernel syscall calling convention to
1745	  disambiguate both ABIs and allow for backward compatibility support
1746	  (selected with CONFIG_OABI_COMPAT).
1747
1748	  To use this you need GCC version 4.0.0 or later.
1749
1750config OABI_COMPAT
1751	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1752	depends on AEABI && !THUMB2_KERNEL
1753	default y
1754	help
1755	  This option preserves the old syscall interface along with the
1756	  new (ARM EABI) one. It also provides a compatibility layer to
1757	  intercept syscalls that have structure arguments which layout
1758	  in memory differs between the legacy ABI and the new ARM EABI
1759	  (only for non "thumb" binaries). This option adds a tiny
1760	  overhead to all syscalls and produces a slightly larger kernel.
1761	  If you know you'll be using only pure EABI user space then you
1762	  can say N here. If this option is not selected and you attempt
1763	  to execute a legacy ABI binary then the result will be
1764	  UNPREDICTABLE (in fact it can be predicted that it won't work
1765	  at all). If in doubt say Y.
1766
1767config ARCH_HAS_HOLES_MEMORYMODEL
1768	bool
1769
1770config ARCH_SPARSEMEM_ENABLE
1771	bool
1772
1773config ARCH_SPARSEMEM_DEFAULT
1774	def_bool ARCH_SPARSEMEM_ENABLE
1775
1776config ARCH_SELECT_MEMORY_MODEL
1777	def_bool ARCH_SPARSEMEM_ENABLE
1778
1779config HAVE_ARCH_PFN_VALID
1780	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1781
1782config HIGHMEM
1783	bool "High Memory Support"
1784	depends on MMU
1785	help
1786	  The address space of ARM processors is only 4 Gigabytes large
1787	  and it has to accommodate user address space, kernel address
1788	  space as well as some memory mapped IO. That means that, if you
1789	  have a large amount of physical memory and/or IO, not all of the
1790	  memory can be "permanently mapped" by the kernel. The physical
1791	  memory that is not permanently mapped is called "high memory".
1792
1793	  Depending on the selected kernel/user memory split, minimum
1794	  vmalloc space and actual amount of RAM, you may not need this
1795	  option which should result in a slightly faster kernel.
1796
1797	  If unsure, say n.
1798
1799config HIGHPTE
1800	bool "Allocate 2nd-level pagetables from highmem"
1801	depends on HIGHMEM
1802
1803config HW_PERF_EVENTS
1804	bool "Enable hardware performance counter support for perf events"
1805	depends on PERF_EVENTS
1806	default y
1807	help
1808	  Enable hardware performance counter support for perf events. If
1809	  disabled, perf events will use software events only.
1810
1811source "mm/Kconfig"
1812
1813config FORCE_MAX_ZONEORDER
1814	int "Maximum zone order" if ARCH_SHMOBILE
1815	range 11 64 if ARCH_SHMOBILE
1816	default "12" if SOC_AM33XX
1817	default "9" if SA1111
1818	default "11"
1819	help
1820	  The kernel memory allocator divides physically contiguous memory
1821	  blocks into "zones", where each zone is a power of two number of
1822	  pages.  This option selects the largest power of two that the kernel
1823	  keeps in the memory allocator.  If you need to allocate very large
1824	  blocks of physically contiguous memory, then you may need to
1825	  increase this value.
1826
1827	  This config option is actually maximum order plus one. For example,
1828	  a value of 11 means that the largest free memory block is 2^10 pages.
1829
1830config ALIGNMENT_TRAP
1831	bool
1832	depends on CPU_CP15_MMU
1833	default y if !ARCH_EBSA110
1834	select HAVE_PROC_CPU if PROC_FS
1835	help
1836	  ARM processors cannot fetch/store information which is not
1837	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1838	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1839	  fetch/store instructions will be emulated in software if you say
1840	  here, which has a severe performance impact. This is necessary for
1841	  correct operation of some network protocols. With an IP-only
1842	  configuration it is safe to say N, otherwise say Y.
1843
1844config UACCESS_WITH_MEMCPY
1845	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1846	depends on MMU
1847	default y if CPU_FEROCEON
1848	help
1849	  Implement faster copy_to_user and clear_user methods for CPU
1850	  cores where a 8-word STM instruction give significantly higher
1851	  memory write throughput than a sequence of individual 32bit stores.
1852
1853	  A possible side effect is a slight increase in scheduling latency
1854	  between threads sharing the same address space if they invoke
1855	  such copy operations with large buffers.
1856
1857	  However, if the CPU data cache is using a write-allocate mode,
1858	  this option is unlikely to provide any performance gain.
1859
1860config SECCOMP
1861	bool
1862	prompt "Enable seccomp to safely compute untrusted bytecode"
1863	---help---
1864	  This kernel feature is useful for number crunching applications
1865	  that may need to compute untrusted bytecode during their
1866	  execution. By using pipes or other transports made available to
1867	  the process as file descriptors supporting the read/write
1868	  syscalls, it's possible to isolate those applications in
1869	  their own address space using seccomp. Once seccomp is
1870	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1871	  and the task is only allowed to execute a few safe syscalls
1872	  defined by each seccomp mode.
1873
1874config CC_STACKPROTECTOR
1875	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1876	help
1877	  This option turns on the -fstack-protector GCC feature. This
1878	  feature puts, at the beginning of functions, a canary value on
1879	  the stack just before the return address, and validates
1880	  the value just before actually returning.  Stack based buffer
1881	  overflows (that need to overwrite this return address) now also
1882	  overwrite the canary, which gets detected and the attack is then
1883	  neutralized via a kernel panic.
1884	  This feature requires gcc version 4.2 or above.
1885
1886config XEN_DOM0
1887	def_bool y
1888	depends on XEN
1889
1890config XEN
1891	bool "Xen guest support on ARM (EXPERIMENTAL)"
1892	depends on ARM && AEABI && OF
1893	depends on CPU_V7 && !CPU_V6
1894	depends on !GENERIC_ATOMIC64
1895	help
1896	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1897
1898endmenu
1899
1900menu "Boot options"
1901
1902config USE_OF
1903	bool "Flattened Device Tree support"
1904	select IRQ_DOMAIN
1905	select OF
1906	select OF_EARLY_FLATTREE
1907	help
1908	  Include support for flattened device tree machine descriptions.
1909
1910config ATAGS
1911	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1912	default y
1913	help
1914	  This is the traditional way of passing data to the kernel at boot
1915	  time. If you are solely relying on the flattened device tree (or
1916	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1917	  to remove ATAGS support from your kernel binary.  If unsure,
1918	  leave this to y.
1919
1920config DEPRECATED_PARAM_STRUCT
1921	bool "Provide old way to pass kernel parameters"
1922	depends on ATAGS
1923	help
1924	  This was deprecated in 2001 and announced to live on for 5 years.
1925	  Some old boot loaders still use this way.
1926
1927# Compressed boot loader in ROM.  Yes, we really want to ask about
1928# TEXT and BSS so we preserve their values in the config files.
1929config ZBOOT_ROM_TEXT
1930	hex "Compressed ROM boot loader base address"
1931	default "0"
1932	help
1933	  The physical address at which the ROM-able zImage is to be
1934	  placed in the target.  Platforms which normally make use of
1935	  ROM-able zImage formats normally set this to a suitable
1936	  value in their defconfig file.
1937
1938	  If ZBOOT_ROM is not enabled, this has no effect.
1939
1940config ZBOOT_ROM_BSS
1941	hex "Compressed ROM boot loader BSS address"
1942	default "0"
1943	help
1944	  The base address of an area of read/write memory in the target
1945	  for the ROM-able zImage which must be available while the
1946	  decompressor is running. It must be large enough to hold the
1947	  entire decompressed kernel plus an additional 128 KiB.
1948	  Platforms which normally make use of ROM-able zImage formats
1949	  normally set this to a suitable value in their defconfig file.
1950
1951	  If ZBOOT_ROM is not enabled, this has no effect.
1952
1953config ZBOOT_ROM
1954	bool "Compressed boot loader in ROM/flash"
1955	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1956	help
1957	  Say Y here if you intend to execute your compressed kernel image
1958	  (zImage) directly from ROM or flash.  If unsure, say N.
1959
1960choice
1961	prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1962	depends on ZBOOT_ROM && ARCH_SH7372
1963	default ZBOOT_ROM_NONE
1964	help
1965	  Include experimental SD/MMC loading code in the ROM-able zImage.
1966	  With this enabled it is possible to write the ROM-able zImage
1967	  kernel image to an MMC or SD card and boot the kernel straight
1968	  from the reset vector. At reset the processor Mask ROM will load
1969	  the first part of the ROM-able zImage which in turn loads the
1970	  rest the kernel image to RAM.
1971
1972config ZBOOT_ROM_NONE
1973	bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1974	help
1975	  Do not load image from SD or MMC
1976
1977config ZBOOT_ROM_MMCIF
1978	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1979	help
1980	  Load image from MMCIF hardware block.
1981
1982config ZBOOT_ROM_SH_MOBILE_SDHI
1983	bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1984	help
1985	  Load image from SDHI hardware block
1986
1987endchoice
1988
1989config ARM_APPENDED_DTB
1990	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1991	depends on OF && !ZBOOT_ROM
1992	help
1993	  With this option, the boot code will look for a device tree binary
1994	  (DTB) appended to zImage
1995	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1996
1997	  This is meant as a backward compatibility convenience for those
1998	  systems with a bootloader that can't be upgraded to accommodate
1999	  the documented boot protocol using a device tree.
2000
2001	  Beware that there is very little in terms of protection against
2002	  this option being confused by leftover garbage in memory that might
2003	  look like a DTB header after a reboot if no actual DTB is appended
2004	  to zImage.  Do not leave this option active in a production kernel
2005	  if you don't intend to always append a DTB.  Proper passing of the
2006	  location into r2 of a bootloader provided DTB is always preferable
2007	  to this option.
2008
2009config ARM_ATAG_DTB_COMPAT
2010	bool "Supplement the appended DTB with traditional ATAG information"
2011	depends on ARM_APPENDED_DTB
2012	help
2013	  Some old bootloaders can't be updated to a DTB capable one, yet
2014	  they provide ATAGs with memory configuration, the ramdisk address,
2015	  the kernel cmdline string, etc.  Such information is dynamically
2016	  provided by the bootloader and can't always be stored in a static
2017	  DTB.  To allow a device tree enabled kernel to be used with such
2018	  bootloaders, this option allows zImage to extract the information
2019	  from the ATAG list and store it at run time into the appended DTB.
2020
2021choice
2022	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2023	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2024
2025config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2026	bool "Use bootloader kernel arguments if available"
2027	help
2028	  Uses the command-line options passed by the boot loader instead of
2029	  the device tree bootargs property. If the boot loader doesn't provide
2030	  any, the device tree bootargs property will be used.
2031
2032config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2033	bool "Extend with bootloader kernel arguments"
2034	help
2035	  The command-line arguments provided by the boot loader will be
2036	  appended to the the device tree bootargs property.
2037
2038endchoice
2039
2040config CMDLINE
2041	string "Default kernel command string"
2042	default ""
2043	help
2044	  On some architectures (EBSA110 and CATS), there is currently no way
2045	  for the boot loader to pass arguments to the kernel. For these
2046	  architectures, you should supply some command-line options at build
2047	  time by entering them here. As a minimum, you should specify the
2048	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
2049
2050choice
2051	prompt "Kernel command line type" if CMDLINE != ""
2052	default CMDLINE_FROM_BOOTLOADER
2053	depends on ATAGS
2054
2055config CMDLINE_FROM_BOOTLOADER
2056	bool "Use bootloader kernel arguments if available"
2057	help
2058	  Uses the command-line options passed by the boot loader. If
2059	  the boot loader doesn't provide any, the default kernel command
2060	  string provided in CMDLINE will be used.
2061
2062config CMDLINE_EXTEND
2063	bool "Extend bootloader kernel arguments"
2064	help
2065	  The command-line arguments provided by the boot loader will be
2066	  appended to the default kernel command string.
2067
2068config CMDLINE_FORCE
2069	bool "Always use the default kernel command string"
2070	help
2071	  Always use the default kernel command string, even if the boot
2072	  loader passes other arguments to the kernel.
2073	  This is useful if you cannot or don't want to change the
2074	  command-line options your boot loader passes to the kernel.
2075endchoice
2076
2077config XIP_KERNEL
2078	bool "Kernel Execute-In-Place from ROM"
2079	depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2080	help
2081	  Execute-In-Place allows the kernel to run from non-volatile storage
2082	  directly addressable by the CPU, such as NOR flash. This saves RAM
2083	  space since the text section of the kernel is not loaded from flash
2084	  to RAM.  Read-write sections, such as the data section and stack,
2085	  are still copied to RAM.  The XIP kernel is not compressed since
2086	  it has to run directly from flash, so it will take more space to
2087	  store it.  The flash address used to link the kernel object files,
2088	  and for storing it, is configuration dependent. Therefore, if you
2089	  say Y here, you must know the proper physical address where to
2090	  store the kernel image depending on your own flash memory usage.
2091
2092	  Also note that the make target becomes "make xipImage" rather than
2093	  "make zImage" or "make Image".  The final kernel binary to put in
2094	  ROM memory will be arch/arm/boot/xipImage.
2095
2096	  If unsure, say N.
2097
2098config XIP_PHYS_ADDR
2099	hex "XIP Kernel Physical Location"
2100	depends on XIP_KERNEL
2101	default "0x00080000"
2102	help
2103	  This is the physical address in your flash memory the kernel will
2104	  be linked for and stored to.  This address is dependent on your
2105	  own flash usage.
2106
2107config KEXEC
2108	bool "Kexec system call (EXPERIMENTAL)"
2109	depends on (!SMP || HOTPLUG_CPU)
2110	help
2111	  kexec is a system call that implements the ability to shutdown your
2112	  current kernel, and to start another kernel.  It is like a reboot
2113	  but it is independent of the system firmware.   And like a reboot
2114	  you can start any kernel with it, not just Linux.
2115
2116	  It is an ongoing process to be certain the hardware in a machine
2117	  is properly shutdown, so do not be surprised if this code does not
2118	  initially work for you.  It may help to enable device hotplugging
2119	  support.
2120
2121config ATAGS_PROC
2122	bool "Export atags in procfs"
2123	depends on ATAGS && KEXEC
2124	default y
2125	help
2126	  Should the atags used to boot the kernel be exported in an "atags"
2127	  file in procfs. Useful with kexec.
2128
2129config CRASH_DUMP
2130	bool "Build kdump crash kernel (EXPERIMENTAL)"
2131	help
2132	  Generate crash dump after being started by kexec. This should
2133	  be normally only set in special crash dump kernels which are
2134	  loaded in the main kernel with kexec-tools into a specially
2135	  reserved region and then later executed after a crash by
2136	  kdump/kexec. The crash dump kernel must be compiled to a
2137	  memory address not used by the main kernel
2138
2139	  For more details see Documentation/kdump/kdump.txt
2140
2141config AUTO_ZRELADDR
2142	bool "Auto calculation of the decompressed kernel image address"
2143	depends on !ZBOOT_ROM && !ARCH_U300
2144	help
2145	  ZRELADDR is the physical address where the decompressed kernel
2146	  image will be placed. If AUTO_ZRELADDR is selected, the address
2147	  will be determined at run-time by masking the current IP with
2148	  0xf8000000. This assumes the zImage being placed in the first 128MB
2149	  from start of memory.
2150
2151endmenu
2152
2153menu "CPU Power Management"
2154
2155if ARCH_HAS_CPUFREQ
2156
2157source "drivers/cpufreq/Kconfig"
2158
2159config CPU_FREQ_IMX
2160	tristate "CPUfreq driver for i.MX CPUs"
2161	depends on ARCH_MXC && CPU_FREQ
2162	select CPU_FREQ_TABLE
2163	help
2164	  This enables the CPUfreq driver for i.MX CPUs.
2165
2166config CPU_FREQ_SA1100
2167	bool
2168
2169config CPU_FREQ_SA1110
2170	bool
2171
2172config CPU_FREQ_INTEGRATOR
2173	tristate "CPUfreq driver for ARM Integrator CPUs"
2174	depends on ARCH_INTEGRATOR && CPU_FREQ
2175	default y
2176	help
2177	  This enables the CPUfreq driver for ARM Integrator CPUs.
2178
2179	  For details, take a look at <file:Documentation/cpu-freq>.
2180
2181	  If in doubt, say Y.
2182
2183config CPU_FREQ_PXA
2184	bool
2185	depends on CPU_FREQ && ARCH_PXA && PXA25x
2186	default y
2187	select CPU_FREQ_DEFAULT_GOV_USERSPACE
2188	select CPU_FREQ_TABLE
2189
2190config CPU_FREQ_S3C
2191	bool
2192	help
2193	  Internal configuration node for common cpufreq on Samsung SoC
2194
2195config CPU_FREQ_S3C24XX
2196	bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2197	depends on ARCH_S3C24XX && CPU_FREQ
2198	select CPU_FREQ_S3C
2199	help
2200	  This enables the CPUfreq driver for the Samsung S3C24XX family
2201	  of CPUs.
2202
2203	  For details, take a look at <file:Documentation/cpu-freq>.
2204
2205	  If in doubt, say N.
2206
2207config CPU_FREQ_S3C24XX_PLL
2208	bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2209	depends on CPU_FREQ_S3C24XX
2210	help
2211	  Compile in support for changing the PLL frequency from the
2212	  S3C24XX series CPUfreq driver. The PLL takes time to settle
2213	  after a frequency change, so by default it is not enabled.
2214
2215	  This also means that the PLL tables for the selected CPU(s) will
2216	  be built which may increase the size of the kernel image.
2217
2218config CPU_FREQ_S3C24XX_DEBUG
2219	bool "Debug CPUfreq Samsung driver core"
2220	depends on CPU_FREQ_S3C24XX
2221	help
2222	  Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2223
2224config CPU_FREQ_S3C24XX_IODEBUG
2225	bool "Debug CPUfreq Samsung driver IO timing"
2226	depends on CPU_FREQ_S3C24XX
2227	help
2228	  Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2229
2230config CPU_FREQ_S3C24XX_DEBUGFS
2231	bool "Export debugfs for CPUFreq"
2232	depends on CPU_FREQ_S3C24XX && DEBUG_FS
2233	help
2234	  Export status information via debugfs.
2235
2236endif
2237
2238source "drivers/cpuidle/Kconfig"
2239
2240endmenu
2241
2242menu "Floating point emulation"
2243
2244comment "At least one emulation must be selected"
2245
2246config FPE_NWFPE
2247	bool "NWFPE math emulation"
2248	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2249	---help---
2250	  Say Y to include the NWFPE floating point emulator in the kernel.
2251	  This is necessary to run most binaries. Linux does not currently
2252	  support floating point hardware so you need to say Y here even if
2253	  your machine has an FPA or floating point co-processor podule.
2254
2255	  You may say N here if you are going to load the Acorn FPEmulator
2256	  early in the bootup.
2257
2258config FPE_NWFPE_XP
2259	bool "Support extended precision"
2260	depends on FPE_NWFPE
2261	help
2262	  Say Y to include 80-bit support in the kernel floating-point
2263	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2264	  Note that gcc does not generate 80-bit operations by default,
2265	  so in most cases this option only enlarges the size of the
2266	  floating point emulator without any good reason.
2267
2268	  You almost surely want to say N here.
2269
2270config FPE_FASTFPE
2271	bool "FastFPE math emulation (EXPERIMENTAL)"
2272	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2273	---help---
2274	  Say Y here to include the FAST floating point emulator in the kernel.
2275	  This is an experimental much faster emulator which now also has full
2276	  precision for the mantissa.  It does not support any exceptions.
2277	  It is very simple, and approximately 3-6 times faster than NWFPE.
2278
2279	  It should be sufficient for most programs.  It may be not suitable
2280	  for scientific calculations, but you have to check this for yourself.
2281	  If you do not feel you need a faster FP emulation you should better
2282	  choose NWFPE.
2283
2284config VFP
2285	bool "VFP-format floating point maths"
2286	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2287	help
2288	  Say Y to include VFP support code in the kernel. This is needed
2289	  if your hardware includes a VFP unit.
2290
2291	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2292	  release notes and additional status information.
2293
2294	  Say N if your target does not have VFP hardware.
2295
2296config VFPv3
2297	bool
2298	depends on VFP
2299	default y if CPU_V7
2300
2301config NEON
2302	bool "Advanced SIMD (NEON) Extension support"
2303	depends on VFPv3 && CPU_V7
2304	help
2305	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2306	  Extension.
2307
2308endmenu
2309
2310menu "Userspace binary formats"
2311
2312source "fs/Kconfig.binfmt"
2313
2314config ARTHUR
2315	tristate "RISC OS personality"
2316	depends on !AEABI
2317	help
2318	  Say Y here to include the kernel code necessary if you want to run
2319	  Acorn RISC OS/Arthur binaries under Linux. This code is still very
2320	  experimental; if this sounds frightening, say N and sleep in peace.
2321	  You can also say M here to compile this support as a module (which
2322	  will be called arthur).
2323
2324endmenu
2325
2326menu "Power management options"
2327
2328source "kernel/power/Kconfig"
2329
2330config ARCH_SUSPEND_POSSIBLE
2331	depends on !ARCH_S5PC100
2332	depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2333		CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2334	def_bool y
2335
2336config ARM_CPU_SUSPEND
2337	def_bool PM_SLEEP
2338
2339endmenu
2340
2341source "net/Kconfig"
2342
2343source "drivers/Kconfig"
2344
2345source "fs/Kconfig"
2346
2347source "arch/arm/Kconfig.debug"
2348
2349source "security/Kconfig"
2350
2351source "crypto/Kconfig"
2352
2353source "lib/Kconfig"
2354
2355source "arch/arm/kvm/Kconfig"
2356