1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select ARCH_WANT_LD_ORPHAN_WARN 39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 40 select BUILDTIME_TABLE_SORT if MMU 41 select CLONE_BACKWARDS 42 select CPU_PM if SUSPEND || CPU_IDLE 43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 44 select DMA_DECLARE_COHERENT 45 select DMA_OPS 46 select DMA_REMAP if MMU 47 select EDAC_SUPPORT 48 select EDAC_ATOMIC_SCRUB 49 select GENERIC_ALLOCATOR 50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 53 select GENERIC_IRQ_IPI if SMP 54 select GENERIC_CPU_AUTOPROBE 55 select GENERIC_EARLY_IOREMAP 56 select GENERIC_IDLE_POLL_SETUP 57 select GENERIC_IRQ_PROBE 58 select GENERIC_IRQ_SHOW 59 select GENERIC_IRQ_SHOW_LEVEL 60 select GENERIC_LIB_DEVMEM_IS_ALLOWED 61 select GENERIC_PCI_IOMAP 62 select GENERIC_SCHED_CLOCK 63 select GENERIC_SMP_IDLE_THREAD 64 select GENERIC_STRNCPY_FROM_USER 65 select GENERIC_STRNLEN_USER 66 select HANDLE_DOMAIN_IRQ 67 select HARDIRQS_SW_RESEND 68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 73 select HAVE_ARCH_MMAP_RND_BITS if MMU 74 select HAVE_ARCH_PFN_VALID 75 select HAVE_ARCH_SECCOMP 76 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 77 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 78 select HAVE_ARCH_TRACEHOOK 79 select HAVE_ARM_SMCCC if CPU_V7 80 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 81 select HAVE_CONTEXT_TRACKING 82 select HAVE_C_RECORDMCOUNT 83 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 84 select HAVE_DMA_CONTIGUOUS if MMU 85 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 86 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 87 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 88 select HAVE_EXIT_THREAD 89 select HAVE_FAST_GUP if ARM_LPAE 90 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 91 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 92 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 93 select HAVE_GCC_PLUGINS 94 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 95 select HAVE_IDE if PCI || ISA || PCMCIA 96 select HAVE_IRQ_TIME_ACCOUNTING 97 select HAVE_KERNEL_GZIP 98 select HAVE_KERNEL_LZ4 99 select HAVE_KERNEL_LZMA 100 select HAVE_KERNEL_LZO 101 select HAVE_KERNEL_XZ 102 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 103 select HAVE_KRETPROBES if HAVE_KPROBES 104 select HAVE_MOD_ARCH_SPECIFIC 105 select HAVE_NMI 106 select HAVE_OPTPROBES if !THUMB2_KERNEL 107 select HAVE_PERF_EVENTS 108 select HAVE_PERF_REGS 109 select HAVE_PERF_USER_STACK_DUMP 110 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 111 select HAVE_REGS_AND_STACK_ACCESS_API 112 select HAVE_RSEQ 113 select HAVE_STACKPROTECTOR 114 select HAVE_SYSCALL_TRACEPOINTS 115 select HAVE_UID16 116 select HAVE_VIRT_CPU_ACCOUNTING_GEN 117 select IRQ_FORCED_THREADING 118 select MODULES_USE_ELF_REL 119 select NEED_DMA_MAP_STATE 120 select OF_EARLY_FLATTREE if OF 121 select OLD_SIGACTION 122 select OLD_SIGSUSPEND3 123 select PCI_SYSCALL if PCI 124 select PERF_USE_VMALLOC 125 select RTC_LIB 126 select SET_FS 127 select SYS_SUPPORTS_APM_EMULATION 128 # Above selects are sorted alphabetically; please add new ones 129 # according to that. Thanks. 130 help 131 The ARM series is a line of low-power-consumption RISC chip designs 132 licensed by ARM Ltd and targeted at embedded applications and 133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 134 manufactured, but legacy ARM-based PC hardware remains popular in 135 Europe. There is an ARM Linux project with a web page at 136 <http://www.arm.linux.org.uk/>. 137 138config ARM_HAS_SG_CHAIN 139 bool 140 141config ARM_DMA_USE_IOMMU 142 bool 143 select ARM_HAS_SG_CHAIN 144 select NEED_SG_DMA_LENGTH 145 146if ARM_DMA_USE_IOMMU 147 148config ARM_DMA_IOMMU_ALIGNMENT 149 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 150 range 4 9 151 default 8 152 help 153 DMA mapping framework by default aligns all buffers to the smallest 154 PAGE_SIZE order which is greater than or equal to the requested buffer 155 size. This works well for buffers up to a few hundreds kilobytes, but 156 for larger buffers it just a waste of address space. Drivers which has 157 relatively small addressing window (like 64Mib) might run out of 158 virtual space with just a few allocations. 159 160 With this parameter you can specify the maximum PAGE_SIZE order for 161 DMA IOMMU buffers. Larger buffers will be aligned only to this 162 specified order. The order is expressed as a power of two multiplied 163 by the PAGE_SIZE. 164 165endif 166 167config SYS_SUPPORTS_APM_EMULATION 168 bool 169 170config HAVE_TCM 171 bool 172 select GENERIC_ALLOCATOR 173 174config HAVE_PROC_CPU 175 bool 176 177config NO_IOPORT_MAP 178 bool 179 180config SBUS 181 bool 182 183config STACKTRACE_SUPPORT 184 bool 185 default y 186 187config LOCKDEP_SUPPORT 188 bool 189 default y 190 191config TRACE_IRQFLAGS_SUPPORT 192 bool 193 default !CPU_V7M 194 195config ARCH_HAS_ILOG2_U32 196 bool 197 198config ARCH_HAS_ILOG2_U64 199 bool 200 201config ARCH_HAS_BANDGAP 202 bool 203 204config FIX_EARLYCON_MEM 205 def_bool y if MMU 206 207config GENERIC_HWEIGHT 208 bool 209 default y 210 211config GENERIC_CALIBRATE_DELAY 212 bool 213 default y 214 215config ARCH_MAY_HAVE_PC_FDC 216 bool 217 218config ZONE_DMA 219 bool 220 221config ARCH_SUPPORTS_UPROBES 222 def_bool y 223 224config ARCH_HAS_DMA_SET_COHERENT_MASK 225 bool 226 227config GENERIC_ISA_DMA 228 bool 229 230config FIQ 231 bool 232 233config NEED_RET_TO_USER 234 bool 235 236config ARCH_MTD_XIP 237 bool 238 239config ARM_PATCH_PHYS_VIRT 240 bool "Patch physical to virtual translations at runtime" if EMBEDDED 241 default y 242 depends on !XIP_KERNEL && MMU 243 help 244 Patch phys-to-virt and virt-to-phys translation functions at 245 boot and module load time according to the position of the 246 kernel in system memory. 247 248 This can only be used with non-XIP MMU kernels where the base 249 of physical memory is at a 2 MiB boundary. 250 251 Only disable this option if you know that you do not require 252 this feature (eg, building a kernel for a single machine) and 253 you need to shrink the kernel to the minimal size. 254 255config NEED_MACH_IO_H 256 bool 257 help 258 Select this when mach/io.h is required to provide special 259 definitions for this platform. The need for mach/io.h should 260 be avoided when possible. 261 262config NEED_MACH_MEMORY_H 263 bool 264 help 265 Select this when mach/memory.h is required to provide special 266 definitions for this platform. The need for mach/memory.h should 267 be avoided when possible. 268 269config PHYS_OFFSET 270 hex "Physical address of main memory" if MMU 271 depends on !ARM_PATCH_PHYS_VIRT 272 default DRAM_BASE if !MMU 273 default 0x00000000 if ARCH_FOOTBRIDGE 274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 275 default 0x20000000 if ARCH_S5PV210 276 default 0xc0000000 if ARCH_SA1100 277 help 278 Please provide the physical address corresponding to the 279 location of main memory in your system. 280 281config GENERIC_BUG 282 def_bool y 283 depends on BUG 284 285config PGTABLE_LEVELS 286 int 287 default 3 if ARM_LPAE 288 default 2 289 290menu "System Type" 291 292config MMU 293 bool "MMU-based Paged Memory Management Support" 294 default y 295 help 296 Select if you want MMU-based virtualised addressing space 297 support by paged memory management. If unsure, say 'Y'. 298 299config ARCH_MMAP_RND_BITS_MIN 300 default 8 301 302config ARCH_MMAP_RND_BITS_MAX 303 default 14 if PAGE_OFFSET=0x40000000 304 default 15 if PAGE_OFFSET=0x80000000 305 default 16 306 307# 308# The "ARM system type" choice list is ordered alphabetically by option 309# text. Please add new entries in the option alphabetic order. 310# 311choice 312 prompt "ARM system type" 313 default ARM_SINGLE_ARMV7M if !MMU 314 default ARCH_MULTIPLATFORM if MMU 315 316config ARCH_MULTIPLATFORM 317 bool "Allow multiple platforms to be selected" 318 depends on MMU 319 select ARCH_FLATMEM_ENABLE 320 select ARCH_SPARSEMEM_ENABLE 321 select ARCH_SELECT_MEMORY_MODEL 322 select ARM_HAS_SG_CHAIN 323 select ARM_PATCH_PHYS_VIRT 324 select AUTO_ZRELADDR 325 select TIMER_OF 326 select COMMON_CLK 327 select GENERIC_IRQ_MULTI_HANDLER 328 select HAVE_PCI 329 select PCI_DOMAINS_GENERIC if PCI 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARM_NVIC 337 select AUTO_ZRELADDR 338 select TIMER_OF 339 select COMMON_CLK 340 select CPU_V7M 341 select NO_IOPORT_MAP 342 select SPARSE_IRQ 343 select USE_OF 344 345config ARCH_EP93XX 346 bool "EP93xx-based" 347 select ARCH_SPARSEMEM_ENABLE 348 select ARM_AMBA 349 imply ARM_PATCH_PHYS_VIRT 350 select ARM_VIC 351 select GENERIC_IRQ_MULTI_HANDLER 352 select AUTO_ZRELADDR 353 select CLKDEV_LOOKUP 354 select CLKSRC_MMIO 355 select CPU_ARM920T 356 select GPIOLIB 357 select HAVE_LEGACY_CLK 358 help 359 This enables support for the Cirrus EP93xx series of CPUs. 360 361config ARCH_FOOTBRIDGE 362 bool "FootBridge" 363 select CPU_SA110 364 select FOOTBRIDGE 365 select HAVE_IDE 366 select NEED_MACH_IO_H if !MMU 367 select NEED_MACH_MEMORY_H 368 help 369 Support for systems based on the DC21285 companion chip 370 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 371 372config ARCH_IOP32X 373 bool "IOP32x-based" 374 depends on MMU 375 select CPU_XSCALE 376 select GPIO_IOP 377 select GPIOLIB 378 select NEED_RET_TO_USER 379 select FORCE_PCI 380 select PLAT_IOP 381 help 382 Support for Intel's 80219 and IOP32X (XScale) family of 383 processors. 384 385config ARCH_IXP4XX 386 bool "IXP4xx-based" 387 depends on MMU 388 select ARCH_HAS_DMA_SET_COHERENT_MASK 389 select ARCH_SUPPORTS_BIG_ENDIAN 390 select CPU_XSCALE 391 select DMABOUNCE if PCI 392 select GENERIC_IRQ_MULTI_HANDLER 393 select GPIO_IXP4XX 394 select GPIOLIB 395 select HAVE_PCI 396 select IXP4XX_IRQ 397 select IXP4XX_TIMER 398 select NEED_MACH_IO_H 399 select USB_EHCI_BIG_ENDIAN_DESC 400 select USB_EHCI_BIG_ENDIAN_MMIO 401 help 402 Support for Intel's IXP4XX (XScale) family of processors. 403 404config ARCH_DOVE 405 bool "Marvell Dove" 406 select CPU_PJ4 407 select GENERIC_IRQ_MULTI_HANDLER 408 select GPIOLIB 409 select HAVE_PCI 410 select MVEBU_MBUS 411 select PINCTRL 412 select PINCTRL_DOVE 413 select PLAT_ORION_LEGACY 414 select SPARSE_IRQ 415 select PM_GENERIC_DOMAINS if PM 416 help 417 Support for the Marvell Dove SoC 88AP510 418 419config ARCH_PXA 420 bool "PXA2xx/PXA3xx-based" 421 depends on MMU 422 select ARCH_MTD_XIP 423 select ARM_CPU_SUSPEND if PM 424 select AUTO_ZRELADDR 425 select COMMON_CLK 426 select CLKSRC_PXA 427 select CLKSRC_MMIO 428 select TIMER_OF 429 select CPU_XSCALE if !CPU_XSC3 430 select GENERIC_IRQ_MULTI_HANDLER 431 select GPIO_PXA 432 select GPIOLIB 433 select HAVE_IDE 434 select IRQ_DOMAIN 435 select PLAT_PXA 436 select SPARSE_IRQ 437 help 438 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 439 440config ARCH_RPC 441 bool "RiscPC" 442 depends on MMU 443 select ARCH_ACORN 444 select ARCH_MAY_HAVE_PC_FDC 445 select ARCH_SPARSEMEM_ENABLE 446 select ARM_HAS_SG_CHAIN 447 select CPU_SA110 448 select FIQ 449 select HAVE_IDE 450 select HAVE_PATA_PLATFORM 451 select ISA_DMA_API 452 select LEGACY_TIMER_TICK 453 select NEED_MACH_IO_H 454 select NEED_MACH_MEMORY_H 455 select NO_IOPORT_MAP 456 help 457 On the Acorn Risc-PC, Linux can support the internal IDE disk and 458 CD-ROM interface, serial and parallel port, and the floppy drive. 459 460config ARCH_SA1100 461 bool "SA1100-based" 462 select ARCH_MTD_XIP 463 select ARCH_SPARSEMEM_ENABLE 464 select CLKSRC_MMIO 465 select CLKSRC_PXA 466 select TIMER_OF if OF 467 select COMMON_CLK 468 select CPU_FREQ 469 select CPU_SA1100 470 select GENERIC_IRQ_MULTI_HANDLER 471 select GPIOLIB 472 select HAVE_IDE 473 select IRQ_DOMAIN 474 select ISA 475 select NEED_MACH_MEMORY_H 476 select SPARSE_IRQ 477 help 478 Support for StrongARM 11x0 based boards. 479 480config ARCH_S3C24XX 481 bool "Samsung S3C24XX SoCs" 482 select ATAGS 483 select CLKSRC_SAMSUNG_PWM 484 select GPIO_SAMSUNG 485 select GPIOLIB 486 select GENERIC_IRQ_MULTI_HANDLER 487 select HAVE_S3C2410_I2C if I2C 488 select HAVE_S3C_RTC if RTC_CLASS 489 select NEED_MACH_IO_H 490 select S3C2410_WATCHDOG 491 select SAMSUNG_ATAGS 492 select USE_OF 493 select WATCHDOG 494 help 495 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 496 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 497 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 498 Samsung SMDK2410 development board (and derivatives). 499 500config ARCH_OMAP1 501 bool "TI OMAP1" 502 depends on MMU 503 select ARCH_OMAP 504 select CLKDEV_LOOKUP 505 select CLKSRC_MMIO 506 select GENERIC_IRQ_CHIP 507 select GENERIC_IRQ_MULTI_HANDLER 508 select GPIOLIB 509 select HAVE_IDE 510 select HAVE_LEGACY_CLK 511 select IRQ_DOMAIN 512 select NEED_MACH_IO_H if PCCARD 513 select NEED_MACH_MEMORY_H 514 select SPARSE_IRQ 515 help 516 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 517 518endchoice 519 520menu "Multiple platform selection" 521 depends on ARCH_MULTIPLATFORM 522 523comment "CPU Core family selection" 524 525config ARCH_MULTI_V4 526 bool "ARMv4 based platforms (FA526)" 527 depends on !ARCH_MULTI_V6_V7 528 select ARCH_MULTI_V4_V5 529 select CPU_FA526 530 531config ARCH_MULTI_V4T 532 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 533 depends on !ARCH_MULTI_V6_V7 534 select ARCH_MULTI_V4_V5 535 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 536 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 537 CPU_ARM925T || CPU_ARM940T) 538 539config ARCH_MULTI_V5 540 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 541 depends on !ARCH_MULTI_V6_V7 542 select ARCH_MULTI_V4_V5 543 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 544 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 545 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 546 547config ARCH_MULTI_V4_V5 548 bool 549 550config ARCH_MULTI_V6 551 bool "ARMv6 based platforms (ARM11)" 552 select ARCH_MULTI_V6_V7 553 select CPU_V6K 554 555config ARCH_MULTI_V7 556 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 557 default y 558 select ARCH_MULTI_V6_V7 559 select CPU_V7 560 select HAVE_SMP 561 562config ARCH_MULTI_V6_V7 563 bool 564 select MIGHT_HAVE_CACHE_L2X0 565 566config ARCH_MULTI_CPU_AUTO 567 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 568 select ARCH_MULTI_V5 569 570endmenu 571 572config ARCH_VIRT 573 bool "Dummy Virtual Machine" 574 depends on ARCH_MULTI_V7 575 select ARM_AMBA 576 select ARM_GIC 577 select ARM_GIC_V2M if PCI 578 select ARM_GIC_V3 579 select ARM_GIC_V3_ITS if PCI 580 select ARM_PSCI 581 select HAVE_ARM_ARCH_TIMER 582 select ARCH_SUPPORTS_BIG_ENDIAN 583 584# 585# This is sorted alphabetically by mach-* pathname. However, plat-* 586# Kconfigs may be included either alphabetically (according to the 587# plat- suffix) or along side the corresponding mach-* source. 588# 589source "arch/arm/mach-actions/Kconfig" 590 591source "arch/arm/mach-alpine/Kconfig" 592 593source "arch/arm/mach-artpec/Kconfig" 594 595source "arch/arm/mach-asm9260/Kconfig" 596 597source "arch/arm/mach-aspeed/Kconfig" 598 599source "arch/arm/mach-at91/Kconfig" 600 601source "arch/arm/mach-axxia/Kconfig" 602 603source "arch/arm/mach-bcm/Kconfig" 604 605source "arch/arm/mach-berlin/Kconfig" 606 607source "arch/arm/mach-clps711x/Kconfig" 608 609source "arch/arm/mach-cns3xxx/Kconfig" 610 611source "arch/arm/mach-davinci/Kconfig" 612 613source "arch/arm/mach-digicolor/Kconfig" 614 615source "arch/arm/mach-dove/Kconfig" 616 617source "arch/arm/mach-ep93xx/Kconfig" 618 619source "arch/arm/mach-exynos/Kconfig" 620 621source "arch/arm/mach-footbridge/Kconfig" 622 623source "arch/arm/mach-gemini/Kconfig" 624 625source "arch/arm/mach-highbank/Kconfig" 626 627source "arch/arm/mach-hisi/Kconfig" 628 629source "arch/arm/mach-imx/Kconfig" 630 631source "arch/arm/mach-integrator/Kconfig" 632 633source "arch/arm/mach-iop32x/Kconfig" 634 635source "arch/arm/mach-ixp4xx/Kconfig" 636 637source "arch/arm/mach-keystone/Kconfig" 638 639source "arch/arm/mach-lpc32xx/Kconfig" 640 641source "arch/arm/mach-mediatek/Kconfig" 642 643source "arch/arm/mach-meson/Kconfig" 644 645source "arch/arm/mach-milbeaut/Kconfig" 646 647source "arch/arm/mach-mmp/Kconfig" 648 649source "arch/arm/mach-moxart/Kconfig" 650 651source "arch/arm/mach-mstar/Kconfig" 652 653source "arch/arm/mach-mv78xx0/Kconfig" 654 655source "arch/arm/mach-mvebu/Kconfig" 656 657source "arch/arm/mach-mxs/Kconfig" 658 659source "arch/arm/mach-nomadik/Kconfig" 660 661source "arch/arm/mach-npcm/Kconfig" 662 663source "arch/arm/mach-nspire/Kconfig" 664 665source "arch/arm/plat-omap/Kconfig" 666 667source "arch/arm/mach-omap1/Kconfig" 668 669source "arch/arm/mach-omap2/Kconfig" 670 671source "arch/arm/mach-orion5x/Kconfig" 672 673source "arch/arm/mach-oxnas/Kconfig" 674 675source "arch/arm/mach-pxa/Kconfig" 676source "arch/arm/plat-pxa/Kconfig" 677 678source "arch/arm/mach-qcom/Kconfig" 679 680source "arch/arm/mach-rda/Kconfig" 681 682source "arch/arm/mach-realtek/Kconfig" 683 684source "arch/arm/mach-realview/Kconfig" 685 686source "arch/arm/mach-rockchip/Kconfig" 687 688source "arch/arm/mach-s3c/Kconfig" 689 690source "arch/arm/mach-s5pv210/Kconfig" 691 692source "arch/arm/mach-sa1100/Kconfig" 693 694source "arch/arm/mach-shmobile/Kconfig" 695 696source "arch/arm/mach-socfpga/Kconfig" 697 698source "arch/arm/mach-spear/Kconfig" 699 700source "arch/arm/mach-sti/Kconfig" 701 702source "arch/arm/mach-stm32/Kconfig" 703 704source "arch/arm/mach-sunxi/Kconfig" 705 706source "arch/arm/mach-tegra/Kconfig" 707 708source "arch/arm/mach-uniphier/Kconfig" 709 710source "arch/arm/mach-ux500/Kconfig" 711 712source "arch/arm/mach-versatile/Kconfig" 713 714source "arch/arm/mach-vexpress/Kconfig" 715 716source "arch/arm/mach-vt8500/Kconfig" 717 718source "arch/arm/mach-zynq/Kconfig" 719 720# ARMv7-M architecture 721config ARCH_LPC18XX 722 bool "NXP LPC18xx/LPC43xx" 723 depends on ARM_SINGLE_ARMV7M 724 select ARCH_HAS_RESET_CONTROLLER 725 select ARM_AMBA 726 select CLKSRC_LPC32XX 727 select PINCTRL 728 help 729 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 730 high performance microcontrollers. 731 732config ARCH_MPS2 733 bool "ARM MPS2 platform" 734 depends on ARM_SINGLE_ARMV7M 735 select ARM_AMBA 736 select CLKSRC_MPS2 737 help 738 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 739 with a range of available cores like Cortex-M3/M4/M7. 740 741 Please, note that depends which Application Note is used memory map 742 for the platform may vary, so adjustment of RAM base might be needed. 743 744# Definitions to make life easier 745config ARCH_ACORN 746 bool 747 748config PLAT_IOP 749 bool 750 751config PLAT_ORION 752 bool 753 select CLKSRC_MMIO 754 select COMMON_CLK 755 select GENERIC_IRQ_CHIP 756 select IRQ_DOMAIN 757 758config PLAT_ORION_LEGACY 759 bool 760 select PLAT_ORION 761 762config PLAT_PXA 763 bool 764 765config PLAT_VERSATILE 766 bool 767 768source "arch/arm/mm/Kconfig" 769 770config IWMMXT 771 bool "Enable iWMMXt support" 772 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 773 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 774 help 775 Enable support for iWMMXt context switching at run time if 776 running on a CPU that supports it. 777 778if !MMU 779source "arch/arm/Kconfig-nommu" 780endif 781 782config PJ4B_ERRATA_4742 783 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 784 depends on CPU_PJ4B && MACH_ARMADA_370 785 default y 786 help 787 When coming out of either a Wait for Interrupt (WFI) or a Wait for 788 Event (WFE) IDLE states, a specific timing sensitivity exists between 789 the retiring WFI/WFE instructions and the newly issued subsequent 790 instructions. This sensitivity can result in a CPU hang scenario. 791 Workaround: 792 The software must insert either a Data Synchronization Barrier (DSB) 793 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 794 instruction 795 796config ARM_ERRATA_326103 797 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 798 depends on CPU_V6 799 help 800 Executing a SWP instruction to read-only memory does not set bit 11 801 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 802 treat the access as a read, preventing a COW from occurring and 803 causing the faulting task to livelock. 804 805config ARM_ERRATA_411920 806 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 807 depends on CPU_V6 || CPU_V6K 808 help 809 Invalidation of the Instruction Cache operation can 810 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 811 It does not affect the MPCore. This option enables the ARM Ltd. 812 recommended workaround. 813 814config ARM_ERRATA_430973 815 bool "ARM errata: Stale prediction on replaced interworking branch" 816 depends on CPU_V7 817 help 818 This option enables the workaround for the 430973 Cortex-A8 819 r1p* erratum. If a code sequence containing an ARM/Thumb 820 interworking branch is replaced with another code sequence at the 821 same virtual address, whether due to self-modifying code or virtual 822 to physical address re-mapping, Cortex-A8 does not recover from the 823 stale interworking branch prediction. This results in Cortex-A8 824 executing the new code sequence in the incorrect ARM or Thumb state. 825 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 826 and also flushes the branch target cache at every context switch. 827 Note that setting specific bits in the ACTLR register may not be 828 available in non-secure mode. 829 830config ARM_ERRATA_458693 831 bool "ARM errata: Processor deadlock when a false hazard is created" 832 depends on CPU_V7 833 depends on !ARCH_MULTIPLATFORM 834 help 835 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 836 erratum. For very specific sequences of memory operations, it is 837 possible for a hazard condition intended for a cache line to instead 838 be incorrectly associated with a different cache line. This false 839 hazard might then cause a processor deadlock. The workaround enables 840 the L1 caching of the NEON accesses and disables the PLD instruction 841 in the ACTLR register. Note that setting specific bits in the ACTLR 842 register may not be available in non-secure mode. 843 844config ARM_ERRATA_460075 845 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 846 depends on CPU_V7 847 depends on !ARCH_MULTIPLATFORM 848 help 849 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 850 erratum. Any asynchronous access to the L2 cache may encounter a 851 situation in which recent store transactions to the L2 cache are lost 852 and overwritten with stale memory contents from external memory. The 853 workaround disables the write-allocate mode for the L2 cache via the 854 ACTLR register. Note that setting specific bits in the ACTLR register 855 may not be available in non-secure mode. 856 857config ARM_ERRATA_742230 858 bool "ARM errata: DMB operation may be faulty" 859 depends on CPU_V7 && SMP 860 depends on !ARCH_MULTIPLATFORM 861 help 862 This option enables the workaround for the 742230 Cortex-A9 863 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 864 between two write operations may not ensure the correct visibility 865 ordering of the two writes. This workaround sets a specific bit in 866 the diagnostic register of the Cortex-A9 which causes the DMB 867 instruction to behave as a DSB, ensuring the correct behaviour of 868 the two writes. 869 870config ARM_ERRATA_742231 871 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 872 depends on CPU_V7 && SMP 873 depends on !ARCH_MULTIPLATFORM 874 help 875 This option enables the workaround for the 742231 Cortex-A9 876 (r2p0..r2p2) erratum. Under certain conditions, specific to the 877 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 878 accessing some data located in the same cache line, may get corrupted 879 data due to bad handling of the address hazard when the line gets 880 replaced from one of the CPUs at the same time as another CPU is 881 accessing it. This workaround sets specific bits in the diagnostic 882 register of the Cortex-A9 which reduces the linefill issuing 883 capabilities of the processor. 884 885config ARM_ERRATA_643719 886 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 887 depends on CPU_V7 && SMP 888 default y 889 help 890 This option enables the workaround for the 643719 Cortex-A9 (prior to 891 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 892 register returns zero when it should return one. The workaround 893 corrects this value, ensuring cache maintenance operations which use 894 it behave as intended and avoiding data corruption. 895 896config ARM_ERRATA_720789 897 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 898 depends on CPU_V7 899 help 900 This option enables the workaround for the 720789 Cortex-A9 (prior to 901 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 902 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 903 As a consequence of this erratum, some TLB entries which should be 904 invalidated are not, resulting in an incoherency in the system page 905 tables. The workaround changes the TLB flushing routines to invalidate 906 entries regardless of the ASID. 907 908config ARM_ERRATA_743622 909 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 910 depends on CPU_V7 911 depends on !ARCH_MULTIPLATFORM 912 help 913 This option enables the workaround for the 743622 Cortex-A9 914 (r2p*) erratum. Under very rare conditions, a faulty 915 optimisation in the Cortex-A9 Store Buffer may lead to data 916 corruption. This workaround sets a specific bit in the diagnostic 917 register of the Cortex-A9 which disables the Store Buffer 918 optimisation, preventing the defect from occurring. This has no 919 visible impact on the overall performance or power consumption of the 920 processor. 921 922config ARM_ERRATA_751472 923 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 924 depends on CPU_V7 925 depends on !ARCH_MULTIPLATFORM 926 help 927 This option enables the workaround for the 751472 Cortex-A9 (prior 928 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 929 completion of a following broadcasted operation if the second 930 operation is received by a CPU before the ICIALLUIS has completed, 931 potentially leading to corrupted entries in the cache or TLB. 932 933config ARM_ERRATA_754322 934 bool "ARM errata: possible faulty MMU translations following an ASID switch" 935 depends on CPU_V7 936 help 937 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 938 r3p*) erratum. A speculative memory access may cause a page table walk 939 which starts prior to an ASID switch but completes afterwards. This 940 can populate the micro-TLB with a stale entry which may be hit with 941 the new ASID. This workaround places two dsb instructions in the mm 942 switching code so that no page table walks can cross the ASID switch. 943 944config ARM_ERRATA_754327 945 bool "ARM errata: no automatic Store Buffer drain" 946 depends on CPU_V7 && SMP 947 help 948 This option enables the workaround for the 754327 Cortex-A9 (prior to 949 r2p0) erratum. The Store Buffer does not have any automatic draining 950 mechanism and therefore a livelock may occur if an external agent 951 continuously polls a memory location waiting to observe an update. 952 This workaround defines cpu_relax() as smp_mb(), preventing correctly 953 written polling loops from denying visibility of updates to memory. 954 955config ARM_ERRATA_364296 956 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 957 depends on CPU_V6 958 help 959 This options enables the workaround for the 364296 ARM1136 960 r0p2 erratum (possible cache data corruption with 961 hit-under-miss enabled). It sets the undocumented bit 31 in 962 the auxiliary control register and the FI bit in the control 963 register, thus disabling hit-under-miss without putting the 964 processor into full low interrupt latency mode. ARM11MPCore 965 is not affected. 966 967config ARM_ERRATA_764369 968 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 969 depends on CPU_V7 && SMP 970 help 971 This option enables the workaround for erratum 764369 972 affecting Cortex-A9 MPCore with two or more processors (all 973 current revisions). Under certain timing circumstances, a data 974 cache line maintenance operation by MVA targeting an Inner 975 Shareable memory region may fail to proceed up to either the 976 Point of Coherency or to the Point of Unification of the 977 system. This workaround adds a DSB instruction before the 978 relevant cache maintenance functions and sets a specific bit 979 in the diagnostic control register of the SCU. 980 981config ARM_ERRATA_775420 982 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 983 depends on CPU_V7 984 help 985 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 986 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 987 operation aborts with MMU exception, it might cause the processor 988 to deadlock. This workaround puts DSB before executing ISB if 989 an abort may occur on cache maintenance. 990 991config ARM_ERRATA_798181 992 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 993 depends on CPU_V7 && SMP 994 help 995 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 996 adequately shooting down all use of the old entries. This 997 option enables the Linux kernel workaround for this erratum 998 which sends an IPI to the CPUs that are running the same ASID 999 as the one being invalidated. 1000 1001config ARM_ERRATA_773022 1002 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1003 depends on CPU_V7 1004 help 1005 This option enables the workaround for the 773022 Cortex-A15 1006 (up to r0p4) erratum. In certain rare sequences of code, the 1007 loop buffer may deliver incorrect instructions. This 1008 workaround disables the loop buffer to avoid the erratum. 1009 1010config ARM_ERRATA_818325_852422 1011 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1012 depends on CPU_V7 1013 help 1014 This option enables the workaround for: 1015 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1016 instruction might deadlock. Fixed in r0p1. 1017 - Cortex-A12 852422: Execution of a sequence of instructions might 1018 lead to either a data corruption or a CPU deadlock. Not fixed in 1019 any Cortex-A12 cores yet. 1020 This workaround for all both errata involves setting bit[12] of the 1021 Feature Register. This bit disables an optimisation applied to a 1022 sequence of 2 instructions that use opposing condition codes. 1023 1024config ARM_ERRATA_821420 1025 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1026 depends on CPU_V7 1027 help 1028 This option enables the workaround for the 821420 Cortex-A12 1029 (all revs) erratum. In very rare timing conditions, a sequence 1030 of VMOV to Core registers instructions, for which the second 1031 one is in the shadow of a branch or abort, can lead to a 1032 deadlock when the VMOV instructions are issued out-of-order. 1033 1034config ARM_ERRATA_825619 1035 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1036 depends on CPU_V7 1037 help 1038 This option enables the workaround for the 825619 Cortex-A12 1039 (all revs) erratum. Within rare timing constraints, executing a 1040 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1041 and Device/Strongly-Ordered loads and stores might cause deadlock 1042 1043config ARM_ERRATA_857271 1044 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1045 depends on CPU_V7 1046 help 1047 This option enables the workaround for the 857271 Cortex-A12 1048 (all revs) erratum. Under very rare timing conditions, the CPU might 1049 hang. The workaround is expected to have a < 1% performance impact. 1050 1051config ARM_ERRATA_852421 1052 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1053 depends on CPU_V7 1054 help 1055 This option enables the workaround for the 852421 Cortex-A17 1056 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1057 execution of a DMB ST instruction might fail to properly order 1058 stores from GroupA and stores from GroupB. 1059 1060config ARM_ERRATA_852423 1061 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1062 depends on CPU_V7 1063 help 1064 This option enables the workaround for: 1065 - Cortex-A17 852423: Execution of a sequence of instructions might 1066 lead to either a data corruption or a CPU deadlock. Not fixed in 1067 any Cortex-A17 cores yet. 1068 This is identical to Cortex-A12 erratum 852422. It is a separate 1069 config option from the A12 erratum due to the way errata are checked 1070 for and handled. 1071 1072config ARM_ERRATA_857272 1073 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1074 depends on CPU_V7 1075 help 1076 This option enables the workaround for the 857272 Cortex-A17 erratum. 1077 This erratum is not known to be fixed in any A17 revision. 1078 This is identical to Cortex-A12 erratum 857271. It is a separate 1079 config option from the A12 erratum due to the way errata are checked 1080 for and handled. 1081 1082endmenu 1083 1084source "arch/arm/common/Kconfig" 1085 1086menu "Bus support" 1087 1088config ISA 1089 bool 1090 help 1091 Find out whether you have ISA slots on your motherboard. ISA is the 1092 name of a bus system, i.e. the way the CPU talks to the other stuff 1093 inside your box. Other bus systems are PCI, EISA, MicroChannel 1094 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1095 newer boards don't support it. If you have ISA, say Y, otherwise N. 1096 1097# Select ISA DMA controller support 1098config ISA_DMA 1099 bool 1100 select ISA_DMA_API 1101 1102# Select ISA DMA interface 1103config ISA_DMA_API 1104 bool 1105 1106config PCI_NANOENGINE 1107 bool "BSE nanoEngine PCI support" 1108 depends on SA1100_NANOENGINE 1109 help 1110 Enable PCI on the BSE nanoEngine board. 1111 1112config ARM_ERRATA_814220 1113 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1114 depends on CPU_V7 1115 help 1116 The v7 ARM states that all cache and branch predictor maintenance 1117 operations that do not specify an address execute, relative to 1118 each other, in program order. 1119 However, because of this erratum, an L2 set/way cache maintenance 1120 operation can overtake an L1 set/way cache maintenance operation. 1121 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1122 r0p4, r0p5. 1123 1124endmenu 1125 1126menu "Kernel Features" 1127 1128config HAVE_SMP 1129 bool 1130 help 1131 This option should be selected by machines which have an SMP- 1132 capable CPU. 1133 1134 The only effect of this option is to make the SMP-related 1135 options available to the user for configuration. 1136 1137config SMP 1138 bool "Symmetric Multi-Processing" 1139 depends on CPU_V6K || CPU_V7 1140 depends on HAVE_SMP 1141 depends on MMU || ARM_MPU 1142 select IRQ_WORK 1143 help 1144 This enables support for systems with more than one CPU. If you have 1145 a system with only one CPU, say N. If you have a system with more 1146 than one CPU, say Y. 1147 1148 If you say N here, the kernel will run on uni- and multiprocessor 1149 machines, but will use only one CPU of a multiprocessor machine. If 1150 you say Y here, the kernel will run on many, but not all, 1151 uniprocessor machines. On a uniprocessor machine, the kernel 1152 will run faster if you say N here. 1153 1154 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1155 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1156 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1157 1158 If you don't know what to do here, say N. 1159 1160config SMP_ON_UP 1161 bool "Allow booting SMP kernel on uniprocessor systems" 1162 depends on SMP && !XIP_KERNEL && MMU 1163 default y 1164 help 1165 SMP kernels contain instructions which fail on non-SMP processors. 1166 Enabling this option allows the kernel to modify itself to make 1167 these instructions safe. Disabling it allows about 1K of space 1168 savings. 1169 1170 If you don't know what to do here, say Y. 1171 1172config ARM_CPU_TOPOLOGY 1173 bool "Support cpu topology definition" 1174 depends on SMP && CPU_V7 1175 default y 1176 help 1177 Support ARM cpu topology definition. The MPIDR register defines 1178 affinity between processors which is then used to describe the cpu 1179 topology of an ARM System. 1180 1181config SCHED_MC 1182 bool "Multi-core scheduler support" 1183 depends on ARM_CPU_TOPOLOGY 1184 help 1185 Multi-core scheduler support improves the CPU scheduler's decision 1186 making when dealing with multi-core CPU chips at a cost of slightly 1187 increased overhead in some places. If unsure say N here. 1188 1189config SCHED_SMT 1190 bool "SMT scheduler support" 1191 depends on ARM_CPU_TOPOLOGY 1192 help 1193 Improves the CPU scheduler's decision making when dealing with 1194 MultiThreading at a cost of slightly increased overhead in some 1195 places. If unsure say N here. 1196 1197config HAVE_ARM_SCU 1198 bool 1199 help 1200 This option enables support for the ARM snoop control unit 1201 1202config HAVE_ARM_ARCH_TIMER 1203 bool "Architected timer support" 1204 depends on CPU_V7 1205 select ARM_ARCH_TIMER 1206 help 1207 This option enables support for the ARM architected timer 1208 1209config HAVE_ARM_TWD 1210 bool 1211 help 1212 This options enables support for the ARM timer and watchdog unit 1213 1214config MCPM 1215 bool "Multi-Cluster Power Management" 1216 depends on CPU_V7 && SMP 1217 help 1218 This option provides the common power management infrastructure 1219 for (multi-)cluster based systems, such as big.LITTLE based 1220 systems. 1221 1222config MCPM_QUAD_CLUSTER 1223 bool 1224 depends on MCPM 1225 help 1226 To avoid wasting resources unnecessarily, MCPM only supports up 1227 to 2 clusters by default. 1228 Platforms with 3 or 4 clusters that use MCPM must select this 1229 option to allow the additional clusters to be managed. 1230 1231config BIG_LITTLE 1232 bool "big.LITTLE support (Experimental)" 1233 depends on CPU_V7 && SMP 1234 select MCPM 1235 help 1236 This option enables support selections for the big.LITTLE 1237 system architecture. 1238 1239config BL_SWITCHER 1240 bool "big.LITTLE switcher support" 1241 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1242 select CPU_PM 1243 help 1244 The big.LITTLE "switcher" provides the core functionality to 1245 transparently handle transition between a cluster of A15's 1246 and a cluster of A7's in a big.LITTLE system. 1247 1248config BL_SWITCHER_DUMMY_IF 1249 tristate "Simple big.LITTLE switcher user interface" 1250 depends on BL_SWITCHER && DEBUG_KERNEL 1251 help 1252 This is a simple and dummy char dev interface to control 1253 the big.LITTLE switcher core code. It is meant for 1254 debugging purposes only. 1255 1256choice 1257 prompt "Memory split" 1258 depends on MMU 1259 default VMSPLIT_3G 1260 help 1261 Select the desired split between kernel and user memory. 1262 1263 If you are not absolutely sure what you are doing, leave this 1264 option alone! 1265 1266 config VMSPLIT_3G 1267 bool "3G/1G user/kernel split" 1268 config VMSPLIT_3G_OPT 1269 depends on !ARM_LPAE 1270 bool "3G/1G user/kernel split (for full 1G low memory)" 1271 config VMSPLIT_2G 1272 bool "2G/2G user/kernel split" 1273 config VMSPLIT_1G 1274 bool "1G/3G user/kernel split" 1275endchoice 1276 1277config PAGE_OFFSET 1278 hex 1279 default PHYS_OFFSET if !MMU 1280 default 0x40000000 if VMSPLIT_1G 1281 default 0x80000000 if VMSPLIT_2G 1282 default 0xB0000000 if VMSPLIT_3G_OPT 1283 default 0xC0000000 1284 1285config KASAN_SHADOW_OFFSET 1286 hex 1287 depends on KASAN 1288 default 0x1f000000 if PAGE_OFFSET=0x40000000 1289 default 0x5f000000 if PAGE_OFFSET=0x80000000 1290 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1291 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1292 default 0xffffffff 1293 1294config NR_CPUS 1295 int "Maximum number of CPUs (2-32)" 1296 range 2 32 1297 depends on SMP 1298 default "4" 1299 1300config HOTPLUG_CPU 1301 bool "Support for hot-pluggable CPUs" 1302 depends on SMP 1303 select GENERIC_IRQ_MIGRATION 1304 help 1305 Say Y here to experiment with turning CPUs off and on. CPUs 1306 can be controlled through /sys/devices/system/cpu. 1307 1308config ARM_PSCI 1309 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1310 depends on HAVE_ARM_SMCCC 1311 select ARM_PSCI_FW 1312 help 1313 Say Y here if you want Linux to communicate with system firmware 1314 implementing the PSCI specification for CPU-centric power 1315 management operations described in ARM document number ARM DEN 1316 0022A ("Power State Coordination Interface System Software on 1317 ARM processors"). 1318 1319# The GPIO number here must be sorted by descending number. In case of 1320# a multiplatform kernel, we just want the highest value required by the 1321# selected platforms. 1322config ARCH_NR_GPIO 1323 int 1324 default 2048 if ARCH_SOCFPGA 1325 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1326 ARCH_ZYNQ || ARCH_ASPEED 1327 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1328 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1329 default 416 if ARCH_SUNXI 1330 default 392 if ARCH_U8500 1331 default 352 if ARCH_VT8500 1332 default 288 if ARCH_ROCKCHIP 1333 default 264 if MACH_H4700 1334 default 0 1335 help 1336 Maximum number of GPIOs in the system. 1337 1338 If unsure, leave the default value. 1339 1340config HZ_FIXED 1341 int 1342 default 128 if SOC_AT91RM9200 1343 default 0 1344 1345choice 1346 depends on HZ_FIXED = 0 1347 prompt "Timer frequency" 1348 1349config HZ_100 1350 bool "100 Hz" 1351 1352config HZ_200 1353 bool "200 Hz" 1354 1355config HZ_250 1356 bool "250 Hz" 1357 1358config HZ_300 1359 bool "300 Hz" 1360 1361config HZ_500 1362 bool "500 Hz" 1363 1364config HZ_1000 1365 bool "1000 Hz" 1366 1367endchoice 1368 1369config HZ 1370 int 1371 default HZ_FIXED if HZ_FIXED != 0 1372 default 100 if HZ_100 1373 default 200 if HZ_200 1374 default 250 if HZ_250 1375 default 300 if HZ_300 1376 default 500 if HZ_500 1377 default 1000 1378 1379config SCHED_HRTICK 1380 def_bool HIGH_RES_TIMERS 1381 1382config THUMB2_KERNEL 1383 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1384 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1385 default y if CPU_THUMBONLY 1386 select ARM_UNWIND 1387 help 1388 By enabling this option, the kernel will be compiled in 1389 Thumb-2 mode. 1390 1391 If unsure, say N. 1392 1393config ARM_PATCH_IDIV 1394 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1395 depends on CPU_32v7 && !XIP_KERNEL 1396 default y 1397 help 1398 The ARM compiler inserts calls to __aeabi_idiv() and 1399 __aeabi_uidiv() when it needs to perform division on signed 1400 and unsigned integers. Some v7 CPUs have support for the sdiv 1401 and udiv instructions that can be used to implement those 1402 functions. 1403 1404 Enabling this option allows the kernel to modify itself to 1405 replace the first two instructions of these library functions 1406 with the sdiv or udiv plus "bx lr" instructions when the CPU 1407 it is running on supports them. Typically this will be faster 1408 and less power intensive than running the original library 1409 code to do integer division. 1410 1411config AEABI 1412 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1413 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1414 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1415 help 1416 This option allows for the kernel to be compiled using the latest 1417 ARM ABI (aka EABI). This is only useful if you are using a user 1418 space environment that is also compiled with EABI. 1419 1420 Since there are major incompatibilities between the legacy ABI and 1421 EABI, especially with regard to structure member alignment, this 1422 option also changes the kernel syscall calling convention to 1423 disambiguate both ABIs and allow for backward compatibility support 1424 (selected with CONFIG_OABI_COMPAT). 1425 1426 To use this you need GCC version 4.0.0 or later. 1427 1428config OABI_COMPAT 1429 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1430 depends on AEABI && !THUMB2_KERNEL 1431 help 1432 This option preserves the old syscall interface along with the 1433 new (ARM EABI) one. It also provides a compatibility layer to 1434 intercept syscalls that have structure arguments which layout 1435 in memory differs between the legacy ABI and the new ARM EABI 1436 (only for non "thumb" binaries). This option adds a tiny 1437 overhead to all syscalls and produces a slightly larger kernel. 1438 1439 The seccomp filter system will not be available when this is 1440 selected, since there is no way yet to sensibly distinguish 1441 between calling conventions during filtering. 1442 1443 If you know you'll be using only pure EABI user space then you 1444 can say N here. If this option is not selected and you attempt 1445 to execute a legacy ABI binary then the result will be 1446 UNPREDICTABLE (in fact it can be predicted that it won't work 1447 at all). If in doubt say N. 1448 1449config ARCH_SELECT_MEMORY_MODEL 1450 bool 1451 1452config ARCH_FLATMEM_ENABLE 1453 bool 1454 1455config ARCH_SPARSEMEM_ENABLE 1456 bool 1457 select SPARSEMEM_STATIC if SPARSEMEM 1458 1459config HIGHMEM 1460 bool "High Memory Support" 1461 depends on MMU 1462 select KMAP_LOCAL 1463 help 1464 The address space of ARM processors is only 4 Gigabytes large 1465 and it has to accommodate user address space, kernel address 1466 space as well as some memory mapped IO. That means that, if you 1467 have a large amount of physical memory and/or IO, not all of the 1468 memory can be "permanently mapped" by the kernel. The physical 1469 memory that is not permanently mapped is called "high memory". 1470 1471 Depending on the selected kernel/user memory split, minimum 1472 vmalloc space and actual amount of RAM, you may not need this 1473 option which should result in a slightly faster kernel. 1474 1475 If unsure, say n. 1476 1477config HIGHPTE 1478 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1479 depends on HIGHMEM 1480 default y 1481 help 1482 The VM uses one page of physical memory for each page table. 1483 For systems with a lot of processes, this can use a lot of 1484 precious low memory, eventually leading to low memory being 1485 consumed by page tables. Setting this option will allow 1486 user-space 2nd level page tables to reside in high memory. 1487 1488config CPU_SW_DOMAIN_PAN 1489 bool "Enable use of CPU domains to implement privileged no-access" 1490 depends on MMU && !ARM_LPAE 1491 default y 1492 help 1493 Increase kernel security by ensuring that normal kernel accesses 1494 are unable to access userspace addresses. This can help prevent 1495 use-after-free bugs becoming an exploitable privilege escalation 1496 by ensuring that magic values (such as LIST_POISON) will always 1497 fault when dereferenced. 1498 1499 CPUs with low-vector mappings use a best-efforts implementation. 1500 Their lower 1MB needs to remain accessible for the vectors, but 1501 the remainder of userspace will become appropriately inaccessible. 1502 1503config HW_PERF_EVENTS 1504 def_bool y 1505 depends on ARM_PMU 1506 1507config SYS_SUPPORTS_HUGETLBFS 1508 def_bool y 1509 depends on ARM_LPAE 1510 1511config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1512 def_bool y 1513 depends on ARM_LPAE 1514 1515config ARCH_WANT_GENERAL_HUGETLB 1516 def_bool y 1517 1518config ARM_MODULE_PLTS 1519 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1520 depends on MODULES 1521 default y 1522 help 1523 Allocate PLTs when loading modules so that jumps and calls whose 1524 targets are too far away for their relative offsets to be encoded 1525 in the instructions themselves can be bounced via veneers in the 1526 module's PLT. This allows modules to be allocated in the generic 1527 vmalloc area after the dedicated module memory area has been 1528 exhausted. The modules will use slightly more memory, but after 1529 rounding up to page size, the actual memory footprint is usually 1530 the same. 1531 1532 Disabling this is usually safe for small single-platform 1533 configurations. If unsure, say y. 1534 1535config FORCE_MAX_ZONEORDER 1536 int "Maximum zone order" 1537 default "12" if SOC_AM33XX 1538 default "9" if SA1111 1539 default "11" 1540 help 1541 The kernel memory allocator divides physically contiguous memory 1542 blocks into "zones", where each zone is a power of two number of 1543 pages. This option selects the largest power of two that the kernel 1544 keeps in the memory allocator. If you need to allocate very large 1545 blocks of physically contiguous memory, then you may need to 1546 increase this value. 1547 1548 This config option is actually maximum order plus one. For example, 1549 a value of 11 means that the largest free memory block is 2^10 pages. 1550 1551config ALIGNMENT_TRAP 1552 def_bool CPU_CP15_MMU 1553 select HAVE_PROC_CPU if PROC_FS 1554 help 1555 ARM processors cannot fetch/store information which is not 1556 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1557 address divisible by 4. On 32-bit ARM processors, these non-aligned 1558 fetch/store instructions will be emulated in software if you say 1559 here, which has a severe performance impact. This is necessary for 1560 correct operation of some network protocols. With an IP-only 1561 configuration it is safe to say N, otherwise say Y. 1562 1563config UACCESS_WITH_MEMCPY 1564 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1565 depends on MMU 1566 default y if CPU_FEROCEON 1567 help 1568 Implement faster copy_to_user and clear_user methods for CPU 1569 cores where a 8-word STM instruction give significantly higher 1570 memory write throughput than a sequence of individual 32bit stores. 1571 1572 A possible side effect is a slight increase in scheduling latency 1573 between threads sharing the same address space if they invoke 1574 such copy operations with large buffers. 1575 1576 However, if the CPU data cache is using a write-allocate mode, 1577 this option is unlikely to provide any performance gain. 1578 1579config PARAVIRT 1580 bool "Enable paravirtualization code" 1581 help 1582 This changes the kernel so it can modify itself when it is run 1583 under a hypervisor, potentially improving performance significantly 1584 over full virtualization. 1585 1586config PARAVIRT_TIME_ACCOUNTING 1587 bool "Paravirtual steal time accounting" 1588 select PARAVIRT 1589 help 1590 Select this option to enable fine granularity task steal time 1591 accounting. Time spent executing other tasks in parallel with 1592 the current vCPU is discounted from the vCPU power. To account for 1593 that, there can be a small performance impact. 1594 1595 If in doubt, say N here. 1596 1597config XEN_DOM0 1598 def_bool y 1599 depends on XEN 1600 1601config XEN 1602 bool "Xen guest support on ARM" 1603 depends on ARM && AEABI && OF 1604 depends on CPU_V7 && !CPU_V6 1605 depends on !GENERIC_ATOMIC64 1606 depends on MMU 1607 select ARCH_DMA_ADDR_T_64BIT 1608 select ARM_PSCI 1609 select SWIOTLB 1610 select SWIOTLB_XEN 1611 select PARAVIRT 1612 help 1613 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1614 1615config STACKPROTECTOR_PER_TASK 1616 bool "Use a unique stack canary value for each task" 1617 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1618 select GCC_PLUGIN_ARM_SSP_PER_TASK 1619 default y 1620 help 1621 Due to the fact that GCC uses an ordinary symbol reference from 1622 which to load the value of the stack canary, this value can only 1623 change at reboot time on SMP systems, and all tasks running in the 1624 kernel's address space are forced to use the same canary value for 1625 the entire duration that the system is up. 1626 1627 Enable this option to switch to a different method that uses a 1628 different canary value for each task. 1629 1630endmenu 1631 1632menu "Boot options" 1633 1634config USE_OF 1635 bool "Flattened Device Tree support" 1636 select IRQ_DOMAIN 1637 select OF 1638 help 1639 Include support for flattened device tree machine descriptions. 1640 1641config ATAGS 1642 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1643 default y 1644 help 1645 This is the traditional way of passing data to the kernel at boot 1646 time. If you are solely relying on the flattened device tree (or 1647 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1648 to remove ATAGS support from your kernel binary. If unsure, 1649 leave this to y. 1650 1651config DEPRECATED_PARAM_STRUCT 1652 bool "Provide old way to pass kernel parameters" 1653 depends on ATAGS 1654 help 1655 This was deprecated in 2001 and announced to live on for 5 years. 1656 Some old boot loaders still use this way. 1657 1658# Compressed boot loader in ROM. Yes, we really want to ask about 1659# TEXT and BSS so we preserve their values in the config files. 1660config ZBOOT_ROM_TEXT 1661 hex "Compressed ROM boot loader base address" 1662 default 0x0 1663 help 1664 The physical address at which the ROM-able zImage is to be 1665 placed in the target. Platforms which normally make use of 1666 ROM-able zImage formats normally set this to a suitable 1667 value in their defconfig file. 1668 1669 If ZBOOT_ROM is not enabled, this has no effect. 1670 1671config ZBOOT_ROM_BSS 1672 hex "Compressed ROM boot loader BSS address" 1673 default 0x0 1674 help 1675 The base address of an area of read/write memory in the target 1676 for the ROM-able zImage which must be available while the 1677 decompressor is running. It must be large enough to hold the 1678 entire decompressed kernel plus an additional 128 KiB. 1679 Platforms which normally make use of ROM-able zImage formats 1680 normally set this to a suitable value in their defconfig file. 1681 1682 If ZBOOT_ROM is not enabled, this has no effect. 1683 1684config ZBOOT_ROM 1685 bool "Compressed boot loader in ROM/flash" 1686 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1687 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1688 help 1689 Say Y here if you intend to execute your compressed kernel image 1690 (zImage) directly from ROM or flash. If unsure, say N. 1691 1692config ARM_APPENDED_DTB 1693 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1694 depends on OF 1695 help 1696 With this option, the boot code will look for a device tree binary 1697 (DTB) appended to zImage 1698 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1699 1700 This is meant as a backward compatibility convenience for those 1701 systems with a bootloader that can't be upgraded to accommodate 1702 the documented boot protocol using a device tree. 1703 1704 Beware that there is very little in terms of protection against 1705 this option being confused by leftover garbage in memory that might 1706 look like a DTB header after a reboot if no actual DTB is appended 1707 to zImage. Do not leave this option active in a production kernel 1708 if you don't intend to always append a DTB. Proper passing of the 1709 location into r2 of a bootloader provided DTB is always preferable 1710 to this option. 1711 1712config ARM_ATAG_DTB_COMPAT 1713 bool "Supplement the appended DTB with traditional ATAG information" 1714 depends on ARM_APPENDED_DTB 1715 help 1716 Some old bootloaders can't be updated to a DTB capable one, yet 1717 they provide ATAGs with memory configuration, the ramdisk address, 1718 the kernel cmdline string, etc. Such information is dynamically 1719 provided by the bootloader and can't always be stored in a static 1720 DTB. To allow a device tree enabled kernel to be used with such 1721 bootloaders, this option allows zImage to extract the information 1722 from the ATAG list and store it at run time into the appended DTB. 1723 1724choice 1725 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1726 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1727 1728config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1729 bool "Use bootloader kernel arguments if available" 1730 help 1731 Uses the command-line options passed by the boot loader instead of 1732 the device tree bootargs property. If the boot loader doesn't provide 1733 any, the device tree bootargs property will be used. 1734 1735config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1736 bool "Extend with bootloader kernel arguments" 1737 help 1738 The command-line arguments provided by the boot loader will be 1739 appended to the the device tree bootargs property. 1740 1741endchoice 1742 1743config CMDLINE 1744 string "Default kernel command string" 1745 default "" 1746 help 1747 On some architectures (e.g. CATS), there is currently no way 1748 for the boot loader to pass arguments to the kernel. For these 1749 architectures, you should supply some command-line options at build 1750 time by entering them here. As a minimum, you should specify the 1751 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1752 1753choice 1754 prompt "Kernel command line type" if CMDLINE != "" 1755 default CMDLINE_FROM_BOOTLOADER 1756 depends on ATAGS 1757 1758config CMDLINE_FROM_BOOTLOADER 1759 bool "Use bootloader kernel arguments if available" 1760 help 1761 Uses the command-line options passed by the boot loader. If 1762 the boot loader doesn't provide any, the default kernel command 1763 string provided in CMDLINE will be used. 1764 1765config CMDLINE_EXTEND 1766 bool "Extend bootloader kernel arguments" 1767 help 1768 The command-line arguments provided by the boot loader will be 1769 appended to the default kernel command string. 1770 1771config CMDLINE_FORCE 1772 bool "Always use the default kernel command string" 1773 help 1774 Always use the default kernel command string, even if the boot 1775 loader passes other arguments to the kernel. 1776 This is useful if you cannot or don't want to change the 1777 command-line options your boot loader passes to the kernel. 1778endchoice 1779 1780config XIP_KERNEL 1781 bool "Kernel Execute-In-Place from ROM" 1782 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1783 help 1784 Execute-In-Place allows the kernel to run from non-volatile storage 1785 directly addressable by the CPU, such as NOR flash. This saves RAM 1786 space since the text section of the kernel is not loaded from flash 1787 to RAM. Read-write sections, such as the data section and stack, 1788 are still copied to RAM. The XIP kernel is not compressed since 1789 it has to run directly from flash, so it will take more space to 1790 store it. The flash address used to link the kernel object files, 1791 and for storing it, is configuration dependent. Therefore, if you 1792 say Y here, you must know the proper physical address where to 1793 store the kernel image depending on your own flash memory usage. 1794 1795 Also note that the make target becomes "make xipImage" rather than 1796 "make zImage" or "make Image". The final kernel binary to put in 1797 ROM memory will be arch/arm/boot/xipImage. 1798 1799 If unsure, say N. 1800 1801config XIP_PHYS_ADDR 1802 hex "XIP Kernel Physical Location" 1803 depends on XIP_KERNEL 1804 default "0x00080000" 1805 help 1806 This is the physical address in your flash memory the kernel will 1807 be linked for and stored to. This address is dependent on your 1808 own flash usage. 1809 1810config XIP_DEFLATED_DATA 1811 bool "Store kernel .data section compressed in ROM" 1812 depends on XIP_KERNEL 1813 select ZLIB_INFLATE 1814 help 1815 Before the kernel is actually executed, its .data section has to be 1816 copied to RAM from ROM. This option allows for storing that data 1817 in compressed form and decompressed to RAM rather than merely being 1818 copied, saving some precious ROM space. A possible drawback is a 1819 slightly longer boot delay. 1820 1821config KEXEC 1822 bool "Kexec system call (EXPERIMENTAL)" 1823 depends on (!SMP || PM_SLEEP_SMP) 1824 depends on MMU 1825 select KEXEC_CORE 1826 help 1827 kexec is a system call that implements the ability to shutdown your 1828 current kernel, and to start another kernel. It is like a reboot 1829 but it is independent of the system firmware. And like a reboot 1830 you can start any kernel with it, not just Linux. 1831 1832 It is an ongoing process to be certain the hardware in a machine 1833 is properly shutdown, so do not be surprised if this code does not 1834 initially work for you. 1835 1836config ATAGS_PROC 1837 bool "Export atags in procfs" 1838 depends on ATAGS && KEXEC 1839 default y 1840 help 1841 Should the atags used to boot the kernel be exported in an "atags" 1842 file in procfs. Useful with kexec. 1843 1844config CRASH_DUMP 1845 bool "Build kdump crash kernel (EXPERIMENTAL)" 1846 help 1847 Generate crash dump after being started by kexec. This should 1848 be normally only set in special crash dump kernels which are 1849 loaded in the main kernel with kexec-tools into a specially 1850 reserved region and then later executed after a crash by 1851 kdump/kexec. The crash dump kernel must be compiled to a 1852 memory address not used by the main kernel 1853 1854 For more details see Documentation/admin-guide/kdump/kdump.rst 1855 1856config AUTO_ZRELADDR 1857 bool "Auto calculation of the decompressed kernel image address" 1858 help 1859 ZRELADDR is the physical address where the decompressed kernel 1860 image will be placed. If AUTO_ZRELADDR is selected, the address 1861 will be determined at run-time, either by masking the current IP 1862 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1863 This assumes the zImage being placed in the first 128MB from 1864 start of memory. 1865 1866config EFI_STUB 1867 bool 1868 1869config EFI 1870 bool "UEFI runtime support" 1871 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1872 select UCS2_STRING 1873 select EFI_PARAMS_FROM_FDT 1874 select EFI_STUB 1875 select EFI_GENERIC_STUB 1876 select EFI_RUNTIME_WRAPPERS 1877 help 1878 This option provides support for runtime services provided 1879 by UEFI firmware (such as non-volatile variables, realtime 1880 clock, and platform reset). A UEFI stub is also provided to 1881 allow the kernel to be booted as an EFI application. This 1882 is only useful for kernels that may run on systems that have 1883 UEFI firmware. 1884 1885config DMI 1886 bool "Enable support for SMBIOS (DMI) tables" 1887 depends on EFI 1888 default y 1889 help 1890 This enables SMBIOS/DMI feature for systems. 1891 1892 This option is only useful on systems that have UEFI firmware. 1893 However, even with this option, the resultant kernel should 1894 continue to boot on existing non-UEFI platforms. 1895 1896 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1897 i.e., the the practice of identifying the platform via DMI to 1898 decide whether certain workarounds for buggy hardware and/or 1899 firmware need to be enabled. This would require the DMI subsystem 1900 to be enabled much earlier than we do on ARM, which is non-trivial. 1901 1902endmenu 1903 1904menu "CPU Power Management" 1905 1906source "drivers/cpufreq/Kconfig" 1907 1908source "drivers/cpuidle/Kconfig" 1909 1910endmenu 1911 1912menu "Floating point emulation" 1913 1914comment "At least one emulation must be selected" 1915 1916config FPE_NWFPE 1917 bool "NWFPE math emulation" 1918 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1919 help 1920 Say Y to include the NWFPE floating point emulator in the kernel. 1921 This is necessary to run most binaries. Linux does not currently 1922 support floating point hardware so you need to say Y here even if 1923 your machine has an FPA or floating point co-processor podule. 1924 1925 You may say N here if you are going to load the Acorn FPEmulator 1926 early in the bootup. 1927 1928config FPE_NWFPE_XP 1929 bool "Support extended precision" 1930 depends on FPE_NWFPE 1931 help 1932 Say Y to include 80-bit support in the kernel floating-point 1933 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1934 Note that gcc does not generate 80-bit operations by default, 1935 so in most cases this option only enlarges the size of the 1936 floating point emulator without any good reason. 1937 1938 You almost surely want to say N here. 1939 1940config FPE_FASTFPE 1941 bool "FastFPE math emulation (EXPERIMENTAL)" 1942 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1943 help 1944 Say Y here to include the FAST floating point emulator in the kernel. 1945 This is an experimental much faster emulator which now also has full 1946 precision for the mantissa. It does not support any exceptions. 1947 It is very simple, and approximately 3-6 times faster than NWFPE. 1948 1949 It should be sufficient for most programs. It may be not suitable 1950 for scientific calculations, but you have to check this for yourself. 1951 If you do not feel you need a faster FP emulation you should better 1952 choose NWFPE. 1953 1954config VFP 1955 bool "VFP-format floating point maths" 1956 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1957 help 1958 Say Y to include VFP support code in the kernel. This is needed 1959 if your hardware includes a VFP unit. 1960 1961 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1962 release notes and additional status information. 1963 1964 Say N if your target does not have VFP hardware. 1965 1966config VFPv3 1967 bool 1968 depends on VFP 1969 default y if CPU_V7 1970 1971config NEON 1972 bool "Advanced SIMD (NEON) Extension support" 1973 depends on VFPv3 && CPU_V7 1974 help 1975 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1976 Extension. 1977 1978config KERNEL_MODE_NEON 1979 bool "Support for NEON in kernel mode" 1980 depends on NEON && AEABI 1981 help 1982 Say Y to include support for NEON in kernel mode. 1983 1984endmenu 1985 1986menu "Power management options" 1987 1988source "kernel/power/Kconfig" 1989 1990config ARCH_SUSPEND_POSSIBLE 1991 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1992 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1993 def_bool y 1994 1995config ARM_CPU_SUSPEND 1996 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1997 depends on ARCH_SUSPEND_POSSIBLE 1998 1999config ARCH_HIBERNATION_POSSIBLE 2000 bool 2001 depends on MMU 2002 default y if ARCH_SUSPEND_POSSIBLE 2003 2004endmenu 2005 2006source "drivers/firmware/Kconfig" 2007 2008if CRYPTO 2009source "arch/arm/crypto/Kconfig" 2010endif 2011 2012source "arch/arm/Kconfig.assembler" 2013