1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_MEMBARRIER_SYNC_CORE 13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 14 select ARCH_HAS_PHYS_TO_DMA 15 select ARCH_HAS_SET_MEMORY 16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 17 select ARCH_HAS_STRICT_MODULE_RWX if MMU 18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 19 select ARCH_HAVE_CUSTOM_GPIO_H 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_MIGHT_HAVE_PC_PARPORT 22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 24 select ARCH_SUPPORTS_ATOMIC_RMW 25 select ARCH_USE_BUILTIN_BSWAP 26 select ARCH_USE_CMPXCHG_LOCKREF 27 select ARCH_WANT_IPC_PARSE_VERSION 28 select BUILDTIME_EXTABLE_SORT if MMU 29 select CLONE_BACKWARDS 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 32 select DMA_DIRECT_OPS if !MMU 33 select EDAC_SUPPORT 34 select EDAC_ATOMIC_SCRUB 35 select GENERIC_ALLOCATOR 36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 39 select GENERIC_CPU_AUTOPROBE 40 select GENERIC_EARLY_IOREMAP 41 select GENERIC_IDLE_POLL_SETUP 42 select GENERIC_IRQ_PROBE 43 select GENERIC_IRQ_SHOW 44 select GENERIC_IRQ_SHOW_LEVEL 45 select GENERIC_PCI_IOMAP 46 select GENERIC_SCHED_CLOCK 47 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_STRNCPY_FROM_USER 49 select GENERIC_STRNLEN_USER 50 select HANDLE_DOMAIN_IRQ 51 select HARDIRQS_SW_RESEND 52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 56 select HAVE_ARCH_MMAP_RND_BITS if MMU 57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 59 select HAVE_ARCH_TRACEHOOK 60 select HAVE_ARM_SMCCC if CPU_V7 61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 62 select HAVE_CONTEXT_TRACKING 63 select HAVE_C_RECORDMCOUNT 64 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DMA_CONTIGUOUS if MMU 66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 69 select HAVE_EXIT_THREAD 70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 73 select HAVE_GCC_PLUGINS 74 select HAVE_GENERIC_DMA_COHERENT 75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 76 select HAVE_IDE if PCI || ISA || PCMCIA 77 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_KERNEL_GZIP 79 select HAVE_KERNEL_LZ4 80 select HAVE_KERNEL_LZMA 81 select HAVE_KERNEL_LZO 82 select HAVE_KERNEL_XZ 83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 84 select HAVE_KRETPROBES if (HAVE_KPROBES) 85 select HAVE_MOD_ARCH_SPECIFIC 86 select HAVE_NMI 87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 88 select HAVE_OPTPROBES if !THUMB2_KERNEL 89 select HAVE_PERF_EVENTS 90 select HAVE_PERF_REGS 91 select HAVE_PERF_USER_STACK_DUMP 92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 93 select HAVE_REGS_AND_STACK_ACCESS_API 94 select HAVE_RSEQ 95 select HAVE_STACKPROTECTOR 96 select HAVE_SYSCALL_TRACEPOINTS 97 select HAVE_UID16 98 select HAVE_VIRT_CPU_ACCOUNTING_GEN 99 select IRQ_FORCED_THREADING 100 select MODULES_USE_ELF_REL 101 select NEED_DMA_MAP_STATE 102 select OF_EARLY_FLATTREE if OF 103 select OF_RESERVED_MEM if OF 104 select OLD_SIGACTION 105 select OLD_SIGSUSPEND3 106 select PERF_USE_VMALLOC 107 select REFCOUNT_FULL 108 select RTC_LIB 109 select SYS_SUPPORTS_APM_EMULATION 110 # Above selects are sorted alphabetically; please add new ones 111 # according to that. Thanks. 112 help 113 The ARM series is a line of low-power-consumption RISC chip designs 114 licensed by ARM Ltd and targeted at embedded applications and 115 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 116 manufactured, but legacy ARM-based PC hardware remains popular in 117 Europe. There is an ARM Linux project with a web page at 118 <http://www.arm.linux.org.uk/>. 119 120config ARM_HAS_SG_CHAIN 121 select ARCH_HAS_SG_CHAIN 122 bool 123 124config ARM_DMA_USE_IOMMU 125 bool 126 select ARM_HAS_SG_CHAIN 127 select NEED_SG_DMA_LENGTH 128 129if ARM_DMA_USE_IOMMU 130 131config ARM_DMA_IOMMU_ALIGNMENT 132 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 133 range 4 9 134 default 8 135 help 136 DMA mapping framework by default aligns all buffers to the smallest 137 PAGE_SIZE order which is greater than or equal to the requested buffer 138 size. This works well for buffers up to a few hundreds kilobytes, but 139 for larger buffers it just a waste of address space. Drivers which has 140 relatively small addressing window (like 64Mib) might run out of 141 virtual space with just a few allocations. 142 143 With this parameter you can specify the maximum PAGE_SIZE order for 144 DMA IOMMU buffers. Larger buffers will be aligned only to this 145 specified order. The order is expressed as a power of two multiplied 146 by the PAGE_SIZE. 147 148endif 149 150config MIGHT_HAVE_PCI 151 bool 152 153config SYS_SUPPORTS_APM_EMULATION 154 bool 155 156config HAVE_TCM 157 bool 158 select GENERIC_ALLOCATOR 159 160config HAVE_PROC_CPU 161 bool 162 163config NO_IOPORT_MAP 164 bool 165 166config EISA 167 bool 168 ---help--- 169 The Extended Industry Standard Architecture (EISA) bus was 170 developed as an open alternative to the IBM MicroChannel bus. 171 172 The EISA bus provided some of the features of the IBM MicroChannel 173 bus while maintaining backward compatibility with cards made for 174 the older ISA bus. The EISA bus saw limited use between 1988 and 175 1995 when it was made obsolete by the PCI bus. 176 177 Say Y here if you are building a kernel for an EISA-based machine. 178 179 Otherwise, say N. 180 181config SBUS 182 bool 183 184config STACKTRACE_SUPPORT 185 bool 186 default y 187 188config LOCKDEP_SUPPORT 189 bool 190 default y 191 192config TRACE_IRQFLAGS_SUPPORT 193 bool 194 default !CPU_V7M 195 196config RWSEM_XCHGADD_ALGORITHM 197 bool 198 default y 199 200config ARCH_HAS_ILOG2_U32 201 bool 202 203config ARCH_HAS_ILOG2_U64 204 bool 205 206config ARCH_HAS_BANDGAP 207 bool 208 209config FIX_EARLYCON_MEM 210 def_bool y if MMU 211 212config GENERIC_HWEIGHT 213 bool 214 default y 215 216config GENERIC_CALIBRATE_DELAY 217 bool 218 default y 219 220config ARCH_MAY_HAVE_PC_FDC 221 bool 222 223config ZONE_DMA 224 bool 225 226config ARCH_SUPPORTS_UPROBES 227 def_bool y 228 229config ARCH_HAS_DMA_SET_COHERENT_MASK 230 bool 231 232config GENERIC_ISA_DMA 233 bool 234 235config FIQ 236 bool 237 238config NEED_RET_TO_USER 239 bool 240 241config ARCH_MTD_XIP 242 bool 243 244config ARM_PATCH_PHYS_VIRT 245 bool "Patch physical to virtual translations at runtime" if EMBEDDED 246 default y 247 depends on !XIP_KERNEL && MMU 248 help 249 Patch phys-to-virt and virt-to-phys translation functions at 250 boot and module load time according to the position of the 251 kernel in system memory. 252 253 This can only be used with non-XIP MMU kernels where the base 254 of physical memory is at a 16MB boundary. 255 256 Only disable this option if you know that you do not require 257 this feature (eg, building a kernel for a single machine) and 258 you need to shrink the kernel to the minimal size. 259 260config NEED_MACH_IO_H 261 bool 262 help 263 Select this when mach/io.h is required to provide special 264 definitions for this platform. The need for mach/io.h should 265 be avoided when possible. 266 267config NEED_MACH_MEMORY_H 268 bool 269 help 270 Select this when mach/memory.h is required to provide special 271 definitions for this platform. The need for mach/memory.h should 272 be avoided when possible. 273 274config PHYS_OFFSET 275 hex "Physical address of main memory" if MMU 276 depends on !ARM_PATCH_PHYS_VIRT 277 default DRAM_BASE if !MMU 278 default 0x00000000 if ARCH_EBSA110 || \ 279 ARCH_FOOTBRIDGE || \ 280 ARCH_INTEGRATOR || \ 281 ARCH_IOP13XX || \ 282 ARCH_KS8695 || \ 283 ARCH_REALVIEW 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0x20000000 if ARCH_S5PV210 286 default 0xc0000000 if ARCH_SA1100 287 help 288 Please provide the physical address corresponding to the 289 location of main memory in your system. 290 291config GENERIC_BUG 292 def_bool y 293 depends on BUG 294 295config PGTABLE_LEVELS 296 int 297 default 3 if ARM_LPAE 298 default 2 299 300menu "System Type" 301 302config MMU 303 bool "MMU-based Paged Memory Management Support" 304 default y 305 help 306 Select if you want MMU-based virtualised addressing space 307 support by paged memory management. If unsure, say 'Y'. 308 309config ARCH_MMAP_RND_BITS_MIN 310 default 8 311 312config ARCH_MMAP_RND_BITS_MAX 313 default 14 if PAGE_OFFSET=0x40000000 314 default 15 if PAGE_OFFSET=0x80000000 315 default 16 316 317# 318# The "ARM system type" choice list is ordered alphabetically by option 319# text. Please add new entries in the option alphabetic order. 320# 321choice 322 prompt "ARM system type" 323 default ARM_SINGLE_ARMV7M if !MMU 324 default ARCH_MULTIPLATFORM if MMU 325 326config ARCH_MULTIPLATFORM 327 bool "Allow multiple platforms to be selected" 328 depends on MMU 329 select ARM_HAS_SG_CHAIN 330 select ARM_PATCH_PHYS_VIRT 331 select AUTO_ZRELADDR 332 select TIMER_OF 333 select COMMON_CLK 334 select GENERIC_CLOCKEVENTS 335 select GENERIC_IRQ_MULTI_HANDLER 336 select MIGHT_HAVE_PCI 337 select PCI_DOMAINS if PCI 338 select SPARSE_IRQ 339 select USE_OF 340 341config ARM_SINGLE_ARMV7M 342 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 343 depends on !MMU 344 select ARM_NVIC 345 select AUTO_ZRELADDR 346 select TIMER_OF 347 select COMMON_CLK 348 select CPU_V7M 349 select GENERIC_CLOCKEVENTS 350 select NO_IOPORT_MAP 351 select SPARSE_IRQ 352 select USE_OF 353 354config ARCH_EBSA110 355 bool "EBSA-110" 356 select ARCH_USES_GETTIMEOFFSET 357 select CPU_SA110 358 select ISA 359 select NEED_MACH_IO_H 360 select NEED_MACH_MEMORY_H 361 select NO_IOPORT_MAP 362 help 363 This is an evaluation board for the StrongARM processor available 364 from Digital. It has limited hardware on-board, including an 365 Ethernet interface, two PCMCIA sockets, two serial ports and a 366 parallel port. 367 368config ARCH_EP93XX 369 bool "EP93xx-based" 370 select ARCH_SPARSEMEM_ENABLE 371 select ARM_AMBA 372 imply ARM_PATCH_PHYS_VIRT 373 select ARM_VIC 374 select AUTO_ZRELADDR 375 select CLKDEV_LOOKUP 376 select CLKSRC_MMIO 377 select CPU_ARM920T 378 select GENERIC_CLOCKEVENTS 379 select GPIOLIB 380 help 381 This enables support for the Cirrus EP93xx series of CPUs. 382 383config ARCH_FOOTBRIDGE 384 bool "FootBridge" 385 select CPU_SA110 386 select FOOTBRIDGE 387 select GENERIC_CLOCKEVENTS 388 select HAVE_IDE 389 select NEED_MACH_IO_H if !MMU 390 select NEED_MACH_MEMORY_H 391 help 392 Support for systems based on the DC21285 companion chip 393 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 394 395config ARCH_NETX 396 bool "Hilscher NetX based" 397 select ARM_VIC 398 select CLKSRC_MMIO 399 select CPU_ARM926T 400 select GENERIC_CLOCKEVENTS 401 help 402 This enables support for systems based on the Hilscher NetX Soc 403 404config ARCH_IOP13XX 405 bool "IOP13xx-based" 406 depends on MMU 407 select CPU_XSC3 408 select NEED_MACH_MEMORY_H 409 select NEED_RET_TO_USER 410 select PCI 411 select PLAT_IOP 412 select VMSPLIT_1G 413 select SPARSE_IRQ 414 help 415 Support for Intel's IOP13XX (XScale) family of processors. 416 417config ARCH_IOP32X 418 bool "IOP32x-based" 419 depends on MMU 420 select CPU_XSCALE 421 select GPIO_IOP 422 select GPIOLIB 423 select NEED_RET_TO_USER 424 select PCI 425 select PLAT_IOP 426 help 427 Support for Intel's 80219 and IOP32X (XScale) family of 428 processors. 429 430config ARCH_IOP33X 431 bool "IOP33x-based" 432 depends on MMU 433 select CPU_XSCALE 434 select GPIO_IOP 435 select GPIOLIB 436 select NEED_RET_TO_USER 437 select PCI 438 select PLAT_IOP 439 help 440 Support for Intel's IOP33X (XScale) family of processors. 441 442config ARCH_IXP4XX 443 bool "IXP4xx-based" 444 depends on MMU 445 select ARCH_HAS_DMA_SET_COHERENT_MASK 446 select ARCH_SUPPORTS_BIG_ENDIAN 447 select CLKSRC_MMIO 448 select CPU_XSCALE 449 select DMABOUNCE if PCI 450 select GENERIC_CLOCKEVENTS 451 select GPIOLIB 452 select MIGHT_HAVE_PCI 453 select NEED_MACH_IO_H 454 select USB_EHCI_BIG_ENDIAN_DESC 455 select USB_EHCI_BIG_ENDIAN_MMIO 456 help 457 Support for Intel's IXP4XX (XScale) family of processors. 458 459config ARCH_DOVE 460 bool "Marvell Dove" 461 select CPU_PJ4 462 select GENERIC_CLOCKEVENTS 463 select GENERIC_IRQ_MULTI_HANDLER 464 select GPIOLIB 465 select MIGHT_HAVE_PCI 466 select MVEBU_MBUS 467 select PINCTRL 468 select PINCTRL_DOVE 469 select PLAT_ORION_LEGACY 470 select SPARSE_IRQ 471 select PM_GENERIC_DOMAINS if PM 472 help 473 Support for the Marvell Dove SoC 88AP510 474 475config ARCH_KS8695 476 bool "Micrel/Kendin KS8695" 477 select CLKSRC_MMIO 478 select CPU_ARM922T 479 select GENERIC_CLOCKEVENTS 480 select GPIOLIB 481 select NEED_MACH_MEMORY_H 482 help 483 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 484 System-on-Chip devices. 485 486config ARCH_W90X900 487 bool "Nuvoton W90X900 CPU" 488 select CLKDEV_LOOKUP 489 select CLKSRC_MMIO 490 select CPU_ARM926T 491 select GENERIC_CLOCKEVENTS 492 select GPIOLIB 493 help 494 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 495 At present, the w90x900 has been renamed nuc900, regarding 496 the ARM series product line, you can login the following 497 link address to know more. 498 499 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 500 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 501 502config ARCH_LPC32XX 503 bool "NXP LPC32XX" 504 select ARM_AMBA 505 select CLKDEV_LOOKUP 506 select CLKSRC_LPC32XX 507 select COMMON_CLK 508 select CPU_ARM926T 509 select GENERIC_CLOCKEVENTS 510 select GENERIC_IRQ_MULTI_HANDLER 511 select GPIOLIB 512 select SPARSE_IRQ 513 select USE_OF 514 help 515 Support for the NXP LPC32XX family of processors 516 517config ARCH_PXA 518 bool "PXA2xx/PXA3xx-based" 519 depends on MMU 520 select ARCH_MTD_XIP 521 select ARM_CPU_SUSPEND if PM 522 select AUTO_ZRELADDR 523 select COMMON_CLK 524 select CLKDEV_LOOKUP 525 select CLKSRC_PXA 526 select CLKSRC_MMIO 527 select TIMER_OF 528 select CPU_XSCALE if !CPU_XSC3 529 select GENERIC_CLOCKEVENTS 530 select GENERIC_IRQ_MULTI_HANDLER 531 select GPIO_PXA 532 select GPIOLIB 533 select HAVE_IDE 534 select IRQ_DOMAIN 535 select PLAT_PXA 536 select SPARSE_IRQ 537 help 538 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 539 540config ARCH_RPC 541 bool "RiscPC" 542 depends on MMU 543 select ARCH_ACORN 544 select ARCH_MAY_HAVE_PC_FDC 545 select ARCH_SPARSEMEM_ENABLE 546 select ARCH_USES_GETTIMEOFFSET 547 select CPU_SA110 548 select FIQ 549 select HAVE_IDE 550 select HAVE_PATA_PLATFORM 551 select ISA_DMA_API 552 select NEED_MACH_IO_H 553 select NEED_MACH_MEMORY_H 554 select NO_IOPORT_MAP 555 help 556 On the Acorn Risc-PC, Linux can support the internal IDE disk and 557 CD-ROM interface, serial and parallel port, and the floppy drive. 558 559config ARCH_SA1100 560 bool "SA1100-based" 561 select ARCH_MTD_XIP 562 select ARCH_SPARSEMEM_ENABLE 563 select CLKDEV_LOOKUP 564 select CLKSRC_MMIO 565 select CLKSRC_PXA 566 select TIMER_OF if OF 567 select CPU_FREQ 568 select CPU_SA1100 569 select GENERIC_CLOCKEVENTS 570 select GENERIC_IRQ_MULTI_HANDLER 571 select GPIOLIB 572 select HAVE_IDE 573 select IRQ_DOMAIN 574 select ISA 575 select NEED_MACH_MEMORY_H 576 select SPARSE_IRQ 577 help 578 Support for StrongARM 11x0 based boards. 579 580config ARCH_S3C24XX 581 bool "Samsung S3C24XX SoCs" 582 select ATAGS 583 select CLKDEV_LOOKUP 584 select CLKSRC_SAMSUNG_PWM 585 select GENERIC_CLOCKEVENTS 586 select GPIO_SAMSUNG 587 select GPIOLIB 588 select GENERIC_IRQ_MULTI_HANDLER 589 select HAVE_S3C2410_I2C if I2C 590 select HAVE_S3C2410_WATCHDOG if WATCHDOG 591 select HAVE_S3C_RTC if RTC_CLASS 592 select NEED_MACH_IO_H 593 select SAMSUNG_ATAGS 594 select USE_OF 595 help 596 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 597 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 598 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 599 Samsung SMDK2410 development board (and derivatives). 600 601config ARCH_DAVINCI 602 bool "TI DaVinci" 603 select ARCH_HAS_HOLES_MEMORYMODEL 604 select COMMON_CLK 605 select CPU_ARM926T 606 select GENERIC_ALLOCATOR 607 select GENERIC_CLOCKEVENTS 608 select GENERIC_IRQ_CHIP 609 select GPIOLIB 610 select HAVE_IDE 611 select PM_GENERIC_DOMAINS if PM 612 select PM_GENERIC_DOMAINS_OF if PM && OF 613 select RESET_CONTROLLER 614 select USE_OF 615 select ZONE_DMA 616 help 617 Support for TI's DaVinci platform. 618 619config ARCH_OMAP1 620 bool "TI OMAP1" 621 depends on MMU 622 select ARCH_HAS_HOLES_MEMORYMODEL 623 select ARCH_OMAP 624 select CLKDEV_LOOKUP 625 select CLKSRC_MMIO 626 select GENERIC_CLOCKEVENTS 627 select GENERIC_IRQ_CHIP 628 select GENERIC_IRQ_MULTI_HANDLER 629 select GPIOLIB 630 select HAVE_IDE 631 select IRQ_DOMAIN 632 select NEED_MACH_IO_H if PCCARD 633 select NEED_MACH_MEMORY_H 634 select SPARSE_IRQ 635 help 636 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 637 638endchoice 639 640menu "Multiple platform selection" 641 depends on ARCH_MULTIPLATFORM 642 643comment "CPU Core family selection" 644 645config ARCH_MULTI_V4 646 bool "ARMv4 based platforms (FA526)" 647 depends on !ARCH_MULTI_V6_V7 648 select ARCH_MULTI_V4_V5 649 select CPU_FA526 650 651config ARCH_MULTI_V4T 652 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 653 depends on !ARCH_MULTI_V6_V7 654 select ARCH_MULTI_V4_V5 655 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 656 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 657 CPU_ARM925T || CPU_ARM940T) 658 659config ARCH_MULTI_V5 660 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 661 depends on !ARCH_MULTI_V6_V7 662 select ARCH_MULTI_V4_V5 663 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 664 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 665 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 666 667config ARCH_MULTI_V4_V5 668 bool 669 670config ARCH_MULTI_V6 671 bool "ARMv6 based platforms (ARM11)" 672 select ARCH_MULTI_V6_V7 673 select CPU_V6K 674 675config ARCH_MULTI_V7 676 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 677 default y 678 select ARCH_MULTI_V6_V7 679 select CPU_V7 680 select HAVE_SMP 681 682config ARCH_MULTI_V6_V7 683 bool 684 select MIGHT_HAVE_CACHE_L2X0 685 686config ARCH_MULTI_CPU_AUTO 687 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 688 select ARCH_MULTI_V5 689 690endmenu 691 692config ARCH_VIRT 693 bool "Dummy Virtual Machine" 694 depends on ARCH_MULTI_V7 695 select ARM_AMBA 696 select ARM_GIC 697 select ARM_GIC_V2M if PCI 698 select ARM_GIC_V3 699 select ARM_GIC_V3_ITS if PCI 700 select ARM_PSCI 701 select HAVE_ARM_ARCH_TIMER 702 select ARCH_SUPPORTS_BIG_ENDIAN 703 704# 705# This is sorted alphabetically by mach-* pathname. However, plat-* 706# Kconfigs may be included either alphabetically (according to the 707# plat- suffix) or along side the corresponding mach-* source. 708# 709source "arch/arm/mach-actions/Kconfig" 710 711source "arch/arm/mach-alpine/Kconfig" 712 713source "arch/arm/mach-artpec/Kconfig" 714 715source "arch/arm/mach-asm9260/Kconfig" 716 717source "arch/arm/mach-aspeed/Kconfig" 718 719source "arch/arm/mach-at91/Kconfig" 720 721source "arch/arm/mach-axxia/Kconfig" 722 723source "arch/arm/mach-bcm/Kconfig" 724 725source "arch/arm/mach-berlin/Kconfig" 726 727source "arch/arm/mach-clps711x/Kconfig" 728 729source "arch/arm/mach-cns3xxx/Kconfig" 730 731source "arch/arm/mach-davinci/Kconfig" 732 733source "arch/arm/mach-digicolor/Kconfig" 734 735source "arch/arm/mach-dove/Kconfig" 736 737source "arch/arm/mach-ep93xx/Kconfig" 738 739source "arch/arm/mach-exynos/Kconfig" 740source "arch/arm/plat-samsung/Kconfig" 741 742source "arch/arm/mach-footbridge/Kconfig" 743 744source "arch/arm/mach-gemini/Kconfig" 745 746source "arch/arm/mach-highbank/Kconfig" 747 748source "arch/arm/mach-hisi/Kconfig" 749 750source "arch/arm/mach-imx/Kconfig" 751 752source "arch/arm/mach-integrator/Kconfig" 753 754source "arch/arm/mach-iop13xx/Kconfig" 755 756source "arch/arm/mach-iop32x/Kconfig" 757 758source "arch/arm/mach-iop33x/Kconfig" 759 760source "arch/arm/mach-ixp4xx/Kconfig" 761 762source "arch/arm/mach-keystone/Kconfig" 763 764source "arch/arm/mach-ks8695/Kconfig" 765 766source "arch/arm/mach-mediatek/Kconfig" 767 768source "arch/arm/mach-meson/Kconfig" 769 770source "arch/arm/mach-mmp/Kconfig" 771 772source "arch/arm/mach-moxart/Kconfig" 773 774source "arch/arm/mach-mv78xx0/Kconfig" 775 776source "arch/arm/mach-mvebu/Kconfig" 777 778source "arch/arm/mach-mxs/Kconfig" 779 780source "arch/arm/mach-netx/Kconfig" 781 782source "arch/arm/mach-nomadik/Kconfig" 783 784source "arch/arm/mach-npcm/Kconfig" 785 786source "arch/arm/mach-nspire/Kconfig" 787 788source "arch/arm/plat-omap/Kconfig" 789 790source "arch/arm/mach-omap1/Kconfig" 791 792source "arch/arm/mach-omap2/Kconfig" 793 794source "arch/arm/mach-orion5x/Kconfig" 795 796source "arch/arm/mach-oxnas/Kconfig" 797 798source "arch/arm/mach-picoxcell/Kconfig" 799 800source "arch/arm/mach-prima2/Kconfig" 801 802source "arch/arm/mach-pxa/Kconfig" 803source "arch/arm/plat-pxa/Kconfig" 804 805source "arch/arm/mach-qcom/Kconfig" 806 807source "arch/arm/mach-realview/Kconfig" 808 809source "arch/arm/mach-rockchip/Kconfig" 810 811source "arch/arm/mach-s3c24xx/Kconfig" 812 813source "arch/arm/mach-s3c64xx/Kconfig" 814 815source "arch/arm/mach-s5pv210/Kconfig" 816 817source "arch/arm/mach-sa1100/Kconfig" 818 819source "arch/arm/mach-shmobile/Kconfig" 820 821source "arch/arm/mach-socfpga/Kconfig" 822 823source "arch/arm/mach-spear/Kconfig" 824 825source "arch/arm/mach-sti/Kconfig" 826 827source "arch/arm/mach-stm32/Kconfig" 828 829source "arch/arm/mach-sunxi/Kconfig" 830 831source "arch/arm/mach-tango/Kconfig" 832 833source "arch/arm/mach-tegra/Kconfig" 834 835source "arch/arm/mach-u300/Kconfig" 836 837source "arch/arm/mach-uniphier/Kconfig" 838 839source "arch/arm/mach-ux500/Kconfig" 840 841source "arch/arm/mach-versatile/Kconfig" 842 843source "arch/arm/mach-vexpress/Kconfig" 844source "arch/arm/plat-versatile/Kconfig" 845 846source "arch/arm/mach-vt8500/Kconfig" 847 848source "arch/arm/mach-w90x900/Kconfig" 849 850source "arch/arm/mach-zx/Kconfig" 851 852source "arch/arm/mach-zynq/Kconfig" 853 854# ARMv7-M architecture 855config ARCH_EFM32 856 bool "Energy Micro efm32" 857 depends on ARM_SINGLE_ARMV7M 858 select GPIOLIB 859 help 860 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 861 processors. 862 863config ARCH_LPC18XX 864 bool "NXP LPC18xx/LPC43xx" 865 depends on ARM_SINGLE_ARMV7M 866 select ARCH_HAS_RESET_CONTROLLER 867 select ARM_AMBA 868 select CLKSRC_LPC32XX 869 select PINCTRL 870 help 871 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 872 high performance microcontrollers. 873 874config ARCH_MPS2 875 bool "ARM MPS2 platform" 876 depends on ARM_SINGLE_ARMV7M 877 select ARM_AMBA 878 select CLKSRC_MPS2 879 help 880 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 881 with a range of available cores like Cortex-M3/M4/M7. 882 883 Please, note that depends which Application Note is used memory map 884 for the platform may vary, so adjustment of RAM base might be needed. 885 886# Definitions to make life easier 887config ARCH_ACORN 888 bool 889 890config PLAT_IOP 891 bool 892 select GENERIC_CLOCKEVENTS 893 894config PLAT_ORION 895 bool 896 select CLKSRC_MMIO 897 select COMMON_CLK 898 select GENERIC_IRQ_CHIP 899 select IRQ_DOMAIN 900 901config PLAT_ORION_LEGACY 902 bool 903 select PLAT_ORION 904 905config PLAT_PXA 906 bool 907 908config PLAT_VERSATILE 909 bool 910 911source "arch/arm/firmware/Kconfig" 912 913source arch/arm/mm/Kconfig 914 915config IWMMXT 916 bool "Enable iWMMXt support" 917 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 918 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 919 help 920 Enable support for iWMMXt context switching at run time if 921 running on a CPU that supports it. 922 923if !MMU 924source "arch/arm/Kconfig-nommu" 925endif 926 927config PJ4B_ERRATA_4742 928 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 929 depends on CPU_PJ4B && MACH_ARMADA_370 930 default y 931 help 932 When coming out of either a Wait for Interrupt (WFI) or a Wait for 933 Event (WFE) IDLE states, a specific timing sensitivity exists between 934 the retiring WFI/WFE instructions and the newly issued subsequent 935 instructions. This sensitivity can result in a CPU hang scenario. 936 Workaround: 937 The software must insert either a Data Synchronization Barrier (DSB) 938 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 939 instruction 940 941config ARM_ERRATA_326103 942 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 943 depends on CPU_V6 944 help 945 Executing a SWP instruction to read-only memory does not set bit 11 946 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 947 treat the access as a read, preventing a COW from occurring and 948 causing the faulting task to livelock. 949 950config ARM_ERRATA_411920 951 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 952 depends on CPU_V6 || CPU_V6K 953 help 954 Invalidation of the Instruction Cache operation can 955 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 956 It does not affect the MPCore. This option enables the ARM Ltd. 957 recommended workaround. 958 959config ARM_ERRATA_430973 960 bool "ARM errata: Stale prediction on replaced interworking branch" 961 depends on CPU_V7 962 help 963 This option enables the workaround for the 430973 Cortex-A8 964 r1p* erratum. If a code sequence containing an ARM/Thumb 965 interworking branch is replaced with another code sequence at the 966 same virtual address, whether due to self-modifying code or virtual 967 to physical address re-mapping, Cortex-A8 does not recover from the 968 stale interworking branch prediction. This results in Cortex-A8 969 executing the new code sequence in the incorrect ARM or Thumb state. 970 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 971 and also flushes the branch target cache at every context switch. 972 Note that setting specific bits in the ACTLR register may not be 973 available in non-secure mode. 974 975config ARM_ERRATA_458693 976 bool "ARM errata: Processor deadlock when a false hazard is created" 977 depends on CPU_V7 978 depends on !ARCH_MULTIPLATFORM 979 help 980 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 981 erratum. For very specific sequences of memory operations, it is 982 possible for a hazard condition intended for a cache line to instead 983 be incorrectly associated with a different cache line. This false 984 hazard might then cause a processor deadlock. The workaround enables 985 the L1 caching of the NEON accesses and disables the PLD instruction 986 in the ACTLR register. Note that setting specific bits in the ACTLR 987 register may not be available in non-secure mode. 988 989config ARM_ERRATA_460075 990 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 991 depends on CPU_V7 992 depends on !ARCH_MULTIPLATFORM 993 help 994 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 995 erratum. Any asynchronous access to the L2 cache may encounter a 996 situation in which recent store transactions to the L2 cache are lost 997 and overwritten with stale memory contents from external memory. The 998 workaround disables the write-allocate mode for the L2 cache via the 999 ACTLR register. Note that setting specific bits in the ACTLR register 1000 may not be available in non-secure mode. 1001 1002config ARM_ERRATA_742230 1003 bool "ARM errata: DMB operation may be faulty" 1004 depends on CPU_V7 && SMP 1005 depends on !ARCH_MULTIPLATFORM 1006 help 1007 This option enables the workaround for the 742230 Cortex-A9 1008 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1009 between two write operations may not ensure the correct visibility 1010 ordering of the two writes. This workaround sets a specific bit in 1011 the diagnostic register of the Cortex-A9 which causes the DMB 1012 instruction to behave as a DSB, ensuring the correct behaviour of 1013 the two writes. 1014 1015config ARM_ERRATA_742231 1016 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1017 depends on CPU_V7 && SMP 1018 depends on !ARCH_MULTIPLATFORM 1019 help 1020 This option enables the workaround for the 742231 Cortex-A9 1021 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1022 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1023 accessing some data located in the same cache line, may get corrupted 1024 data due to bad handling of the address hazard when the line gets 1025 replaced from one of the CPUs at the same time as another CPU is 1026 accessing it. This workaround sets specific bits in the diagnostic 1027 register of the Cortex-A9 which reduces the linefill issuing 1028 capabilities of the processor. 1029 1030config ARM_ERRATA_643719 1031 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1032 depends on CPU_V7 && SMP 1033 default y 1034 help 1035 This option enables the workaround for the 643719 Cortex-A9 (prior to 1036 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1037 register returns zero when it should return one. The workaround 1038 corrects this value, ensuring cache maintenance operations which use 1039 it behave as intended and avoiding data corruption. 1040 1041config ARM_ERRATA_720789 1042 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1043 depends on CPU_V7 1044 help 1045 This option enables the workaround for the 720789 Cortex-A9 (prior to 1046 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1047 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1048 As a consequence of this erratum, some TLB entries which should be 1049 invalidated are not, resulting in an incoherency in the system page 1050 tables. The workaround changes the TLB flushing routines to invalidate 1051 entries regardless of the ASID. 1052 1053config ARM_ERRATA_743622 1054 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1055 depends on CPU_V7 1056 depends on !ARCH_MULTIPLATFORM 1057 help 1058 This option enables the workaround for the 743622 Cortex-A9 1059 (r2p*) erratum. Under very rare conditions, a faulty 1060 optimisation in the Cortex-A9 Store Buffer may lead to data 1061 corruption. This workaround sets a specific bit in the diagnostic 1062 register of the Cortex-A9 which disables the Store Buffer 1063 optimisation, preventing the defect from occurring. This has no 1064 visible impact on the overall performance or power consumption of the 1065 processor. 1066 1067config ARM_ERRATA_751472 1068 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1069 depends on CPU_V7 1070 depends on !ARCH_MULTIPLATFORM 1071 help 1072 This option enables the workaround for the 751472 Cortex-A9 (prior 1073 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1074 completion of a following broadcasted operation if the second 1075 operation is received by a CPU before the ICIALLUIS has completed, 1076 potentially leading to corrupted entries in the cache or TLB. 1077 1078config ARM_ERRATA_754322 1079 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1080 depends on CPU_V7 1081 help 1082 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1083 r3p*) erratum. A speculative memory access may cause a page table walk 1084 which starts prior to an ASID switch but completes afterwards. This 1085 can populate the micro-TLB with a stale entry which may be hit with 1086 the new ASID. This workaround places two dsb instructions in the mm 1087 switching code so that no page table walks can cross the ASID switch. 1088 1089config ARM_ERRATA_754327 1090 bool "ARM errata: no automatic Store Buffer drain" 1091 depends on CPU_V7 && SMP 1092 help 1093 This option enables the workaround for the 754327 Cortex-A9 (prior to 1094 r2p0) erratum. The Store Buffer does not have any automatic draining 1095 mechanism and therefore a livelock may occur if an external agent 1096 continuously polls a memory location waiting to observe an update. 1097 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1098 written polling loops from denying visibility of updates to memory. 1099 1100config ARM_ERRATA_364296 1101 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1102 depends on CPU_V6 1103 help 1104 This options enables the workaround for the 364296 ARM1136 1105 r0p2 erratum (possible cache data corruption with 1106 hit-under-miss enabled). It sets the undocumented bit 31 in 1107 the auxiliary control register and the FI bit in the control 1108 register, thus disabling hit-under-miss without putting the 1109 processor into full low interrupt latency mode. ARM11MPCore 1110 is not affected. 1111 1112config ARM_ERRATA_764369 1113 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1114 depends on CPU_V7 && SMP 1115 help 1116 This option enables the workaround for erratum 764369 1117 affecting Cortex-A9 MPCore with two or more processors (all 1118 current revisions). Under certain timing circumstances, a data 1119 cache line maintenance operation by MVA targeting an Inner 1120 Shareable memory region may fail to proceed up to either the 1121 Point of Coherency or to the Point of Unification of the 1122 system. This workaround adds a DSB instruction before the 1123 relevant cache maintenance functions and sets a specific bit 1124 in the diagnostic control register of the SCU. 1125 1126config ARM_ERRATA_775420 1127 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1128 depends on CPU_V7 1129 help 1130 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1131 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1132 operation aborts with MMU exception, it might cause the processor 1133 to deadlock. This workaround puts DSB before executing ISB if 1134 an abort may occur on cache maintenance. 1135 1136config ARM_ERRATA_798181 1137 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1138 depends on CPU_V7 && SMP 1139 help 1140 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1141 adequately shooting down all use of the old entries. This 1142 option enables the Linux kernel workaround for this erratum 1143 which sends an IPI to the CPUs that are running the same ASID 1144 as the one being invalidated. 1145 1146config ARM_ERRATA_773022 1147 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1148 depends on CPU_V7 1149 help 1150 This option enables the workaround for the 773022 Cortex-A15 1151 (up to r0p4) erratum. In certain rare sequences of code, the 1152 loop buffer may deliver incorrect instructions. This 1153 workaround disables the loop buffer to avoid the erratum. 1154 1155config ARM_ERRATA_818325_852422 1156 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1157 depends on CPU_V7 1158 help 1159 This option enables the workaround for: 1160 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1161 instruction might deadlock. Fixed in r0p1. 1162 - Cortex-A12 852422: Execution of a sequence of instructions might 1163 lead to either a data corruption or a CPU deadlock. Not fixed in 1164 any Cortex-A12 cores yet. 1165 This workaround for all both errata involves setting bit[12] of the 1166 Feature Register. This bit disables an optimisation applied to a 1167 sequence of 2 instructions that use opposing condition codes. 1168 1169config ARM_ERRATA_821420 1170 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1171 depends on CPU_V7 1172 help 1173 This option enables the workaround for the 821420 Cortex-A12 1174 (all revs) erratum. In very rare timing conditions, a sequence 1175 of VMOV to Core registers instructions, for which the second 1176 one is in the shadow of a branch or abort, can lead to a 1177 deadlock when the VMOV instructions are issued out-of-order. 1178 1179config ARM_ERRATA_825619 1180 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1181 depends on CPU_V7 1182 help 1183 This option enables the workaround for the 825619 Cortex-A12 1184 (all revs) erratum. Within rare timing constraints, executing a 1185 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1186 and Device/Strongly-Ordered loads and stores might cause deadlock 1187 1188config ARM_ERRATA_852421 1189 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1190 depends on CPU_V7 1191 help 1192 This option enables the workaround for the 852421 Cortex-A17 1193 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1194 execution of a DMB ST instruction might fail to properly order 1195 stores from GroupA and stores from GroupB. 1196 1197config ARM_ERRATA_852423 1198 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1199 depends on CPU_V7 1200 help 1201 This option enables the workaround for: 1202 - Cortex-A17 852423: Execution of a sequence of instructions might 1203 lead to either a data corruption or a CPU deadlock. Not fixed in 1204 any Cortex-A17 cores yet. 1205 This is identical to Cortex-A12 erratum 852422. It is a separate 1206 config option from the A12 erratum due to the way errata are checked 1207 for and handled. 1208 1209endmenu 1210 1211source "arch/arm/common/Kconfig" 1212 1213menu "Bus support" 1214 1215config ISA 1216 bool 1217 help 1218 Find out whether you have ISA slots on your motherboard. ISA is the 1219 name of a bus system, i.e. the way the CPU talks to the other stuff 1220 inside your box. Other bus systems are PCI, EISA, MicroChannel 1221 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1222 newer boards don't support it. If you have ISA, say Y, otherwise N. 1223 1224# Select ISA DMA controller support 1225config ISA_DMA 1226 bool 1227 select ISA_DMA_API 1228 1229# Select ISA DMA interface 1230config ISA_DMA_API 1231 bool 1232 1233config PCI 1234 bool "PCI support" if MIGHT_HAVE_PCI 1235 help 1236 Find out whether you have a PCI motherboard. PCI is the name of a 1237 bus system, i.e. the way the CPU talks to the other stuff inside 1238 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1239 VESA. If you have PCI, say Y, otherwise N. 1240 1241config PCI_DOMAINS 1242 bool "Support for multiple PCI domains" 1243 depends on PCI 1244 help 1245 Enable PCI domains kernel management. Say Y if your machine 1246 has a PCI bus hierarchy that requires more than one PCI 1247 domain (aka segment) to be correctly managed. Say N otherwise. 1248 1249 If you don't know what to do here, say N. 1250 1251config PCI_DOMAINS_GENERIC 1252 def_bool PCI_DOMAINS 1253 1254config PCI_NANOENGINE 1255 bool "BSE nanoEngine PCI support" 1256 depends on SA1100_NANOENGINE 1257 help 1258 Enable PCI on the BSE nanoEngine board. 1259 1260config PCI_SYSCALL 1261 def_bool PCI 1262 1263config PCI_HOST_ITE8152 1264 bool 1265 depends on PCI && MACH_ARMCORE 1266 default y 1267 select DMABOUNCE 1268 1269source "drivers/pci/Kconfig" 1270 1271source "drivers/pcmcia/Kconfig" 1272 1273endmenu 1274 1275menu "Kernel Features" 1276 1277config HAVE_SMP 1278 bool 1279 help 1280 This option should be selected by machines which have an SMP- 1281 capable CPU. 1282 1283 The only effect of this option is to make the SMP-related 1284 options available to the user for configuration. 1285 1286config SMP 1287 bool "Symmetric Multi-Processing" 1288 depends on CPU_V6K || CPU_V7 1289 depends on GENERIC_CLOCKEVENTS 1290 depends on HAVE_SMP 1291 depends on MMU || ARM_MPU 1292 select IRQ_WORK 1293 help 1294 This enables support for systems with more than one CPU. If you have 1295 a system with only one CPU, say N. If you have a system with more 1296 than one CPU, say Y. 1297 1298 If you say N here, the kernel will run on uni- and multiprocessor 1299 machines, but will use only one CPU of a multiprocessor machine. If 1300 you say Y here, the kernel will run on many, but not all, 1301 uniprocessor machines. On a uniprocessor machine, the kernel 1302 will run faster if you say N here. 1303 1304 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1305 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1306 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1307 1308 If you don't know what to do here, say N. 1309 1310config SMP_ON_UP 1311 bool "Allow booting SMP kernel on uniprocessor systems" 1312 depends on SMP && !XIP_KERNEL && MMU 1313 default y 1314 help 1315 SMP kernels contain instructions which fail on non-SMP processors. 1316 Enabling this option allows the kernel to modify itself to make 1317 these instructions safe. Disabling it allows about 1K of space 1318 savings. 1319 1320 If you don't know what to do here, say Y. 1321 1322config ARM_CPU_TOPOLOGY 1323 bool "Support cpu topology definition" 1324 depends on SMP && CPU_V7 1325 default y 1326 help 1327 Support ARM cpu topology definition. The MPIDR register defines 1328 affinity between processors which is then used to describe the cpu 1329 topology of an ARM System. 1330 1331config SCHED_MC 1332 bool "Multi-core scheduler support" 1333 depends on ARM_CPU_TOPOLOGY 1334 help 1335 Multi-core scheduler support improves the CPU scheduler's decision 1336 making when dealing with multi-core CPU chips at a cost of slightly 1337 increased overhead in some places. If unsure say N here. 1338 1339config SCHED_SMT 1340 bool "SMT scheduler support" 1341 depends on ARM_CPU_TOPOLOGY 1342 help 1343 Improves the CPU scheduler's decision making when dealing with 1344 MultiThreading at a cost of slightly increased overhead in some 1345 places. If unsure say N here. 1346 1347config HAVE_ARM_SCU 1348 bool 1349 help 1350 This option enables support for the ARM system coherency unit 1351 1352config HAVE_ARM_ARCH_TIMER 1353 bool "Architected timer support" 1354 depends on CPU_V7 1355 select ARM_ARCH_TIMER 1356 select GENERIC_CLOCKEVENTS 1357 help 1358 This option enables support for the ARM architected timer 1359 1360config HAVE_ARM_TWD 1361 bool 1362 select TIMER_OF if OF 1363 help 1364 This options enables support for the ARM timer and watchdog unit 1365 1366config MCPM 1367 bool "Multi-Cluster Power Management" 1368 depends on CPU_V7 && SMP 1369 help 1370 This option provides the common power management infrastructure 1371 for (multi-)cluster based systems, such as big.LITTLE based 1372 systems. 1373 1374config MCPM_QUAD_CLUSTER 1375 bool 1376 depends on MCPM 1377 help 1378 To avoid wasting resources unnecessarily, MCPM only supports up 1379 to 2 clusters by default. 1380 Platforms with 3 or 4 clusters that use MCPM must select this 1381 option to allow the additional clusters to be managed. 1382 1383config BIG_LITTLE 1384 bool "big.LITTLE support (Experimental)" 1385 depends on CPU_V7 && SMP 1386 select MCPM 1387 help 1388 This option enables support selections for the big.LITTLE 1389 system architecture. 1390 1391config BL_SWITCHER 1392 bool "big.LITTLE switcher support" 1393 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1394 select CPU_PM 1395 help 1396 The big.LITTLE "switcher" provides the core functionality to 1397 transparently handle transition between a cluster of A15's 1398 and a cluster of A7's in a big.LITTLE system. 1399 1400config BL_SWITCHER_DUMMY_IF 1401 tristate "Simple big.LITTLE switcher user interface" 1402 depends on BL_SWITCHER && DEBUG_KERNEL 1403 help 1404 This is a simple and dummy char dev interface to control 1405 the big.LITTLE switcher core code. It is meant for 1406 debugging purposes only. 1407 1408choice 1409 prompt "Memory split" 1410 depends on MMU 1411 default VMSPLIT_3G 1412 help 1413 Select the desired split between kernel and user memory. 1414 1415 If you are not absolutely sure what you are doing, leave this 1416 option alone! 1417 1418 config VMSPLIT_3G 1419 bool "3G/1G user/kernel split" 1420 config VMSPLIT_3G_OPT 1421 depends on !ARM_LPAE 1422 bool "3G/1G user/kernel split (for full 1G low memory)" 1423 config VMSPLIT_2G 1424 bool "2G/2G user/kernel split" 1425 config VMSPLIT_1G 1426 bool "1G/3G user/kernel split" 1427endchoice 1428 1429config PAGE_OFFSET 1430 hex 1431 default PHYS_OFFSET if !MMU 1432 default 0x40000000 if VMSPLIT_1G 1433 default 0x80000000 if VMSPLIT_2G 1434 default 0xB0000000 if VMSPLIT_3G_OPT 1435 default 0xC0000000 1436 1437config NR_CPUS 1438 int "Maximum number of CPUs (2-32)" 1439 range 2 32 1440 depends on SMP 1441 default "4" 1442 1443config HOTPLUG_CPU 1444 bool "Support for hot-pluggable CPUs" 1445 depends on SMP 1446 help 1447 Say Y here to experiment with turning CPUs off and on. CPUs 1448 can be controlled through /sys/devices/system/cpu. 1449 1450config ARM_PSCI 1451 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1452 depends on HAVE_ARM_SMCCC 1453 select ARM_PSCI_FW 1454 help 1455 Say Y here if you want Linux to communicate with system firmware 1456 implementing the PSCI specification for CPU-centric power 1457 management operations described in ARM document number ARM DEN 1458 0022A ("Power State Coordination Interface System Software on 1459 ARM processors"). 1460 1461# The GPIO number here must be sorted by descending number. In case of 1462# a multiplatform kernel, we just want the highest value required by the 1463# selected platforms. 1464config ARCH_NR_GPIO 1465 int 1466 default 2048 if ARCH_SOCFPGA 1467 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1468 ARCH_ZYNQ 1469 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1470 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1471 default 416 if ARCH_SUNXI 1472 default 392 if ARCH_U8500 1473 default 352 if ARCH_VT8500 1474 default 288 if ARCH_ROCKCHIP 1475 default 264 if MACH_H4700 1476 default 0 1477 help 1478 Maximum number of GPIOs in the system. 1479 1480 If unsure, leave the default value. 1481 1482config HZ_FIXED 1483 int 1484 default 200 if ARCH_EBSA110 1485 default 128 if SOC_AT91RM9200 1486 default 0 1487 1488choice 1489 depends on HZ_FIXED = 0 1490 prompt "Timer frequency" 1491 1492config HZ_100 1493 bool "100 Hz" 1494 1495config HZ_200 1496 bool "200 Hz" 1497 1498config HZ_250 1499 bool "250 Hz" 1500 1501config HZ_300 1502 bool "300 Hz" 1503 1504config HZ_500 1505 bool "500 Hz" 1506 1507config HZ_1000 1508 bool "1000 Hz" 1509 1510endchoice 1511 1512config HZ 1513 int 1514 default HZ_FIXED if HZ_FIXED != 0 1515 default 100 if HZ_100 1516 default 200 if HZ_200 1517 default 250 if HZ_250 1518 default 300 if HZ_300 1519 default 500 if HZ_500 1520 default 1000 1521 1522config SCHED_HRTICK 1523 def_bool HIGH_RES_TIMERS 1524 1525config THUMB2_KERNEL 1526 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1527 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1528 default y if CPU_THUMBONLY 1529 select ARM_UNWIND 1530 help 1531 By enabling this option, the kernel will be compiled in 1532 Thumb-2 mode. 1533 1534 If unsure, say N. 1535 1536config THUMB2_AVOID_R_ARM_THM_JUMP11 1537 bool "Work around buggy Thumb-2 short branch relocations in gas" 1538 depends on THUMB2_KERNEL && MODULES 1539 default y 1540 help 1541 Various binutils versions can resolve Thumb-2 branches to 1542 locally-defined, preemptible global symbols as short-range "b.n" 1543 branch instructions. 1544 1545 This is a problem, because there's no guarantee the final 1546 destination of the symbol, or any candidate locations for a 1547 trampoline, are within range of the branch. For this reason, the 1548 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1549 relocation in modules at all, and it makes little sense to add 1550 support. 1551 1552 The symptom is that the kernel fails with an "unsupported 1553 relocation" error when loading some modules. 1554 1555 Until fixed tools are available, passing 1556 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1557 code which hits this problem, at the cost of a bit of extra runtime 1558 stack usage in some cases. 1559 1560 The problem is described in more detail at: 1561 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1562 1563 Only Thumb-2 kernels are affected. 1564 1565 Unless you are sure your tools don't have this problem, say Y. 1566 1567config ARM_PATCH_IDIV 1568 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1569 depends on CPU_32v7 && !XIP_KERNEL 1570 default y 1571 help 1572 The ARM compiler inserts calls to __aeabi_idiv() and 1573 __aeabi_uidiv() when it needs to perform division on signed 1574 and unsigned integers. Some v7 CPUs have support for the sdiv 1575 and udiv instructions that can be used to implement those 1576 functions. 1577 1578 Enabling this option allows the kernel to modify itself to 1579 replace the first two instructions of these library functions 1580 with the sdiv or udiv plus "bx lr" instructions when the CPU 1581 it is running on supports them. Typically this will be faster 1582 and less power intensive than running the original library 1583 code to do integer division. 1584 1585config AEABI 1586 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1587 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1588 help 1589 This option allows for the kernel to be compiled using the latest 1590 ARM ABI (aka EABI). This is only useful if you are using a user 1591 space environment that is also compiled with EABI. 1592 1593 Since there are major incompatibilities between the legacy ABI and 1594 EABI, especially with regard to structure member alignment, this 1595 option also changes the kernel syscall calling convention to 1596 disambiguate both ABIs and allow for backward compatibility support 1597 (selected with CONFIG_OABI_COMPAT). 1598 1599 To use this you need GCC version 4.0.0 or later. 1600 1601config OABI_COMPAT 1602 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1603 depends on AEABI && !THUMB2_KERNEL 1604 help 1605 This option preserves the old syscall interface along with the 1606 new (ARM EABI) one. It also provides a compatibility layer to 1607 intercept syscalls that have structure arguments which layout 1608 in memory differs between the legacy ABI and the new ARM EABI 1609 (only for non "thumb" binaries). This option adds a tiny 1610 overhead to all syscalls and produces a slightly larger kernel. 1611 1612 The seccomp filter system will not be available when this is 1613 selected, since there is no way yet to sensibly distinguish 1614 between calling conventions during filtering. 1615 1616 If you know you'll be using only pure EABI user space then you 1617 can say N here. If this option is not selected and you attempt 1618 to execute a legacy ABI binary then the result will be 1619 UNPREDICTABLE (in fact it can be predicted that it won't work 1620 at all). If in doubt say N. 1621 1622config ARCH_HAS_HOLES_MEMORYMODEL 1623 bool 1624 1625config ARCH_SPARSEMEM_ENABLE 1626 bool 1627 1628config ARCH_SPARSEMEM_DEFAULT 1629 def_bool ARCH_SPARSEMEM_ENABLE 1630 1631config ARCH_SELECT_MEMORY_MODEL 1632 def_bool ARCH_SPARSEMEM_ENABLE 1633 1634config HAVE_ARCH_PFN_VALID 1635 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1636 1637config HAVE_GENERIC_GUP 1638 def_bool y 1639 depends on ARM_LPAE 1640 1641config HIGHMEM 1642 bool "High Memory Support" 1643 depends on MMU 1644 help 1645 The address space of ARM processors is only 4 Gigabytes large 1646 and it has to accommodate user address space, kernel address 1647 space as well as some memory mapped IO. That means that, if you 1648 have a large amount of physical memory and/or IO, not all of the 1649 memory can be "permanently mapped" by the kernel. The physical 1650 memory that is not permanently mapped is called "high memory". 1651 1652 Depending on the selected kernel/user memory split, minimum 1653 vmalloc space and actual amount of RAM, you may not need this 1654 option which should result in a slightly faster kernel. 1655 1656 If unsure, say n. 1657 1658config HIGHPTE 1659 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1660 depends on HIGHMEM 1661 default y 1662 help 1663 The VM uses one page of physical memory for each page table. 1664 For systems with a lot of processes, this can use a lot of 1665 precious low memory, eventually leading to low memory being 1666 consumed by page tables. Setting this option will allow 1667 user-space 2nd level page tables to reside in high memory. 1668 1669config CPU_SW_DOMAIN_PAN 1670 bool "Enable use of CPU domains to implement privileged no-access" 1671 depends on MMU && !ARM_LPAE 1672 default y 1673 help 1674 Increase kernel security by ensuring that normal kernel accesses 1675 are unable to access userspace addresses. This can help prevent 1676 use-after-free bugs becoming an exploitable privilege escalation 1677 by ensuring that magic values (such as LIST_POISON) will always 1678 fault when dereferenced. 1679 1680 CPUs with low-vector mappings use a best-efforts implementation. 1681 Their lower 1MB needs to remain accessible for the vectors, but 1682 the remainder of userspace will become appropriately inaccessible. 1683 1684config HW_PERF_EVENTS 1685 def_bool y 1686 depends on ARM_PMU 1687 1688config SYS_SUPPORTS_HUGETLBFS 1689 def_bool y 1690 depends on ARM_LPAE 1691 1692config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1693 def_bool y 1694 depends on ARM_LPAE 1695 1696config ARCH_WANT_GENERAL_HUGETLB 1697 def_bool y 1698 1699config ARM_MODULE_PLTS 1700 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1701 depends on MODULES 1702 default y 1703 help 1704 Allocate PLTs when loading modules so that jumps and calls whose 1705 targets are too far away for their relative offsets to be encoded 1706 in the instructions themselves can be bounced via veneers in the 1707 module's PLT. This allows modules to be allocated in the generic 1708 vmalloc area after the dedicated module memory area has been 1709 exhausted. The modules will use slightly more memory, but after 1710 rounding up to page size, the actual memory footprint is usually 1711 the same. 1712 1713 Disabling this is usually safe for small single-platform 1714 configurations. If unsure, say y. 1715 1716config FORCE_MAX_ZONEORDER 1717 int "Maximum zone order" 1718 default "12" if SOC_AM33XX 1719 default "9" if SA1111 || ARCH_EFM32 1720 default "11" 1721 help 1722 The kernel memory allocator divides physically contiguous memory 1723 blocks into "zones", where each zone is a power of two number of 1724 pages. This option selects the largest power of two that the kernel 1725 keeps in the memory allocator. If you need to allocate very large 1726 blocks of physically contiguous memory, then you may need to 1727 increase this value. 1728 1729 This config option is actually maximum order plus one. For example, 1730 a value of 11 means that the largest free memory block is 2^10 pages. 1731 1732config ALIGNMENT_TRAP 1733 bool 1734 depends on CPU_CP15_MMU 1735 default y if !ARCH_EBSA110 1736 select HAVE_PROC_CPU if PROC_FS 1737 help 1738 ARM processors cannot fetch/store information which is not 1739 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1740 address divisible by 4. On 32-bit ARM processors, these non-aligned 1741 fetch/store instructions will be emulated in software if you say 1742 here, which has a severe performance impact. This is necessary for 1743 correct operation of some network protocols. With an IP-only 1744 configuration it is safe to say N, otherwise say Y. 1745 1746config UACCESS_WITH_MEMCPY 1747 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1748 depends on MMU 1749 default y if CPU_FEROCEON 1750 help 1751 Implement faster copy_to_user and clear_user methods for CPU 1752 cores where a 8-word STM instruction give significantly higher 1753 memory write throughput than a sequence of individual 32bit stores. 1754 1755 A possible side effect is a slight increase in scheduling latency 1756 between threads sharing the same address space if they invoke 1757 such copy operations with large buffers. 1758 1759 However, if the CPU data cache is using a write-allocate mode, 1760 this option is unlikely to provide any performance gain. 1761 1762config SECCOMP 1763 bool 1764 prompt "Enable seccomp to safely compute untrusted bytecode" 1765 ---help--- 1766 This kernel feature is useful for number crunching applications 1767 that may need to compute untrusted bytecode during their 1768 execution. By using pipes or other transports made available to 1769 the process as file descriptors supporting the read/write 1770 syscalls, it's possible to isolate those applications in 1771 their own address space using seccomp. Once seccomp is 1772 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1773 and the task is only allowed to execute a few safe syscalls 1774 defined by each seccomp mode. 1775 1776config PARAVIRT 1777 bool "Enable paravirtualization code" 1778 help 1779 This changes the kernel so it can modify itself when it is run 1780 under a hypervisor, potentially improving performance significantly 1781 over full virtualization. 1782 1783config PARAVIRT_TIME_ACCOUNTING 1784 bool "Paravirtual steal time accounting" 1785 select PARAVIRT 1786 default n 1787 help 1788 Select this option to enable fine granularity task steal time 1789 accounting. Time spent executing other tasks in parallel with 1790 the current vCPU is discounted from the vCPU power. To account for 1791 that, there can be a small performance impact. 1792 1793 If in doubt, say N here. 1794 1795config XEN_DOM0 1796 def_bool y 1797 depends on XEN 1798 1799config XEN 1800 bool "Xen guest support on ARM" 1801 depends on ARM && AEABI && OF 1802 depends on CPU_V7 && !CPU_V6 1803 depends on !GENERIC_ATOMIC64 1804 depends on MMU 1805 select ARCH_DMA_ADDR_T_64BIT 1806 select ARM_PSCI 1807 select SWIOTLB 1808 select SWIOTLB_XEN 1809 select PARAVIRT 1810 help 1811 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1812 1813endmenu 1814 1815menu "Boot options" 1816 1817config USE_OF 1818 bool "Flattened Device Tree support" 1819 select IRQ_DOMAIN 1820 select OF 1821 help 1822 Include support for flattened device tree machine descriptions. 1823 1824config ATAGS 1825 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1826 default y 1827 help 1828 This is the traditional way of passing data to the kernel at boot 1829 time. If you are solely relying on the flattened device tree (or 1830 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1831 to remove ATAGS support from your kernel binary. If unsure, 1832 leave this to y. 1833 1834config DEPRECATED_PARAM_STRUCT 1835 bool "Provide old way to pass kernel parameters" 1836 depends on ATAGS 1837 help 1838 This was deprecated in 2001 and announced to live on for 5 years. 1839 Some old boot loaders still use this way. 1840 1841# Compressed boot loader in ROM. Yes, we really want to ask about 1842# TEXT and BSS so we preserve their values in the config files. 1843config ZBOOT_ROM_TEXT 1844 hex "Compressed ROM boot loader base address" 1845 default "0" 1846 help 1847 The physical address at which the ROM-able zImage is to be 1848 placed in the target. Platforms which normally make use of 1849 ROM-able zImage formats normally set this to a suitable 1850 value in their defconfig file. 1851 1852 If ZBOOT_ROM is not enabled, this has no effect. 1853 1854config ZBOOT_ROM_BSS 1855 hex "Compressed ROM boot loader BSS address" 1856 default "0" 1857 help 1858 The base address of an area of read/write memory in the target 1859 for the ROM-able zImage which must be available while the 1860 decompressor is running. It must be large enough to hold the 1861 entire decompressed kernel plus an additional 128 KiB. 1862 Platforms which normally make use of ROM-able zImage formats 1863 normally set this to a suitable value in their defconfig file. 1864 1865 If ZBOOT_ROM is not enabled, this has no effect. 1866 1867config ZBOOT_ROM 1868 bool "Compressed boot loader in ROM/flash" 1869 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1870 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1871 help 1872 Say Y here if you intend to execute your compressed kernel image 1873 (zImage) directly from ROM or flash. If unsure, say N. 1874 1875config ARM_APPENDED_DTB 1876 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1877 depends on OF 1878 help 1879 With this option, the boot code will look for a device tree binary 1880 (DTB) appended to zImage 1881 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1882 1883 This is meant as a backward compatibility convenience for those 1884 systems with a bootloader that can't be upgraded to accommodate 1885 the documented boot protocol using a device tree. 1886 1887 Beware that there is very little in terms of protection against 1888 this option being confused by leftover garbage in memory that might 1889 look like a DTB header after a reboot if no actual DTB is appended 1890 to zImage. Do not leave this option active in a production kernel 1891 if you don't intend to always append a DTB. Proper passing of the 1892 location into r2 of a bootloader provided DTB is always preferable 1893 to this option. 1894 1895config ARM_ATAG_DTB_COMPAT 1896 bool "Supplement the appended DTB with traditional ATAG information" 1897 depends on ARM_APPENDED_DTB 1898 help 1899 Some old bootloaders can't be updated to a DTB capable one, yet 1900 they provide ATAGs with memory configuration, the ramdisk address, 1901 the kernel cmdline string, etc. Such information is dynamically 1902 provided by the bootloader and can't always be stored in a static 1903 DTB. To allow a device tree enabled kernel to be used with such 1904 bootloaders, this option allows zImage to extract the information 1905 from the ATAG list and store it at run time into the appended DTB. 1906 1907choice 1908 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1909 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1910 1911config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1912 bool "Use bootloader kernel arguments if available" 1913 help 1914 Uses the command-line options passed by the boot loader instead of 1915 the device tree bootargs property. If the boot loader doesn't provide 1916 any, the device tree bootargs property will be used. 1917 1918config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1919 bool "Extend with bootloader kernel arguments" 1920 help 1921 The command-line arguments provided by the boot loader will be 1922 appended to the the device tree bootargs property. 1923 1924endchoice 1925 1926config CMDLINE 1927 string "Default kernel command string" 1928 default "" 1929 help 1930 On some architectures (EBSA110 and CATS), there is currently no way 1931 for the boot loader to pass arguments to the kernel. For these 1932 architectures, you should supply some command-line options at build 1933 time by entering them here. As a minimum, you should specify the 1934 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1935 1936choice 1937 prompt "Kernel command line type" if CMDLINE != "" 1938 default CMDLINE_FROM_BOOTLOADER 1939 depends on ATAGS 1940 1941config CMDLINE_FROM_BOOTLOADER 1942 bool "Use bootloader kernel arguments if available" 1943 help 1944 Uses the command-line options passed by the boot loader. If 1945 the boot loader doesn't provide any, the default kernel command 1946 string provided in CMDLINE will be used. 1947 1948config CMDLINE_EXTEND 1949 bool "Extend bootloader kernel arguments" 1950 help 1951 The command-line arguments provided by the boot loader will be 1952 appended to the default kernel command string. 1953 1954config CMDLINE_FORCE 1955 bool "Always use the default kernel command string" 1956 help 1957 Always use the default kernel command string, even if the boot 1958 loader passes other arguments to the kernel. 1959 This is useful if you cannot or don't want to change the 1960 command-line options your boot loader passes to the kernel. 1961endchoice 1962 1963config XIP_KERNEL 1964 bool "Kernel Execute-In-Place from ROM" 1965 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1966 help 1967 Execute-In-Place allows the kernel to run from non-volatile storage 1968 directly addressable by the CPU, such as NOR flash. This saves RAM 1969 space since the text section of the kernel is not loaded from flash 1970 to RAM. Read-write sections, such as the data section and stack, 1971 are still copied to RAM. The XIP kernel is not compressed since 1972 it has to run directly from flash, so it will take more space to 1973 store it. The flash address used to link the kernel object files, 1974 and for storing it, is configuration dependent. Therefore, if you 1975 say Y here, you must know the proper physical address where to 1976 store the kernel image depending on your own flash memory usage. 1977 1978 Also note that the make target becomes "make xipImage" rather than 1979 "make zImage" or "make Image". The final kernel binary to put in 1980 ROM memory will be arch/arm/boot/xipImage. 1981 1982 If unsure, say N. 1983 1984config XIP_PHYS_ADDR 1985 hex "XIP Kernel Physical Location" 1986 depends on XIP_KERNEL 1987 default "0x00080000" 1988 help 1989 This is the physical address in your flash memory the kernel will 1990 be linked for and stored to. This address is dependent on your 1991 own flash usage. 1992 1993config XIP_DEFLATED_DATA 1994 bool "Store kernel .data section compressed in ROM" 1995 depends on XIP_KERNEL 1996 select ZLIB_INFLATE 1997 help 1998 Before the kernel is actually executed, its .data section has to be 1999 copied to RAM from ROM. This option allows for storing that data 2000 in compressed form and decompressed to RAM rather than merely being 2001 copied, saving some precious ROM space. A possible drawback is a 2002 slightly longer boot delay. 2003 2004config KEXEC 2005 bool "Kexec system call (EXPERIMENTAL)" 2006 depends on (!SMP || PM_SLEEP_SMP) 2007 depends on !CPU_V7M 2008 select KEXEC_CORE 2009 help 2010 kexec is a system call that implements the ability to shutdown your 2011 current kernel, and to start another kernel. It is like a reboot 2012 but it is independent of the system firmware. And like a reboot 2013 you can start any kernel with it, not just Linux. 2014 2015 It is an ongoing process to be certain the hardware in a machine 2016 is properly shutdown, so do not be surprised if this code does not 2017 initially work for you. 2018 2019config ATAGS_PROC 2020 bool "Export atags in procfs" 2021 depends on ATAGS && KEXEC 2022 default y 2023 help 2024 Should the atags used to boot the kernel be exported in an "atags" 2025 file in procfs. Useful with kexec. 2026 2027config CRASH_DUMP 2028 bool "Build kdump crash kernel (EXPERIMENTAL)" 2029 help 2030 Generate crash dump after being started by kexec. This should 2031 be normally only set in special crash dump kernels which are 2032 loaded in the main kernel with kexec-tools into a specially 2033 reserved region and then later executed after a crash by 2034 kdump/kexec. The crash dump kernel must be compiled to a 2035 memory address not used by the main kernel 2036 2037 For more details see Documentation/kdump/kdump.txt 2038 2039config AUTO_ZRELADDR 2040 bool "Auto calculation of the decompressed kernel image address" 2041 help 2042 ZRELADDR is the physical address where the decompressed kernel 2043 image will be placed. If AUTO_ZRELADDR is selected, the address 2044 will be determined at run-time by masking the current IP with 2045 0xf8000000. This assumes the zImage being placed in the first 128MB 2046 from start of memory. 2047 2048config EFI_STUB 2049 bool 2050 2051config EFI 2052 bool "UEFI runtime support" 2053 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2054 select UCS2_STRING 2055 select EFI_PARAMS_FROM_FDT 2056 select EFI_STUB 2057 select EFI_ARMSTUB 2058 select EFI_RUNTIME_WRAPPERS 2059 ---help--- 2060 This option provides support for runtime services provided 2061 by UEFI firmware (such as non-volatile variables, realtime 2062 clock, and platform reset). A UEFI stub is also provided to 2063 allow the kernel to be booted as an EFI application. This 2064 is only useful for kernels that may run on systems that have 2065 UEFI firmware. 2066 2067config DMI 2068 bool "Enable support for SMBIOS (DMI) tables" 2069 depends on EFI 2070 default y 2071 help 2072 This enables SMBIOS/DMI feature for systems. 2073 2074 This option is only useful on systems that have UEFI firmware. 2075 However, even with this option, the resultant kernel should 2076 continue to boot on existing non-UEFI platforms. 2077 2078 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2079 i.e., the the practice of identifying the platform via DMI to 2080 decide whether certain workarounds for buggy hardware and/or 2081 firmware need to be enabled. This would require the DMI subsystem 2082 to be enabled much earlier than we do on ARM, which is non-trivial. 2083 2084endmenu 2085 2086menu "CPU Power Management" 2087 2088source "drivers/cpufreq/Kconfig" 2089 2090source "drivers/cpuidle/Kconfig" 2091 2092endmenu 2093 2094menu "Floating point emulation" 2095 2096comment "At least one emulation must be selected" 2097 2098config FPE_NWFPE 2099 bool "NWFPE math emulation" 2100 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2101 ---help--- 2102 Say Y to include the NWFPE floating point emulator in the kernel. 2103 This is necessary to run most binaries. Linux does not currently 2104 support floating point hardware so you need to say Y here even if 2105 your machine has an FPA or floating point co-processor podule. 2106 2107 You may say N here if you are going to load the Acorn FPEmulator 2108 early in the bootup. 2109 2110config FPE_NWFPE_XP 2111 bool "Support extended precision" 2112 depends on FPE_NWFPE 2113 help 2114 Say Y to include 80-bit support in the kernel floating-point 2115 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2116 Note that gcc does not generate 80-bit operations by default, 2117 so in most cases this option only enlarges the size of the 2118 floating point emulator without any good reason. 2119 2120 You almost surely want to say N here. 2121 2122config FPE_FASTFPE 2123 bool "FastFPE math emulation (EXPERIMENTAL)" 2124 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2125 ---help--- 2126 Say Y here to include the FAST floating point emulator in the kernel. 2127 This is an experimental much faster emulator which now also has full 2128 precision for the mantissa. It does not support any exceptions. 2129 It is very simple, and approximately 3-6 times faster than NWFPE. 2130 2131 It should be sufficient for most programs. It may be not suitable 2132 for scientific calculations, but you have to check this for yourself. 2133 If you do not feel you need a faster FP emulation you should better 2134 choose NWFPE. 2135 2136config VFP 2137 bool "VFP-format floating point maths" 2138 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2139 help 2140 Say Y to include VFP support code in the kernel. This is needed 2141 if your hardware includes a VFP unit. 2142 2143 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2144 release notes and additional status information. 2145 2146 Say N if your target does not have VFP hardware. 2147 2148config VFPv3 2149 bool 2150 depends on VFP 2151 default y if CPU_V7 2152 2153config NEON 2154 bool "Advanced SIMD (NEON) Extension support" 2155 depends on VFPv3 && CPU_V7 2156 help 2157 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2158 Extension. 2159 2160config KERNEL_MODE_NEON 2161 bool "Support for NEON in kernel mode" 2162 depends on NEON && AEABI 2163 help 2164 Say Y to include support for NEON in kernel mode. 2165 2166endmenu 2167 2168menu "Power management options" 2169 2170source "kernel/power/Kconfig" 2171 2172config ARCH_SUSPEND_POSSIBLE 2173 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2174 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2175 def_bool y 2176 2177config ARM_CPU_SUSPEND 2178 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2179 depends on ARCH_SUSPEND_POSSIBLE 2180 2181config ARCH_HIBERNATION_POSSIBLE 2182 bool 2183 depends on MMU 2184 default y if ARCH_SUSPEND_POSSIBLE 2185 2186endmenu 2187 2188source "drivers/firmware/Kconfig" 2189 2190if CRYPTO 2191source "arch/arm/crypto/Kconfig" 2192endif 2193 2194source "arch/arm/kvm/Kconfig" 2195