1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select HAVE_GENERIC_DMA_COHERENT 20 select HAVE_KERNEL_GZIP 21 select HAVE_KERNEL_LZO 22 select HAVE_KERNEL_LZMA 23 select HAVE_IRQ_WORK 24 select HAVE_PERF_EVENTS 25 select PERF_USE_VMALLOC 26 select HAVE_REGS_AND_STACK_ACCESS_API 27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 28 select HAVE_C_RECORDMCOUNT 29 select HAVE_GENERIC_HARDIRQS 30 select HAVE_SPARSE_IRQ 31 select GENERIC_IRQ_SHOW 32 help 33 The ARM series is a line of low-power-consumption RISC chip designs 34 licensed by ARM Ltd and targeted at embedded applications and 35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 36 manufactured, but legacy ARM-based PC hardware remains popular in 37 Europe. There is an ARM Linux project with a web page at 38 <http://www.arm.linux.org.uk/>. 39 40config HAVE_PWM 41 bool 42 43config MIGHT_HAVE_PCI 44 bool 45 46config SYS_SUPPORTS_APM_EMULATION 47 bool 48 49config HAVE_SCHED_CLOCK 50 bool 51 52config GENERIC_GPIO 53 bool 54 55config ARCH_USES_GETTIMEOFFSET 56 bool 57 default n 58 59config GENERIC_CLOCKEVENTS 60 bool 61 62config GENERIC_CLOCKEVENTS_BROADCAST 63 bool 64 depends on GENERIC_CLOCKEVENTS 65 default y if SMP 66 67config KTIME_SCALAR 68 bool 69 default y 70 71config HAVE_TCM 72 bool 73 select GENERIC_ALLOCATOR 74 75config HAVE_PROC_CPU 76 bool 77 78config NO_IOPORT 79 bool 80 81config EISA 82 bool 83 ---help--- 84 The Extended Industry Standard Architecture (EISA) bus was 85 developed as an open alternative to the IBM MicroChannel bus. 86 87 The EISA bus provided some of the features of the IBM MicroChannel 88 bus while maintaining backward compatibility with cards made for 89 the older ISA bus. The EISA bus saw limited use between 1988 and 90 1995 when it was made obsolete by the PCI bus. 91 92 Say Y here if you are building a kernel for an EISA-based machine. 93 94 Otherwise, say N. 95 96config SBUS 97 bool 98 99config MCA 100 bool 101 help 102 MicroChannel Architecture is found in some IBM PS/2 machines and 103 laptops. It is a bus system similar to PCI or ISA. See 104 <file:Documentation/mca.txt> (and especially the web page given 105 there) before attempting to build an MCA bus kernel. 106 107config STACKTRACE_SUPPORT 108 bool 109 default y 110 111config HAVE_LATENCYTOP_SUPPORT 112 bool 113 depends on !SMP 114 default y 115 116config LOCKDEP_SUPPORT 117 bool 118 default y 119 120config TRACE_IRQFLAGS_SUPPORT 121 bool 122 default y 123 124config HARDIRQS_SW_RESEND 125 bool 126 default y 127 128config GENERIC_IRQ_PROBE 129 bool 130 default y 131 132config GENERIC_LOCKBREAK 133 bool 134 default y 135 depends on SMP && PREEMPT 136 137config RWSEM_GENERIC_SPINLOCK 138 bool 139 default y 140 141config RWSEM_XCHGADD_ALGORITHM 142 bool 143 144config ARCH_HAS_ILOG2_U32 145 bool 146 147config ARCH_HAS_ILOG2_U64 148 bool 149 150config ARCH_HAS_CPUFREQ 151 bool 152 help 153 Internal node to signify that the ARCH has CPUFREQ support 154 and that the relevant menu configurations are displayed for 155 it. 156 157config ARCH_HAS_CPU_IDLE_WAIT 158 def_bool y 159 160config GENERIC_HWEIGHT 161 bool 162 default y 163 164config GENERIC_CALIBRATE_DELAY 165 bool 166 default y 167 168config ARCH_MAY_HAVE_PC_FDC 169 bool 170 171config ZONE_DMA 172 bool 173 174config NEED_DMA_MAP_STATE 175 def_bool y 176 177config GENERIC_ISA_DMA 178 bool 179 180config FIQ 181 bool 182 183config ARCH_MTD_XIP 184 bool 185 186config VECTORS_BASE 187 hex 188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 189 default DRAM_BASE if REMAP_VECTORS_TO_RAM 190 default 0x00000000 191 help 192 The base address of exception vectors. 193 194config ARM_PATCH_PHYS_VIRT 195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" 196 depends on EXPERIMENTAL 197 depends on !XIP_KERNEL && MMU 198 depends on !ARCH_REALVIEW || !SPARSEMEM 199 help 200 Patch phys-to-virt and virt-to-phys translation functions at 201 boot and module load time according to the position of the 202 kernel in system memory. 203 204 This can only be used with non-XIP MMU kernels where the base 205 of physical memory is at a 16MB boundary, or theoretically 64K 206 for the MSM machine class. 207 208config ARM_PATCH_PHYS_VIRT_16BIT 209 def_bool y 210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM 211 help 212 This option extends the physical to virtual translation patching 213 to allow physical memory down to a theoretical minimum of 64K 214 boundaries. 215 216source "init/Kconfig" 217 218source "kernel/Kconfig.freezer" 219 220menu "System Type" 221 222config MMU 223 bool "MMU-based Paged Memory Management Support" 224 default y 225 help 226 Select if you want MMU-based virtualised addressing space 227 support by paged memory management. If unsure, say 'Y'. 228 229# 230# The "ARM system type" choice list is ordered alphabetically by option 231# text. Please add new entries in the option alphabetic order. 232# 233choice 234 prompt "ARM system type" 235 default ARCH_VERSATILE 236 237config ARCH_INTEGRATOR 238 bool "ARM Ltd. Integrator family" 239 select ARM_AMBA 240 select ARCH_HAS_CPUFREQ 241 select CLKDEV_LOOKUP 242 select ICST 243 select GENERIC_CLOCKEVENTS 244 select PLAT_VERSATILE 245 select PLAT_VERSATILE_FPGA_IRQ 246 help 247 Support for ARM's Integrator platform. 248 249config ARCH_REALVIEW 250 bool "ARM Ltd. RealView family" 251 select ARM_AMBA 252 select CLKDEV_LOOKUP 253 select ICST 254 select GENERIC_CLOCKEVENTS 255 select ARCH_WANT_OPTIONAL_GPIOLIB 256 select PLAT_VERSATILE 257 select PLAT_VERSATILE_CLCD 258 select ARM_TIMER_SP804 259 select GPIO_PL061 if GPIOLIB 260 help 261 This enables support for ARM Ltd RealView boards. 262 263config ARCH_VERSATILE 264 bool "ARM Ltd. Versatile family" 265 select ARM_AMBA 266 select ARM_VIC 267 select CLKDEV_LOOKUP 268 select ICST 269 select GENERIC_CLOCKEVENTS 270 select ARCH_WANT_OPTIONAL_GPIOLIB 271 select PLAT_VERSATILE 272 select PLAT_VERSATILE_CLCD 273 select PLAT_VERSATILE_FPGA_IRQ 274 select ARM_TIMER_SP804 275 help 276 This enables support for ARM Ltd Versatile board. 277 278config ARCH_VEXPRESS 279 bool "ARM Ltd. Versatile Express family" 280 select ARCH_WANT_OPTIONAL_GPIOLIB 281 select ARM_AMBA 282 select ARM_TIMER_SP804 283 select CLKDEV_LOOKUP 284 select GENERIC_CLOCKEVENTS 285 select HAVE_CLK 286 select HAVE_PATA_PLATFORM 287 select ICST 288 select PLAT_VERSATILE 289 select PLAT_VERSATILE_CLCD 290 help 291 This enables support for the ARM Ltd Versatile Express boards. 292 293config ARCH_AT91 294 bool "Atmel AT91" 295 select ARCH_REQUIRE_GPIOLIB 296 select HAVE_CLK 297 select CLKDEV_LOOKUP 298 select ARM_PATCH_PHYS_VIRT if MMU 299 help 300 This enables support for systems based on the Atmel AT91RM9200, 301 AT91SAM9 and AT91CAP9 processors. 302 303config ARCH_BCMRING 304 bool "Broadcom BCMRING" 305 depends on MMU 306 select CPU_V6 307 select ARM_AMBA 308 select ARM_TIMER_SP804 309 select CLKDEV_LOOKUP 310 select GENERIC_CLOCKEVENTS 311 select ARCH_WANT_OPTIONAL_GPIOLIB 312 help 313 Support for Broadcom's BCMRing platform. 314 315config ARCH_CLPS711X 316 bool "Cirrus Logic CLPS711x/EP721x-based" 317 select CPU_ARM720T 318 select ARCH_USES_GETTIMEOFFSET 319 help 320 Support for Cirrus Logic 711x/721x based boards. 321 322config ARCH_CNS3XXX 323 bool "Cavium Networks CNS3XXX family" 324 select CPU_V6 325 select GENERIC_CLOCKEVENTS 326 select ARM_GIC 327 select MIGHT_HAVE_PCI 328 select PCI_DOMAINS if PCI 329 help 330 Support for Cavium Networks CNS3XXX platform. 331 332config ARCH_GEMINI 333 bool "Cortina Systems Gemini" 334 select CPU_FA526 335 select ARCH_REQUIRE_GPIOLIB 336 select ARCH_USES_GETTIMEOFFSET 337 help 338 Support for the Cortina Systems Gemini family SoCs 339 340config ARCH_EBSA110 341 bool "EBSA-110" 342 select CPU_SA110 343 select ISA 344 select NO_IOPORT 345 select ARCH_USES_GETTIMEOFFSET 346 help 347 This is an evaluation board for the StrongARM processor available 348 from Digital. It has limited hardware on-board, including an 349 Ethernet interface, two PCMCIA sockets, two serial ports and a 350 parallel port. 351 352config ARCH_EP93XX 353 bool "EP93xx-based" 354 select CPU_ARM920T 355 select ARM_AMBA 356 select ARM_VIC 357 select CLKDEV_LOOKUP 358 select ARCH_REQUIRE_GPIOLIB 359 select ARCH_HAS_HOLES_MEMORYMODEL 360 select ARCH_USES_GETTIMEOFFSET 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select GENERIC_CLOCKEVENTS 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_MXC 374 bool "Freescale MXC/iMX-based" 375 select GENERIC_CLOCKEVENTS 376 select ARCH_REQUIRE_GPIOLIB 377 select CLKDEV_LOOKUP 378 select CLKSRC_MMIO 379 select HAVE_SCHED_CLOCK 380 help 381 Support for Freescale MXC/iMX-based family of processors 382 383config ARCH_MXS 384 bool "Freescale MXS-based" 385 select GENERIC_CLOCKEVENTS 386 select ARCH_REQUIRE_GPIOLIB 387 select CLKDEV_LOOKUP 388 select CLKSRC_MMIO 389 help 390 Support for Freescale MXS-based family of processors 391 392config ARCH_NETX 393 bool "Hilscher NetX based" 394 select CLKSRC_MMIO 395 select CPU_ARM926T 396 select ARM_VIC 397 select GENERIC_CLOCKEVENTS 398 help 399 This enables support for systems based on the Hilscher NetX Soc 400 401config ARCH_H720X 402 bool "Hynix HMS720x-based" 403 select CPU_ARM720T 404 select ISA_DMA_API 405 select ARCH_USES_GETTIMEOFFSET 406 help 407 This enables support for systems based on the Hynix HMS720x 408 409config ARCH_IOP13XX 410 bool "IOP13xx-based" 411 depends on MMU 412 select CPU_XSC3 413 select PLAT_IOP 414 select PCI 415 select ARCH_SUPPORTS_MSI 416 select VMSPLIT_1G 417 help 418 Support for Intel's IOP13XX (XScale) family of processors. 419 420config ARCH_IOP32X 421 bool "IOP32x-based" 422 depends on MMU 423 select CPU_XSCALE 424 select PLAT_IOP 425 select PCI 426 select ARCH_REQUIRE_GPIOLIB 427 help 428 Support for Intel's 80219 and IOP32X (XScale) family of 429 processors. 430 431config ARCH_IOP33X 432 bool "IOP33x-based" 433 depends on MMU 434 select CPU_XSCALE 435 select PLAT_IOP 436 select PCI 437 select ARCH_REQUIRE_GPIOLIB 438 help 439 Support for Intel's IOP33X (XScale) family of processors. 440 441config ARCH_IXP23XX 442 bool "IXP23XX-based" 443 depends on MMU 444 select CPU_XSC3 445 select PCI 446 select ARCH_USES_GETTIMEOFFSET 447 help 448 Support for Intel's IXP23xx (XScale) family of processors. 449 450config ARCH_IXP2000 451 bool "IXP2400/2800-based" 452 depends on MMU 453 select CPU_XSCALE 454 select PCI 455 select ARCH_USES_GETTIMEOFFSET 456 help 457 Support for Intel's IXP2400/2800 (XScale) family of processors. 458 459config ARCH_IXP4XX 460 bool "IXP4xx-based" 461 depends on MMU 462 select CLKSRC_MMIO 463 select CPU_XSCALE 464 select GENERIC_GPIO 465 select GENERIC_CLOCKEVENTS 466 select HAVE_SCHED_CLOCK 467 select MIGHT_HAVE_PCI 468 select DMABOUNCE if PCI 469 help 470 Support for Intel's IXP4XX (XScale) family of processors. 471 472config ARCH_DOVE 473 bool "Marvell Dove" 474 select CPU_V7 475 select PCI 476 select ARCH_REQUIRE_GPIOLIB 477 select GENERIC_CLOCKEVENTS 478 select PLAT_ORION 479 help 480 Support for the Marvell Dove SoC 88AP510 481 482config ARCH_KIRKWOOD 483 bool "Marvell Kirkwood" 484 select CPU_FEROCEON 485 select PCI 486 select ARCH_REQUIRE_GPIOLIB 487 select GENERIC_CLOCKEVENTS 488 select PLAT_ORION 489 help 490 Support for the following Marvell Kirkwood series SoCs: 491 88F6180, 88F6192 and 88F6281. 492 493config ARCH_LOKI 494 bool "Marvell Loki (88RC8480)" 495 select CPU_FEROCEON 496 select GENERIC_CLOCKEVENTS 497 select PLAT_ORION 498 help 499 Support for the Marvell Loki (88RC8480) SoC. 500 501config ARCH_LPC32XX 502 bool "NXP LPC32XX" 503 select CLKSRC_MMIO 504 select CPU_ARM926T 505 select ARCH_REQUIRE_GPIOLIB 506 select HAVE_IDE 507 select ARM_AMBA 508 select USB_ARCH_HAS_OHCI 509 select CLKDEV_LOOKUP 510 select GENERIC_TIME 511 select GENERIC_CLOCKEVENTS 512 help 513 Support for the NXP LPC32XX family of processors 514 515config ARCH_MV78XX0 516 bool "Marvell MV78xx0" 517 select CPU_FEROCEON 518 select PCI 519 select ARCH_REQUIRE_GPIOLIB 520 select GENERIC_CLOCKEVENTS 521 select PLAT_ORION 522 help 523 Support for the following Marvell MV78xx0 series SoCs: 524 MV781x0, MV782x0. 525 526config ARCH_ORION5X 527 bool "Marvell Orion" 528 depends on MMU 529 select CPU_FEROCEON 530 select PCI 531 select ARCH_REQUIRE_GPIOLIB 532 select GENERIC_CLOCKEVENTS 533 select PLAT_ORION 534 help 535 Support for the following Marvell Orion 5x series SoCs: 536 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 537 Orion-2 (5281), Orion-1-90 (6183). 538 539config ARCH_MMP 540 bool "Marvell PXA168/910/MMP2" 541 depends on MMU 542 select ARCH_REQUIRE_GPIOLIB 543 select CLKDEV_LOOKUP 544 select GENERIC_CLOCKEVENTS 545 select HAVE_SCHED_CLOCK 546 select TICK_ONESHOT 547 select PLAT_PXA 548 select SPARSE_IRQ 549 help 550 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 551 552config ARCH_KS8695 553 bool "Micrel/Kendin KS8695" 554 select CPU_ARM922T 555 select ARCH_REQUIRE_GPIOLIB 556 select ARCH_USES_GETTIMEOFFSET 557 help 558 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 559 System-on-Chip devices. 560 561config ARCH_W90X900 562 bool "Nuvoton W90X900 CPU" 563 select CPU_ARM926T 564 select ARCH_REQUIRE_GPIOLIB 565 select CLKDEV_LOOKUP 566 select CLKSRC_MMIO 567 select GENERIC_CLOCKEVENTS 568 help 569 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 570 At present, the w90x900 has been renamed nuc900, regarding 571 the ARM series product line, you can login the following 572 link address to know more. 573 574 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 575 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 576 577config ARCH_NUC93X 578 bool "Nuvoton NUC93X CPU" 579 select CPU_ARM926T 580 select CLKDEV_LOOKUP 581 help 582 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a 583 low-power and high performance MPEG-4/JPEG multimedia controller chip. 584 585config ARCH_TEGRA 586 bool "NVIDIA Tegra" 587 select CLKDEV_LOOKUP 588 select CLKSRC_MMIO 589 select GENERIC_TIME 590 select GENERIC_CLOCKEVENTS 591 select GENERIC_GPIO 592 select HAVE_CLK 593 select HAVE_SCHED_CLOCK 594 select ARCH_HAS_BARRIERS if CACHE_L2X0 595 select ARCH_HAS_CPUFREQ 596 help 597 This enables support for NVIDIA Tegra based systems (Tegra APX, 598 Tegra 6xx and Tegra 2 series). 599 600config ARCH_PNX4008 601 bool "Philips Nexperia PNX4008 Mobile" 602 select CPU_ARM926T 603 select CLKDEV_LOOKUP 604 select ARCH_USES_GETTIMEOFFSET 605 help 606 This enables support for Philips PNX4008 mobile platform. 607 608config ARCH_PXA 609 bool "PXA2xx/PXA3xx-based" 610 depends on MMU 611 select ARCH_MTD_XIP 612 select ARCH_HAS_CPUFREQ 613 select CLKDEV_LOOKUP 614 select CLKSRC_MMIO 615 select ARCH_REQUIRE_GPIOLIB 616 select GENERIC_CLOCKEVENTS 617 select HAVE_SCHED_CLOCK 618 select TICK_ONESHOT 619 select PLAT_PXA 620 select SPARSE_IRQ 621 help 622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 623 624config ARCH_MSM 625 bool "Qualcomm MSM" 626 select HAVE_CLK 627 select GENERIC_CLOCKEVENTS 628 select ARCH_REQUIRE_GPIOLIB 629 select CLKDEV_LOOKUP 630 help 631 Support for Qualcomm MSM/QSD based systems. This runs on the 632 apps processor of the MSM/QSD and depends on a shared memory 633 interface to the modem processor which runs the baseband 634 stack and controls some vital subsystems 635 (clock and power control, etc). 636 637config ARCH_SHMOBILE 638 bool "Renesas SH-Mobile / R-Mobile" 639 select HAVE_CLK 640 select CLKDEV_LOOKUP 641 select GENERIC_CLOCKEVENTS 642 select NO_IOPORT 643 select SPARSE_IRQ 644 select MULTI_IRQ_HANDLER 645 select PM_GENERIC_DOMAINS if PM 646 help 647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 648 649config ARCH_RPC 650 bool "RiscPC" 651 select ARCH_ACORN 652 select FIQ 653 select TIMER_ACORN 654 select ARCH_MAY_HAVE_PC_FDC 655 select HAVE_PATA_PLATFORM 656 select ISA_DMA_API 657 select NO_IOPORT 658 select ARCH_SPARSEMEM_ENABLE 659 select ARCH_USES_GETTIMEOFFSET 660 help 661 On the Acorn Risc-PC, Linux can support the internal IDE disk and 662 CD-ROM interface, serial and parallel port, and the floppy drive. 663 664config ARCH_SA1100 665 bool "SA1100-based" 666 select CLKSRC_MMIO 667 select CPU_SA1100 668 select ISA 669 select ARCH_SPARSEMEM_ENABLE 670 select ARCH_MTD_XIP 671 select ARCH_HAS_CPUFREQ 672 select CPU_FREQ 673 select GENERIC_CLOCKEVENTS 674 select HAVE_CLK 675 select HAVE_SCHED_CLOCK 676 select TICK_ONESHOT 677 select ARCH_REQUIRE_GPIOLIB 678 help 679 Support for StrongARM 11x0 based boards. 680 681config ARCH_S3C2410 682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 683 select GENERIC_GPIO 684 select ARCH_HAS_CPUFREQ 685 select HAVE_CLK 686 select ARCH_USES_GETTIMEOFFSET 687 select HAVE_S3C2410_I2C if I2C 688 help 689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 691 the Samsung SMDK2410 development board (and derivatives). 692 693 Note, the S3C2416 and the S3C2450 are so close that they even share 694 the same SoC ID code. This means that there is no separate machine 695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 696 697config ARCH_S3C64XX 698 bool "Samsung S3C64XX" 699 select PLAT_SAMSUNG 700 select CPU_V6 701 select ARM_VIC 702 select HAVE_CLK 703 select NO_IOPORT 704 select ARCH_USES_GETTIMEOFFSET 705 select ARCH_HAS_CPUFREQ 706 select ARCH_REQUIRE_GPIOLIB 707 select SAMSUNG_CLKSRC 708 select SAMSUNG_IRQ_VIC_TIMER 709 select SAMSUNG_IRQ_UART 710 select S3C_GPIO_TRACK 711 select S3C_GPIO_PULL_UPDOWN 712 select S3C_GPIO_CFG_S3C24XX 713 select S3C_GPIO_CFG_S3C64XX 714 select S3C_DEV_NAND 715 select USB_ARCH_HAS_OHCI 716 select SAMSUNG_GPIOLIB_4BIT 717 select HAVE_S3C2410_I2C if I2C 718 select HAVE_S3C2410_WATCHDOG if WATCHDOG 719 help 720 Samsung S3C64XX series based systems 721 722config ARCH_S5P64X0 723 bool "Samsung S5P6440 S5P6450" 724 select CPU_V6 725 select GENERIC_GPIO 726 select HAVE_CLK 727 select HAVE_S3C2410_WATCHDOG if WATCHDOG 728 select GENERIC_CLOCKEVENTS 729 select HAVE_SCHED_CLOCK 730 select HAVE_S3C2410_I2C if I2C 731 select HAVE_S3C_RTC if RTC_CLASS 732 help 733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 734 SMDK6450. 735 736config ARCH_S5PC100 737 bool "Samsung S5PC100" 738 select GENERIC_GPIO 739 select HAVE_CLK 740 select CPU_V7 741 select ARM_L1_CACHE_SHIFT_6 742 select ARCH_USES_GETTIMEOFFSET 743 select HAVE_S3C2410_I2C if I2C 744 select HAVE_S3C_RTC if RTC_CLASS 745 select HAVE_S3C2410_WATCHDOG if WATCHDOG 746 help 747 Samsung S5PC100 series based systems 748 749config ARCH_S5PV210 750 bool "Samsung S5PV210/S5PC110" 751 select CPU_V7 752 select ARCH_SPARSEMEM_ENABLE 753 select GENERIC_GPIO 754 select HAVE_CLK 755 select ARM_L1_CACHE_SHIFT_6 756 select ARCH_HAS_CPUFREQ 757 select GENERIC_CLOCKEVENTS 758 select HAVE_SCHED_CLOCK 759 select HAVE_S3C2410_I2C if I2C 760 select HAVE_S3C_RTC if RTC_CLASS 761 select HAVE_S3C2410_WATCHDOG if WATCHDOG 762 help 763 Samsung S5PV210/S5PC110 series based systems 764 765config ARCH_EXYNOS4 766 bool "Samsung EXYNOS4" 767 select CPU_V7 768 select ARCH_SPARSEMEM_ENABLE 769 select GENERIC_GPIO 770 select HAVE_CLK 771 select ARCH_HAS_CPUFREQ 772 select GENERIC_CLOCKEVENTS 773 select HAVE_S3C_RTC if RTC_CLASS 774 select HAVE_S3C2410_I2C if I2C 775 select HAVE_S3C2410_WATCHDOG if WATCHDOG 776 help 777 Samsung EXYNOS4 series based systems 778 779config ARCH_SHARK 780 bool "Shark" 781 select CPU_SA110 782 select ISA 783 select ISA_DMA 784 select ZONE_DMA 785 select PCI 786 select ARCH_USES_GETTIMEOFFSET 787 help 788 Support for the StrongARM based Digital DNARD machine, also known 789 as "Shark" (<http://www.shark-linux.de/shark.html>). 790 791config ARCH_TCC_926 792 bool "Telechips TCC ARM926-based systems" 793 select CLKSRC_MMIO 794 select CPU_ARM926T 795 select HAVE_CLK 796 select CLKDEV_LOOKUP 797 select GENERIC_CLOCKEVENTS 798 help 799 Support for Telechips TCC ARM926-based systems. 800 801config ARCH_U300 802 bool "ST-Ericsson U300 Series" 803 depends on MMU 804 select CLKSRC_MMIO 805 select CPU_ARM926T 806 select HAVE_SCHED_CLOCK 807 select HAVE_TCM 808 select ARM_AMBA 809 select ARM_VIC 810 select GENERIC_CLOCKEVENTS 811 select CLKDEV_LOOKUP 812 select GENERIC_GPIO 813 help 814 Support for ST-Ericsson U300 series mobile platforms. 815 816config ARCH_U8500 817 bool "ST-Ericsson U8500 Series" 818 select CPU_V7 819 select ARM_AMBA 820 select GENERIC_CLOCKEVENTS 821 select CLKDEV_LOOKUP 822 select ARCH_REQUIRE_GPIOLIB 823 select ARCH_HAS_CPUFREQ 824 help 825 Support for ST-Ericsson's Ux500 architecture 826 827config ARCH_NOMADIK 828 bool "STMicroelectronics Nomadik" 829 select ARM_AMBA 830 select ARM_VIC 831 select CPU_ARM926T 832 select CLKDEV_LOOKUP 833 select GENERIC_CLOCKEVENTS 834 select ARCH_REQUIRE_GPIOLIB 835 help 836 Support for the Nomadik platform by ST-Ericsson 837 838config ARCH_DAVINCI 839 bool "TI DaVinci" 840 select GENERIC_CLOCKEVENTS 841 select ARCH_REQUIRE_GPIOLIB 842 select ZONE_DMA 843 select HAVE_IDE 844 select CLKDEV_LOOKUP 845 select GENERIC_ALLOCATOR 846 select GENERIC_IRQ_CHIP 847 select ARCH_HAS_HOLES_MEMORYMODEL 848 help 849 Support for TI's DaVinci platform. 850 851config ARCH_OMAP 852 bool "TI OMAP" 853 select HAVE_CLK 854 select ARCH_REQUIRE_GPIOLIB 855 select ARCH_HAS_CPUFREQ 856 select GENERIC_CLOCKEVENTS 857 select HAVE_SCHED_CLOCK 858 select ARCH_HAS_HOLES_MEMORYMODEL 859 help 860 Support for TI's OMAP platform (OMAP1/2/3/4). 861 862config PLAT_SPEAR 863 bool "ST SPEAr" 864 select ARM_AMBA 865 select ARCH_REQUIRE_GPIOLIB 866 select CLKDEV_LOOKUP 867 select CLKSRC_MMIO 868 select GENERIC_CLOCKEVENTS 869 select HAVE_CLK 870 help 871 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 872 873config ARCH_VT8500 874 bool "VIA/WonderMedia 85xx" 875 select CPU_ARM926T 876 select GENERIC_GPIO 877 select ARCH_HAS_CPUFREQ 878 select GENERIC_CLOCKEVENTS 879 select ARCH_REQUIRE_GPIOLIB 880 select HAVE_PWM 881 help 882 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 883endchoice 884 885# 886# This is sorted alphabetically by mach-* pathname. However, plat-* 887# Kconfigs may be included either alphabetically (according to the 888# plat- suffix) or along side the corresponding mach-* source. 889# 890source "arch/arm/mach-at91/Kconfig" 891 892source "arch/arm/mach-bcmring/Kconfig" 893 894source "arch/arm/mach-clps711x/Kconfig" 895 896source "arch/arm/mach-cns3xxx/Kconfig" 897 898source "arch/arm/mach-davinci/Kconfig" 899 900source "arch/arm/mach-dove/Kconfig" 901 902source "arch/arm/mach-ep93xx/Kconfig" 903 904source "arch/arm/mach-footbridge/Kconfig" 905 906source "arch/arm/mach-gemini/Kconfig" 907 908source "arch/arm/mach-h720x/Kconfig" 909 910source "arch/arm/mach-integrator/Kconfig" 911 912source "arch/arm/mach-iop32x/Kconfig" 913 914source "arch/arm/mach-iop33x/Kconfig" 915 916source "arch/arm/mach-iop13xx/Kconfig" 917 918source "arch/arm/mach-ixp4xx/Kconfig" 919 920source "arch/arm/mach-ixp2000/Kconfig" 921 922source "arch/arm/mach-ixp23xx/Kconfig" 923 924source "arch/arm/mach-kirkwood/Kconfig" 925 926source "arch/arm/mach-ks8695/Kconfig" 927 928source "arch/arm/mach-loki/Kconfig" 929 930source "arch/arm/mach-lpc32xx/Kconfig" 931 932source "arch/arm/mach-msm/Kconfig" 933 934source "arch/arm/mach-mv78xx0/Kconfig" 935 936source "arch/arm/plat-mxc/Kconfig" 937 938source "arch/arm/mach-mxs/Kconfig" 939 940source "arch/arm/mach-netx/Kconfig" 941 942source "arch/arm/mach-nomadik/Kconfig" 943source "arch/arm/plat-nomadik/Kconfig" 944 945source "arch/arm/mach-nuc93x/Kconfig" 946 947source "arch/arm/plat-omap/Kconfig" 948 949source "arch/arm/mach-omap1/Kconfig" 950 951source "arch/arm/mach-omap2/Kconfig" 952 953source "arch/arm/mach-orion5x/Kconfig" 954 955source "arch/arm/mach-pxa/Kconfig" 956source "arch/arm/plat-pxa/Kconfig" 957 958source "arch/arm/mach-mmp/Kconfig" 959 960source "arch/arm/mach-realview/Kconfig" 961 962source "arch/arm/mach-sa1100/Kconfig" 963 964source "arch/arm/plat-samsung/Kconfig" 965source "arch/arm/plat-s3c24xx/Kconfig" 966source "arch/arm/plat-s5p/Kconfig" 967 968source "arch/arm/plat-spear/Kconfig" 969 970source "arch/arm/plat-tcc/Kconfig" 971 972if ARCH_S3C2410 973source "arch/arm/mach-s3c2400/Kconfig" 974source "arch/arm/mach-s3c2410/Kconfig" 975source "arch/arm/mach-s3c2412/Kconfig" 976source "arch/arm/mach-s3c2416/Kconfig" 977source "arch/arm/mach-s3c2440/Kconfig" 978source "arch/arm/mach-s3c2443/Kconfig" 979endif 980 981if ARCH_S3C64XX 982source "arch/arm/mach-s3c64xx/Kconfig" 983endif 984 985source "arch/arm/mach-s5p64x0/Kconfig" 986 987source "arch/arm/mach-s5pc100/Kconfig" 988 989source "arch/arm/mach-s5pv210/Kconfig" 990 991source "arch/arm/mach-exynos4/Kconfig" 992 993source "arch/arm/mach-shmobile/Kconfig" 994 995source "arch/arm/mach-tegra/Kconfig" 996 997source "arch/arm/mach-u300/Kconfig" 998 999source "arch/arm/mach-ux500/Kconfig" 1000 1001source "arch/arm/mach-versatile/Kconfig" 1002 1003source "arch/arm/mach-vexpress/Kconfig" 1004source "arch/arm/plat-versatile/Kconfig" 1005 1006source "arch/arm/mach-vt8500/Kconfig" 1007 1008source "arch/arm/mach-w90x900/Kconfig" 1009 1010# Definitions to make life easier 1011config ARCH_ACORN 1012 bool 1013 1014config PLAT_IOP 1015 bool 1016 select GENERIC_CLOCKEVENTS 1017 select HAVE_SCHED_CLOCK 1018 1019config PLAT_ORION 1020 bool 1021 select CLKSRC_MMIO 1022 select GENERIC_IRQ_CHIP 1023 select HAVE_SCHED_CLOCK 1024 1025config PLAT_PXA 1026 bool 1027 1028config PLAT_VERSATILE 1029 bool 1030 1031config ARM_TIMER_SP804 1032 bool 1033 select CLKSRC_MMIO 1034 1035source arch/arm/mm/Kconfig 1036 1037config IWMMXT 1038 bool "Enable iWMMXt support" 1039 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1040 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1041 help 1042 Enable support for iWMMXt context switching at run time if 1043 running on a CPU that supports it. 1044 1045# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 1046config XSCALE_PMU 1047 bool 1048 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 1049 default y 1050 1051config CPU_HAS_PMU 1052 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1053 (!ARCH_OMAP3 || OMAP3_EMU) 1054 default y 1055 bool 1056 1057config MULTI_IRQ_HANDLER 1058 bool 1059 help 1060 Allow each machine to specify it's own IRQ handler at run time. 1061 1062if !MMU 1063source "arch/arm/Kconfig-nommu" 1064endif 1065 1066config ARM_ERRATA_411920 1067 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1068 depends on CPU_V6 || CPU_V6K 1069 help 1070 Invalidation of the Instruction Cache operation can 1071 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1072 It does not affect the MPCore. This option enables the ARM Ltd. 1073 recommended workaround. 1074 1075config ARM_ERRATA_430973 1076 bool "ARM errata: Stale prediction on replaced interworking branch" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for the 430973 Cortex-A8 1080 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1081 interworking branch is replaced with another code sequence at the 1082 same virtual address, whether due to self-modifying code or virtual 1083 to physical address re-mapping, Cortex-A8 does not recover from the 1084 stale interworking branch prediction. This results in Cortex-A8 1085 executing the new code sequence in the incorrect ARM or Thumb state. 1086 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1087 and also flushes the branch target cache at every context switch. 1088 Note that setting specific bits in the ACTLR register may not be 1089 available in non-secure mode. 1090 1091config ARM_ERRATA_458693 1092 bool "ARM errata: Processor deadlock when a false hazard is created" 1093 depends on CPU_V7 1094 help 1095 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1096 erratum. For very specific sequences of memory operations, it is 1097 possible for a hazard condition intended for a cache line to instead 1098 be incorrectly associated with a different cache line. This false 1099 hazard might then cause a processor deadlock. The workaround enables 1100 the L1 caching of the NEON accesses and disables the PLD instruction 1101 in the ACTLR register. Note that setting specific bits in the ACTLR 1102 register may not be available in non-secure mode. 1103 1104config ARM_ERRATA_460075 1105 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1106 depends on CPU_V7 1107 help 1108 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1109 erratum. Any asynchronous access to the L2 cache may encounter a 1110 situation in which recent store transactions to the L2 cache are lost 1111 and overwritten with stale memory contents from external memory. The 1112 workaround disables the write-allocate mode for the L2 cache via the 1113 ACTLR register. Note that setting specific bits in the ACTLR register 1114 may not be available in non-secure mode. 1115 1116config ARM_ERRATA_742230 1117 bool "ARM errata: DMB operation may be faulty" 1118 depends on CPU_V7 && SMP 1119 help 1120 This option enables the workaround for the 742230 Cortex-A9 1121 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1122 between two write operations may not ensure the correct visibility 1123 ordering of the two writes. This workaround sets a specific bit in 1124 the diagnostic register of the Cortex-A9 which causes the DMB 1125 instruction to behave as a DSB, ensuring the correct behaviour of 1126 the two writes. 1127 1128config ARM_ERRATA_742231 1129 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1130 depends on CPU_V7 && SMP 1131 help 1132 This option enables the workaround for the 742231 Cortex-A9 1133 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1134 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1135 accessing some data located in the same cache line, may get corrupted 1136 data due to bad handling of the address hazard when the line gets 1137 replaced from one of the CPUs at the same time as another CPU is 1138 accessing it. This workaround sets specific bits in the diagnostic 1139 register of the Cortex-A9 which reduces the linefill issuing 1140 capabilities of the processor. 1141 1142config PL310_ERRATA_588369 1143 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1144 depends on CACHE_L2X0 1145 help 1146 The PL310 L2 cache controller implements three types of Clean & 1147 Invalidate maintenance operations: by Physical Address 1148 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1149 They are architecturally defined to behave as the execution of a 1150 clean operation followed immediately by an invalidate operation, 1151 both performing to the same memory location. This functionality 1152 is not correctly implemented in PL310 as clean lines are not 1153 invalidated as a result of these operations. 1154 1155config ARM_ERRATA_720789 1156 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1157 depends on CPU_V7 && SMP 1158 help 1159 This option enables the workaround for the 720789 Cortex-A9 (prior to 1160 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1161 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1162 As a consequence of this erratum, some TLB entries which should be 1163 invalidated are not, resulting in an incoherency in the system page 1164 tables. The workaround changes the TLB flushing routines to invalidate 1165 entries regardless of the ASID. 1166 1167config PL310_ERRATA_727915 1168 bool "Background Clean & Invalidate by Way operation can cause data corruption" 1169 depends on CACHE_L2X0 1170 help 1171 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1172 operation (offset 0x7FC). This operation runs in background so that 1173 PL310 can handle normal accesses while it is in progress. Under very 1174 rare circumstances, due to this erratum, write data can be lost when 1175 PL310 treats a cacheable write transaction during a Clean & 1176 Invalidate by Way operation. 1177 1178config ARM_ERRATA_743622 1179 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1180 depends on CPU_V7 1181 help 1182 This option enables the workaround for the 743622 Cortex-A9 1183 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1184 optimisation in the Cortex-A9 Store Buffer may lead to data 1185 corruption. This workaround sets a specific bit in the diagnostic 1186 register of the Cortex-A9 which disables the Store Buffer 1187 optimisation, preventing the defect from occurring. This has no 1188 visible impact on the overall performance or power consumption of the 1189 processor. 1190 1191config ARM_ERRATA_751472 1192 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1193 depends on CPU_V7 && SMP 1194 help 1195 This option enables the workaround for the 751472 Cortex-A9 (prior 1196 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1197 completion of a following broadcasted operation if the second 1198 operation is received by a CPU before the ICIALLUIS has completed, 1199 potentially leading to corrupted entries in the cache or TLB. 1200 1201config ARM_ERRATA_753970 1202 bool "ARM errata: cache sync operation may be faulty" 1203 depends on CACHE_PL310 1204 help 1205 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1206 1207 Under some condition the effect of cache sync operation on 1208 the store buffer still remains when the operation completes. 1209 This means that the store buffer is always asked to drain and 1210 this prevents it from merging any further writes. The workaround 1211 is to replace the normal offset of cache sync operation (0x730) 1212 by another offset targeting an unmapped PL310 register 0x740. 1213 This has the same effect as the cache sync operation: store buffer 1214 drain and waiting for all buffers empty. 1215 1216config ARM_ERRATA_754322 1217 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1218 depends on CPU_V7 1219 help 1220 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1221 r3p*) erratum. A speculative memory access may cause a page table walk 1222 which starts prior to an ASID switch but completes afterwards. This 1223 can populate the micro-TLB with a stale entry which may be hit with 1224 the new ASID. This workaround places two dsb instructions in the mm 1225 switching code so that no page table walks can cross the ASID switch. 1226 1227config ARM_ERRATA_754327 1228 bool "ARM errata: no automatic Store Buffer drain" 1229 depends on CPU_V7 && SMP 1230 help 1231 This option enables the workaround for the 754327 Cortex-A9 (prior to 1232 r2p0) erratum. The Store Buffer does not have any automatic draining 1233 mechanism and therefore a livelock may occur if an external agent 1234 continuously polls a memory location waiting to observe an update. 1235 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1236 written polling loops from denying visibility of updates to memory. 1237 1238endmenu 1239 1240source "arch/arm/common/Kconfig" 1241 1242menu "Bus support" 1243 1244config ARM_AMBA 1245 bool 1246 1247config ISA 1248 bool 1249 help 1250 Find out whether you have ISA slots on your motherboard. ISA is the 1251 name of a bus system, i.e. the way the CPU talks to the other stuff 1252 inside your box. Other bus systems are PCI, EISA, MicroChannel 1253 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1254 newer boards don't support it. If you have ISA, say Y, otherwise N. 1255 1256# Select ISA DMA controller support 1257config ISA_DMA 1258 bool 1259 select ISA_DMA_API 1260 1261# Select ISA DMA interface 1262config ISA_DMA_API 1263 bool 1264 1265config PCI 1266 bool "PCI support" if MIGHT_HAVE_PCI 1267 help 1268 Find out whether you have a PCI motherboard. PCI is the name of a 1269 bus system, i.e. the way the CPU talks to the other stuff inside 1270 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1271 VESA. If you have PCI, say Y, otherwise N. 1272 1273config PCI_DOMAINS 1274 bool 1275 depends on PCI 1276 1277config PCI_NANOENGINE 1278 bool "BSE nanoEngine PCI support" 1279 depends on SA1100_NANOENGINE 1280 help 1281 Enable PCI on the BSE nanoEngine board. 1282 1283config PCI_SYSCALL 1284 def_bool PCI 1285 1286# Select the host bridge type 1287config PCI_HOST_VIA82C505 1288 bool 1289 depends on PCI && ARCH_SHARK 1290 default y 1291 1292config PCI_HOST_ITE8152 1293 bool 1294 depends on PCI && MACH_ARMCORE 1295 default y 1296 select DMABOUNCE 1297 1298source "drivers/pci/Kconfig" 1299 1300source "drivers/pcmcia/Kconfig" 1301 1302endmenu 1303 1304menu "Kernel Features" 1305 1306source "kernel/time/Kconfig" 1307 1308config SMP 1309 bool "Symmetric Multi-Processing" 1310 depends on CPU_V6K || CPU_V7 1311 depends on GENERIC_CLOCKEVENTS 1312 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1313 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1314 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1315 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE 1316 select USE_GENERIC_SMP_HELPERS 1317 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1318 help 1319 This enables support for systems with more than one CPU. If you have 1320 a system with only one CPU, like most personal computers, say N. If 1321 you have a system with more than one CPU, say Y. 1322 1323 If you say N here, the kernel will run on single and multiprocessor 1324 machines, but will use only one CPU of a multiprocessor machine. If 1325 you say Y here, the kernel will run on many, but not all, single 1326 processor machines. On a single processor machine, the kernel will 1327 run faster if you say N here. 1328 1329 See also <file:Documentation/i386/IO-APIC.txt>, 1330 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1331 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1332 1333 If you don't know what to do here, say N. 1334 1335config SMP_ON_UP 1336 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1337 depends on EXPERIMENTAL 1338 depends on SMP && !XIP_KERNEL 1339 default y 1340 help 1341 SMP kernels contain instructions which fail on non-SMP processors. 1342 Enabling this option allows the kernel to modify itself to make 1343 these instructions safe. Disabling it allows about 1K of space 1344 savings. 1345 1346 If you don't know what to do here, say Y. 1347 1348config HAVE_ARM_SCU 1349 bool 1350 depends on SMP 1351 help 1352 This option enables support for the ARM system coherency unit 1353 1354config HAVE_ARM_TWD 1355 bool 1356 depends on SMP 1357 select TICK_ONESHOT 1358 help 1359 This options enables support for the ARM timer and watchdog unit 1360 1361choice 1362 prompt "Memory split" 1363 default VMSPLIT_3G 1364 help 1365 Select the desired split between kernel and user memory. 1366 1367 If you are not absolutely sure what you are doing, leave this 1368 option alone! 1369 1370 config VMSPLIT_3G 1371 bool "3G/1G user/kernel split" 1372 config VMSPLIT_2G 1373 bool "2G/2G user/kernel split" 1374 config VMSPLIT_1G 1375 bool "1G/3G user/kernel split" 1376endchoice 1377 1378config PAGE_OFFSET 1379 hex 1380 default 0x40000000 if VMSPLIT_1G 1381 default 0x80000000 if VMSPLIT_2G 1382 default 0xC0000000 1383 1384config NR_CPUS 1385 int "Maximum number of CPUs (2-32)" 1386 range 2 32 1387 depends on SMP 1388 default "4" 1389 1390config HOTPLUG_CPU 1391 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1392 depends on SMP && HOTPLUG && EXPERIMENTAL 1393 help 1394 Say Y here to experiment with turning CPUs off and on. CPUs 1395 can be controlled through /sys/devices/system/cpu. 1396 1397config LOCAL_TIMERS 1398 bool "Use local timer interrupts" 1399 depends on SMP 1400 default y 1401 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1402 help 1403 Enable support for local timers on SMP platforms, rather then the 1404 legacy IPI broadcast method. Local timers allows the system 1405 accounting to be spread across the timer interval, preventing a 1406 "thundering herd" at every timer tick. 1407 1408source kernel/Kconfig.preempt 1409 1410config HZ 1411 int 1412 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1413 ARCH_S5PV210 || ARCH_EXYNOS4 1414 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1415 default AT91_TIMER_HZ if ARCH_AT91 1416 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1417 default 100 1418 1419config THUMB2_KERNEL 1420 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1421 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1422 select AEABI 1423 select ARM_ASM_UNIFIED 1424 help 1425 By enabling this option, the kernel will be compiled in 1426 Thumb-2 mode. A compiler/assembler that understand the unified 1427 ARM-Thumb syntax is needed. 1428 1429 If unsure, say N. 1430 1431config THUMB2_AVOID_R_ARM_THM_JUMP11 1432 bool "Work around buggy Thumb-2 short branch relocations in gas" 1433 depends on THUMB2_KERNEL && MODULES 1434 default y 1435 help 1436 Various binutils versions can resolve Thumb-2 branches to 1437 locally-defined, preemptible global symbols as short-range "b.n" 1438 branch instructions. 1439 1440 This is a problem, because there's no guarantee the final 1441 destination of the symbol, or any candidate locations for a 1442 trampoline, are within range of the branch. For this reason, the 1443 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1444 relocation in modules at all, and it makes little sense to add 1445 support. 1446 1447 The symptom is that the kernel fails with an "unsupported 1448 relocation" error when loading some modules. 1449 1450 Until fixed tools are available, passing 1451 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1452 code which hits this problem, at the cost of a bit of extra runtime 1453 stack usage in some cases. 1454 1455 The problem is described in more detail at: 1456 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1457 1458 Only Thumb-2 kernels are affected. 1459 1460 Unless you are sure your tools don't have this problem, say Y. 1461 1462config ARM_ASM_UNIFIED 1463 bool 1464 1465config AEABI 1466 bool "Use the ARM EABI to compile the kernel" 1467 help 1468 This option allows for the kernel to be compiled using the latest 1469 ARM ABI (aka EABI). This is only useful if you are using a user 1470 space environment that is also compiled with EABI. 1471 1472 Since there are major incompatibilities between the legacy ABI and 1473 EABI, especially with regard to structure member alignment, this 1474 option also changes the kernel syscall calling convention to 1475 disambiguate both ABIs and allow for backward compatibility support 1476 (selected with CONFIG_OABI_COMPAT). 1477 1478 To use this you need GCC version 4.0.0 or later. 1479 1480config OABI_COMPAT 1481 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1482 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1483 default y 1484 help 1485 This option preserves the old syscall interface along with the 1486 new (ARM EABI) one. It also provides a compatibility layer to 1487 intercept syscalls that have structure arguments which layout 1488 in memory differs between the legacy ABI and the new ARM EABI 1489 (only for non "thumb" binaries). This option adds a tiny 1490 overhead to all syscalls and produces a slightly larger kernel. 1491 If you know you'll be using only pure EABI user space then you 1492 can say N here. If this option is not selected and you attempt 1493 to execute a legacy ABI binary then the result will be 1494 UNPREDICTABLE (in fact it can be predicted that it won't work 1495 at all). If in doubt say Y. 1496 1497config ARCH_HAS_HOLES_MEMORYMODEL 1498 bool 1499 1500config ARCH_SPARSEMEM_ENABLE 1501 bool 1502 1503config ARCH_SPARSEMEM_DEFAULT 1504 def_bool ARCH_SPARSEMEM_ENABLE 1505 1506config ARCH_SELECT_MEMORY_MODEL 1507 def_bool ARCH_SPARSEMEM_ENABLE 1508 1509config HAVE_ARCH_PFN_VALID 1510 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1511 1512config HIGHMEM 1513 bool "High Memory Support" 1514 depends on MMU 1515 help 1516 The address space of ARM processors is only 4 Gigabytes large 1517 and it has to accommodate user address space, kernel address 1518 space as well as some memory mapped IO. That means that, if you 1519 have a large amount of physical memory and/or IO, not all of the 1520 memory can be "permanently mapped" by the kernel. The physical 1521 memory that is not permanently mapped is called "high memory". 1522 1523 Depending on the selected kernel/user memory split, minimum 1524 vmalloc space and actual amount of RAM, you may not need this 1525 option which should result in a slightly faster kernel. 1526 1527 If unsure, say n. 1528 1529config HIGHPTE 1530 bool "Allocate 2nd-level pagetables from highmem" 1531 depends on HIGHMEM 1532 1533config HW_PERF_EVENTS 1534 bool "Enable hardware performance counter support for perf events" 1535 depends on PERF_EVENTS && CPU_HAS_PMU 1536 default y 1537 help 1538 Enable hardware performance counter support for perf events. If 1539 disabled, perf events will use software events only. 1540 1541source "mm/Kconfig" 1542 1543config FORCE_MAX_ZONEORDER 1544 int "Maximum zone order" if ARCH_SHMOBILE 1545 range 11 64 if ARCH_SHMOBILE 1546 default "9" if SA1111 1547 default "11" 1548 help 1549 The kernel memory allocator divides physically contiguous memory 1550 blocks into "zones", where each zone is a power of two number of 1551 pages. This option selects the largest power of two that the kernel 1552 keeps in the memory allocator. If you need to allocate very large 1553 blocks of physically contiguous memory, then you may need to 1554 increase this value. 1555 1556 This config option is actually maximum order plus one. For example, 1557 a value of 11 means that the largest free memory block is 2^10 pages. 1558 1559config LEDS 1560 bool "Timer and CPU usage LEDs" 1561 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1562 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1563 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1564 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1565 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1566 ARCH_AT91 || ARCH_DAVINCI || \ 1567 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1568 help 1569 If you say Y here, the LEDs on your machine will be used 1570 to provide useful information about your current system status. 1571 1572 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1573 be able to select which LEDs are active using the options below. If 1574 you are compiling a kernel for the EBSA-110 or the LART however, the 1575 red LED will simply flash regularly to indicate that the system is 1576 still functional. It is safe to say Y here if you have a CATS 1577 system, but the driver will do nothing. 1578 1579config LEDS_TIMER 1580 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1581 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1582 || MACH_OMAP_PERSEUS2 1583 depends on LEDS 1584 depends on !GENERIC_CLOCKEVENTS 1585 default y if ARCH_EBSA110 1586 help 1587 If you say Y here, one of the system LEDs (the green one on the 1588 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1589 will flash regularly to indicate that the system is still 1590 operational. This is mainly useful to kernel hackers who are 1591 debugging unstable kernels. 1592 1593 The LART uses the same LED for both Timer LED and CPU usage LED 1594 functions. You may choose to use both, but the Timer LED function 1595 will overrule the CPU usage LED. 1596 1597config LEDS_CPU 1598 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1599 !ARCH_OMAP) \ 1600 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1601 || MACH_OMAP_PERSEUS2 1602 depends on LEDS 1603 help 1604 If you say Y here, the red LED will be used to give a good real 1605 time indication of CPU usage, by lighting whenever the idle task 1606 is not currently executing. 1607 1608 The LART uses the same LED for both Timer LED and CPU usage LED 1609 functions. You may choose to use both, but the Timer LED function 1610 will overrule the CPU usage LED. 1611 1612config ALIGNMENT_TRAP 1613 bool 1614 depends on CPU_CP15_MMU 1615 default y if !ARCH_EBSA110 1616 select HAVE_PROC_CPU if PROC_FS 1617 help 1618 ARM processors cannot fetch/store information which is not 1619 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1620 address divisible by 4. On 32-bit ARM processors, these non-aligned 1621 fetch/store instructions will be emulated in software if you say 1622 here, which has a severe performance impact. This is necessary for 1623 correct operation of some network protocols. With an IP-only 1624 configuration it is safe to say N, otherwise say Y. 1625 1626config UACCESS_WITH_MEMCPY 1627 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1628 depends on MMU && EXPERIMENTAL 1629 default y if CPU_FEROCEON 1630 help 1631 Implement faster copy_to_user and clear_user methods for CPU 1632 cores where a 8-word STM instruction give significantly higher 1633 memory write throughput than a sequence of individual 32bit stores. 1634 1635 A possible side effect is a slight increase in scheduling latency 1636 between threads sharing the same address space if they invoke 1637 such copy operations with large buffers. 1638 1639 However, if the CPU data cache is using a write-allocate mode, 1640 this option is unlikely to provide any performance gain. 1641 1642config SECCOMP 1643 bool 1644 prompt "Enable seccomp to safely compute untrusted bytecode" 1645 ---help--- 1646 This kernel feature is useful for number crunching applications 1647 that may need to compute untrusted bytecode during their 1648 execution. By using pipes or other transports made available to 1649 the process as file descriptors supporting the read/write 1650 syscalls, it's possible to isolate those applications in 1651 their own address space using seccomp. Once seccomp is 1652 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1653 and the task is only allowed to execute a few safe syscalls 1654 defined by each seccomp mode. 1655 1656config CC_STACKPROTECTOR 1657 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1658 depends on EXPERIMENTAL 1659 help 1660 This option turns on the -fstack-protector GCC feature. This 1661 feature puts, at the beginning of functions, a canary value on 1662 the stack just before the return address, and validates 1663 the value just before actually returning. Stack based buffer 1664 overflows (that need to overwrite this return address) now also 1665 overwrite the canary, which gets detected and the attack is then 1666 neutralized via a kernel panic. 1667 This feature requires gcc version 4.2 or above. 1668 1669config DEPRECATED_PARAM_STRUCT 1670 bool "Provide old way to pass kernel parameters" 1671 help 1672 This was deprecated in 2001 and announced to live on for 5 years. 1673 Some old boot loaders still use this way. 1674 1675endmenu 1676 1677menu "Boot options" 1678 1679config USE_OF 1680 bool "Flattened Device Tree support" 1681 select OF 1682 select OF_EARLY_FLATTREE 1683 help 1684 Include support for flattened device tree machine descriptions. 1685 1686# Compressed boot loader in ROM. Yes, we really want to ask about 1687# TEXT and BSS so we preserve their values in the config files. 1688config ZBOOT_ROM_TEXT 1689 hex "Compressed ROM boot loader base address" 1690 default "0" 1691 help 1692 The physical address at which the ROM-able zImage is to be 1693 placed in the target. Platforms which normally make use of 1694 ROM-able zImage formats normally set this to a suitable 1695 value in their defconfig file. 1696 1697 If ZBOOT_ROM is not enabled, this has no effect. 1698 1699config ZBOOT_ROM_BSS 1700 hex "Compressed ROM boot loader BSS address" 1701 default "0" 1702 help 1703 The base address of an area of read/write memory in the target 1704 for the ROM-able zImage which must be available while the 1705 decompressor is running. It must be large enough to hold the 1706 entire decompressed kernel plus an additional 128 KiB. 1707 Platforms which normally make use of ROM-able zImage formats 1708 normally set this to a suitable value in their defconfig file. 1709 1710 If ZBOOT_ROM is not enabled, this has no effect. 1711 1712config ZBOOT_ROM 1713 bool "Compressed boot loader in ROM/flash" 1714 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1715 help 1716 Say Y here if you intend to execute your compressed kernel image 1717 (zImage) directly from ROM or flash. If unsure, say N. 1718 1719config ZBOOT_ROM_MMCIF 1720 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1721 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1722 help 1723 Say Y here to include experimental MMCIF loading code in the 1724 ROM-able zImage. With this enabled it is possible to write the 1725 the ROM-able zImage kernel image to an MMC card and boot the 1726 kernel straight from the reset vector. At reset the processor 1727 Mask ROM will load the first part of the the ROM-able zImage 1728 which in turn loads the rest the kernel image to RAM using the 1729 MMCIF hardware block. 1730 1731config CMDLINE 1732 string "Default kernel command string" 1733 default "" 1734 help 1735 On some architectures (EBSA110 and CATS), there is currently no way 1736 for the boot loader to pass arguments to the kernel. For these 1737 architectures, you should supply some command-line options at build 1738 time by entering them here. As a minimum, you should specify the 1739 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1740 1741choice 1742 prompt "Kernel command line type" if CMDLINE != "" 1743 default CMDLINE_FROM_BOOTLOADER 1744 1745config CMDLINE_FROM_BOOTLOADER 1746 bool "Use bootloader kernel arguments if available" 1747 help 1748 Uses the command-line options passed by the boot loader. If 1749 the boot loader doesn't provide any, the default kernel command 1750 string provided in CMDLINE will be used. 1751 1752config CMDLINE_EXTEND 1753 bool "Extend bootloader kernel arguments" 1754 help 1755 The command-line arguments provided by the boot loader will be 1756 appended to the default kernel command string. 1757 1758config CMDLINE_FORCE 1759 bool "Always use the default kernel command string" 1760 help 1761 Always use the default kernel command string, even if the boot 1762 loader passes other arguments to the kernel. 1763 This is useful if you cannot or don't want to change the 1764 command-line options your boot loader passes to the kernel. 1765endchoice 1766 1767config XIP_KERNEL 1768 bool "Kernel Execute-In-Place from ROM" 1769 depends on !ZBOOT_ROM 1770 help 1771 Execute-In-Place allows the kernel to run from non-volatile storage 1772 directly addressable by the CPU, such as NOR flash. This saves RAM 1773 space since the text section of the kernel is not loaded from flash 1774 to RAM. Read-write sections, such as the data section and stack, 1775 are still copied to RAM. The XIP kernel is not compressed since 1776 it has to run directly from flash, so it will take more space to 1777 store it. The flash address used to link the kernel object files, 1778 and for storing it, is configuration dependent. Therefore, if you 1779 say Y here, you must know the proper physical address where to 1780 store the kernel image depending on your own flash memory usage. 1781 1782 Also note that the make target becomes "make xipImage" rather than 1783 "make zImage" or "make Image". The final kernel binary to put in 1784 ROM memory will be arch/arm/boot/xipImage. 1785 1786 If unsure, say N. 1787 1788config XIP_PHYS_ADDR 1789 hex "XIP Kernel Physical Location" 1790 depends on XIP_KERNEL 1791 default "0x00080000" 1792 help 1793 This is the physical address in your flash memory the kernel will 1794 be linked for and stored to. This address is dependent on your 1795 own flash usage. 1796 1797config KEXEC 1798 bool "Kexec system call (EXPERIMENTAL)" 1799 depends on EXPERIMENTAL 1800 help 1801 kexec is a system call that implements the ability to shutdown your 1802 current kernel, and to start another kernel. It is like a reboot 1803 but it is independent of the system firmware. And like a reboot 1804 you can start any kernel with it, not just Linux. 1805 1806 It is an ongoing process to be certain the hardware in a machine 1807 is properly shutdown, so do not be surprised if this code does not 1808 initially work for you. It may help to enable device hotplugging 1809 support. 1810 1811config ATAGS_PROC 1812 bool "Export atags in procfs" 1813 depends on KEXEC 1814 default y 1815 help 1816 Should the atags used to boot the kernel be exported in an "atags" 1817 file in procfs. Useful with kexec. 1818 1819config CRASH_DUMP 1820 bool "Build kdump crash kernel (EXPERIMENTAL)" 1821 depends on EXPERIMENTAL 1822 help 1823 Generate crash dump after being started by kexec. This should 1824 be normally only set in special crash dump kernels which are 1825 loaded in the main kernel with kexec-tools into a specially 1826 reserved region and then later executed after a crash by 1827 kdump/kexec. The crash dump kernel must be compiled to a 1828 memory address not used by the main kernel 1829 1830 For more details see Documentation/kdump/kdump.txt 1831 1832config AUTO_ZRELADDR 1833 bool "Auto calculation of the decompressed kernel image address" 1834 depends on !ZBOOT_ROM && !ARCH_U300 1835 help 1836 ZRELADDR is the physical address where the decompressed kernel 1837 image will be placed. If AUTO_ZRELADDR is selected, the address 1838 will be determined at run-time by masking the current IP with 1839 0xf8000000. This assumes the zImage being placed in the first 128MB 1840 from start of memory. 1841 1842endmenu 1843 1844menu "CPU Power Management" 1845 1846if ARCH_HAS_CPUFREQ 1847 1848source "drivers/cpufreq/Kconfig" 1849 1850config CPU_FREQ_IMX 1851 tristate "CPUfreq driver for i.MX CPUs" 1852 depends on ARCH_MXC && CPU_FREQ 1853 help 1854 This enables the CPUfreq driver for i.MX CPUs. 1855 1856config CPU_FREQ_SA1100 1857 bool 1858 1859config CPU_FREQ_SA1110 1860 bool 1861 1862config CPU_FREQ_INTEGRATOR 1863 tristate "CPUfreq driver for ARM Integrator CPUs" 1864 depends on ARCH_INTEGRATOR && CPU_FREQ 1865 default y 1866 help 1867 This enables the CPUfreq driver for ARM Integrator CPUs. 1868 1869 For details, take a look at <file:Documentation/cpu-freq>. 1870 1871 If in doubt, say Y. 1872 1873config CPU_FREQ_PXA 1874 bool 1875 depends on CPU_FREQ && ARCH_PXA && PXA25x 1876 default y 1877 select CPU_FREQ_DEFAULT_GOV_USERSPACE 1878 1879config CPU_FREQ_S3C64XX 1880 bool "CPUfreq support for Samsung S3C64XX CPUs" 1881 depends on CPU_FREQ && CPU_S3C6410 1882 1883config CPU_FREQ_S3C 1884 bool 1885 help 1886 Internal configuration node for common cpufreq on Samsung SoC 1887 1888config CPU_FREQ_S3C24XX 1889 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 1890 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 1891 select CPU_FREQ_S3C 1892 help 1893 This enables the CPUfreq driver for the Samsung S3C24XX family 1894 of CPUs. 1895 1896 For details, take a look at <file:Documentation/cpu-freq>. 1897 1898 If in doubt, say N. 1899 1900config CPU_FREQ_S3C24XX_PLL 1901 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 1902 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 1903 help 1904 Compile in support for changing the PLL frequency from the 1905 S3C24XX series CPUfreq driver. The PLL takes time to settle 1906 after a frequency change, so by default it is not enabled. 1907 1908 This also means that the PLL tables for the selected CPU(s) will 1909 be built which may increase the size of the kernel image. 1910 1911config CPU_FREQ_S3C24XX_DEBUG 1912 bool "Debug CPUfreq Samsung driver core" 1913 depends on CPU_FREQ_S3C24XX 1914 help 1915 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 1916 1917config CPU_FREQ_S3C24XX_IODEBUG 1918 bool "Debug CPUfreq Samsung driver IO timing" 1919 depends on CPU_FREQ_S3C24XX 1920 help 1921 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 1922 1923config CPU_FREQ_S3C24XX_DEBUGFS 1924 bool "Export debugfs for CPUFreq" 1925 depends on CPU_FREQ_S3C24XX && DEBUG_FS 1926 help 1927 Export status information via debugfs. 1928 1929endif 1930 1931source "drivers/cpuidle/Kconfig" 1932 1933endmenu 1934 1935menu "Floating point emulation" 1936 1937comment "At least one emulation must be selected" 1938 1939config FPE_NWFPE 1940 bool "NWFPE math emulation" 1941 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1942 ---help--- 1943 Say Y to include the NWFPE floating point emulator in the kernel. 1944 This is necessary to run most binaries. Linux does not currently 1945 support floating point hardware so you need to say Y here even if 1946 your machine has an FPA or floating point co-processor podule. 1947 1948 You may say N here if you are going to load the Acorn FPEmulator 1949 early in the bootup. 1950 1951config FPE_NWFPE_XP 1952 bool "Support extended precision" 1953 depends on FPE_NWFPE 1954 help 1955 Say Y to include 80-bit support in the kernel floating-point 1956 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1957 Note that gcc does not generate 80-bit operations by default, 1958 so in most cases this option only enlarges the size of the 1959 floating point emulator without any good reason. 1960 1961 You almost surely want to say N here. 1962 1963config FPE_FASTFPE 1964 bool "FastFPE math emulation (EXPERIMENTAL)" 1965 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 1966 ---help--- 1967 Say Y here to include the FAST floating point emulator in the kernel. 1968 This is an experimental much faster emulator which now also has full 1969 precision for the mantissa. It does not support any exceptions. 1970 It is very simple, and approximately 3-6 times faster than NWFPE. 1971 1972 It should be sufficient for most programs. It may be not suitable 1973 for scientific calculations, but you have to check this for yourself. 1974 If you do not feel you need a faster FP emulation you should better 1975 choose NWFPE. 1976 1977config VFP 1978 bool "VFP-format floating point maths" 1979 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1980 help 1981 Say Y to include VFP support code in the kernel. This is needed 1982 if your hardware includes a VFP unit. 1983 1984 Please see <file:Documentation/arm/VFP/release-notes.txt> for 1985 release notes and additional status information. 1986 1987 Say N if your target does not have VFP hardware. 1988 1989config VFPv3 1990 bool 1991 depends on VFP 1992 default y if CPU_V7 1993 1994config NEON 1995 bool "Advanced SIMD (NEON) Extension support" 1996 depends on VFPv3 && CPU_V7 1997 help 1998 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1999 Extension. 2000 2001endmenu 2002 2003menu "Userspace binary formats" 2004 2005source "fs/Kconfig.binfmt" 2006 2007config ARTHUR 2008 tristate "RISC OS personality" 2009 depends on !AEABI 2010 help 2011 Say Y here to include the kernel code necessary if you want to run 2012 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2013 experimental; if this sounds frightening, say N and sleep in peace. 2014 You can also say M here to compile this support as a module (which 2015 will be called arthur). 2016 2017endmenu 2018 2019menu "Power management options" 2020 2021source "kernel/power/Kconfig" 2022 2023config ARCH_SUSPEND_POSSIBLE 2024 depends on !ARCH_S5P64X0 && !ARCH_S5PC100 2025 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2026 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2027 def_bool y 2028 2029endmenu 2030 2031source "net/Kconfig" 2032 2033source "drivers/Kconfig" 2034 2035source "fs/Kconfig" 2036 2037source "arch/arm/Kconfig.debug" 2038 2039source "security/Kconfig" 2040 2041source "crypto/Kconfig" 2042 2043source "lib/Kconfig" 2044