1config ARM 2 bool 3 default y 4 select HAVE_AOUT 5 select HAVE_DMA_API_DEBUG 6 select HAVE_IDE 7 select HAVE_MEMBLOCK 8 select RTC_LIB 9 select SYS_SUPPORTS_APM_EMULATION 10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) 11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 12 select HAVE_ARCH_KGDB 13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) 14 select HAVE_KRETPROBES if (HAVE_KPROBES) 15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) 18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 19 select HAVE_GENERIC_DMA_COHERENT 20 select HAVE_KERNEL_GZIP 21 select HAVE_KERNEL_LZO 22 select HAVE_KERNEL_LZMA 23 select HAVE_IRQ_WORK 24 select HAVE_PERF_EVENTS 25 select PERF_USE_VMALLOC 26 select HAVE_REGS_AND_STACK_ACCESS_API 27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 28 select HAVE_C_RECORDMCOUNT 29 select HAVE_GENERIC_HARDIRQS 30 select HAVE_SPARSE_IRQ 31 select GENERIC_IRQ_SHOW 32 help 33 The ARM series is a line of low-power-consumption RISC chip designs 34 licensed by ARM Ltd and targeted at embedded applications and 35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 36 manufactured, but legacy ARM-based PC hardware remains popular in 37 Europe. There is an ARM Linux project with a web page at 38 <http://www.arm.linux.org.uk/>. 39 40config HAVE_PWM 41 bool 42 43config MIGHT_HAVE_PCI 44 bool 45 46config SYS_SUPPORTS_APM_EMULATION 47 bool 48 49config HAVE_SCHED_CLOCK 50 bool 51 52config GENERIC_GPIO 53 bool 54 55config ARCH_USES_GETTIMEOFFSET 56 bool 57 default n 58 59config GENERIC_CLOCKEVENTS 60 bool 61 62config GENERIC_CLOCKEVENTS_BROADCAST 63 bool 64 depends on GENERIC_CLOCKEVENTS 65 default y if SMP 66 67config KTIME_SCALAR 68 bool 69 default y 70 71config HAVE_TCM 72 bool 73 select GENERIC_ALLOCATOR 74 75config HAVE_PROC_CPU 76 bool 77 78config NO_IOPORT 79 bool 80 81config EISA 82 bool 83 ---help--- 84 The Extended Industry Standard Architecture (EISA) bus was 85 developed as an open alternative to the IBM MicroChannel bus. 86 87 The EISA bus provided some of the features of the IBM MicroChannel 88 bus while maintaining backward compatibility with cards made for 89 the older ISA bus. The EISA bus saw limited use between 1988 and 90 1995 when it was made obsolete by the PCI bus. 91 92 Say Y here if you are building a kernel for an EISA-based machine. 93 94 Otherwise, say N. 95 96config SBUS 97 bool 98 99config MCA 100 bool 101 help 102 MicroChannel Architecture is found in some IBM PS/2 machines and 103 laptops. It is a bus system similar to PCI or ISA. See 104 <file:Documentation/mca.txt> (and especially the web page given 105 there) before attempting to build an MCA bus kernel. 106 107config STACKTRACE_SUPPORT 108 bool 109 default y 110 111config HAVE_LATENCYTOP_SUPPORT 112 bool 113 depends on !SMP 114 default y 115 116config LOCKDEP_SUPPORT 117 bool 118 default y 119 120config TRACE_IRQFLAGS_SUPPORT 121 bool 122 default y 123 124config HARDIRQS_SW_RESEND 125 bool 126 default y 127 128config GENERIC_IRQ_PROBE 129 bool 130 default y 131 132config GENERIC_LOCKBREAK 133 bool 134 default y 135 depends on SMP && PREEMPT 136 137config RWSEM_GENERIC_SPINLOCK 138 bool 139 default y 140 141config RWSEM_XCHGADD_ALGORITHM 142 bool 143 144config ARCH_HAS_ILOG2_U32 145 bool 146 147config ARCH_HAS_ILOG2_U64 148 bool 149 150config ARCH_HAS_CPUFREQ 151 bool 152 help 153 Internal node to signify that the ARCH has CPUFREQ support 154 and that the relevant menu configurations are displayed for 155 it. 156 157config ARCH_HAS_CPU_IDLE_WAIT 158 def_bool y 159 160config GENERIC_HWEIGHT 161 bool 162 default y 163 164config GENERIC_CALIBRATE_DELAY 165 bool 166 default y 167 168config ARCH_MAY_HAVE_PC_FDC 169 bool 170 171config ZONE_DMA 172 bool 173 174config NEED_DMA_MAP_STATE 175 def_bool y 176 177config GENERIC_ISA_DMA 178 bool 179 180config FIQ 181 bool 182 183config ARCH_MTD_XIP 184 bool 185 186config VECTORS_BASE 187 hex 188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 189 default DRAM_BASE if REMAP_VECTORS_TO_RAM 190 default 0x00000000 191 help 192 The base address of exception vectors. 193 194config ARM_PATCH_PHYS_VIRT 195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" 196 depends on EXPERIMENTAL 197 depends on !XIP_KERNEL && MMU 198 depends on !ARCH_REALVIEW || !SPARSEMEM 199 help 200 Patch phys-to-virt and virt-to-phys translation functions at 201 boot and module load time according to the position of the 202 kernel in system memory. 203 204 This can only be used with non-XIP MMU kernels where the base 205 of physical memory is at a 16MB boundary, or theoretically 64K 206 for the MSM machine class. 207 208config ARM_PATCH_PHYS_VIRT_16BIT 209 def_bool y 210 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM 211 help 212 This option extends the physical to virtual translation patching 213 to allow physical memory down to a theoretical minimum of 64K 214 boundaries. 215 216source "init/Kconfig" 217 218source "kernel/Kconfig.freezer" 219 220menu "System Type" 221 222config MMU 223 bool "MMU-based Paged Memory Management Support" 224 default y 225 help 226 Select if you want MMU-based virtualised addressing space 227 support by paged memory management. If unsure, say 'Y'. 228 229# 230# The "ARM system type" choice list is ordered alphabetically by option 231# text. Please add new entries in the option alphabetic order. 232# 233choice 234 prompt "ARM system type" 235 default ARCH_VERSATILE 236 237config ARCH_INTEGRATOR 238 bool "ARM Ltd. Integrator family" 239 select ARM_AMBA 240 select ARCH_HAS_CPUFREQ 241 select CLKDEV_LOOKUP 242 select ICST 243 select GENERIC_CLOCKEVENTS 244 select PLAT_VERSATILE 245 select PLAT_VERSATILE_FPGA_IRQ 246 help 247 Support for ARM's Integrator platform. 248 249config ARCH_REALVIEW 250 bool "ARM Ltd. RealView family" 251 select ARM_AMBA 252 select CLKDEV_LOOKUP 253 select ICST 254 select GENERIC_CLOCKEVENTS 255 select ARCH_WANT_OPTIONAL_GPIOLIB 256 select PLAT_VERSATILE 257 select PLAT_VERSATILE_CLCD 258 select ARM_TIMER_SP804 259 select GPIO_PL061 if GPIOLIB 260 help 261 This enables support for ARM Ltd RealView boards. 262 263config ARCH_VERSATILE 264 bool "ARM Ltd. Versatile family" 265 select ARM_AMBA 266 select ARM_VIC 267 select CLKDEV_LOOKUP 268 select ICST 269 select GENERIC_CLOCKEVENTS 270 select ARCH_WANT_OPTIONAL_GPIOLIB 271 select PLAT_VERSATILE 272 select PLAT_VERSATILE_CLCD 273 select PLAT_VERSATILE_FPGA_IRQ 274 select ARM_TIMER_SP804 275 help 276 This enables support for ARM Ltd Versatile board. 277 278config ARCH_VEXPRESS 279 bool "ARM Ltd. Versatile Express family" 280 select ARCH_WANT_OPTIONAL_GPIOLIB 281 select ARM_AMBA 282 select ARM_TIMER_SP804 283 select CLKDEV_LOOKUP 284 select GENERIC_CLOCKEVENTS 285 select HAVE_CLK 286 select HAVE_PATA_PLATFORM 287 select ICST 288 select PLAT_VERSATILE 289 select PLAT_VERSATILE_CLCD 290 help 291 This enables support for the ARM Ltd Versatile Express boards. 292 293config ARCH_AT91 294 bool "Atmel AT91" 295 select ARCH_REQUIRE_GPIOLIB 296 select HAVE_CLK 297 select CLKDEV_LOOKUP 298 select ARM_PATCH_PHYS_VIRT if MMU 299 help 300 This enables support for systems based on the Atmel AT91RM9200, 301 AT91SAM9 and AT91CAP9 processors. 302 303config ARCH_BCMRING 304 bool "Broadcom BCMRING" 305 depends on MMU 306 select CPU_V6 307 select ARM_AMBA 308 select ARM_TIMER_SP804 309 select CLKDEV_LOOKUP 310 select GENERIC_CLOCKEVENTS 311 select ARCH_WANT_OPTIONAL_GPIOLIB 312 help 313 Support for Broadcom's BCMRing platform. 314 315config ARCH_CLPS711X 316 bool "Cirrus Logic CLPS711x/EP721x-based" 317 select CPU_ARM720T 318 select ARCH_USES_GETTIMEOFFSET 319 help 320 Support for Cirrus Logic 711x/721x based boards. 321 322config ARCH_CNS3XXX 323 bool "Cavium Networks CNS3XXX family" 324 select CPU_V6 325 select GENERIC_CLOCKEVENTS 326 select ARM_GIC 327 select MIGHT_HAVE_PCI 328 select PCI_DOMAINS if PCI 329 help 330 Support for Cavium Networks CNS3XXX platform. 331 332config ARCH_GEMINI 333 bool "Cortina Systems Gemini" 334 select CPU_FA526 335 select ARCH_REQUIRE_GPIOLIB 336 select ARCH_USES_GETTIMEOFFSET 337 help 338 Support for the Cortina Systems Gemini family SoCs 339 340config ARCH_EBSA110 341 bool "EBSA-110" 342 select CPU_SA110 343 select ISA 344 select NO_IOPORT 345 select ARCH_USES_GETTIMEOFFSET 346 help 347 This is an evaluation board for the StrongARM processor available 348 from Digital. It has limited hardware on-board, including an 349 Ethernet interface, two PCMCIA sockets, two serial ports and a 350 parallel port. 351 352config ARCH_EP93XX 353 bool "EP93xx-based" 354 select CPU_ARM920T 355 select ARM_AMBA 356 select ARM_VIC 357 select CLKDEV_LOOKUP 358 select ARCH_REQUIRE_GPIOLIB 359 select ARCH_HAS_HOLES_MEMORYMODEL 360 select ARCH_USES_GETTIMEOFFSET 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select GENERIC_CLOCKEVENTS 369 help 370 Support for systems based on the DC21285 companion chip 371 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 372 373config ARCH_MXC 374 bool "Freescale MXC/iMX-based" 375 select GENERIC_CLOCKEVENTS 376 select ARCH_REQUIRE_GPIOLIB 377 select CLKDEV_LOOKUP 378 select CLKSRC_MMIO 379 select HAVE_SCHED_CLOCK 380 help 381 Support for Freescale MXC/iMX-based family of processors 382 383config ARCH_MXS 384 bool "Freescale MXS-based" 385 select GENERIC_CLOCKEVENTS 386 select ARCH_REQUIRE_GPIOLIB 387 select CLKDEV_LOOKUP 388 select CLKSRC_MMIO 389 help 390 Support for Freescale MXS-based family of processors 391 392config ARCH_NETX 393 bool "Hilscher NetX based" 394 select CLKSRC_MMIO 395 select CPU_ARM926T 396 select ARM_VIC 397 select GENERIC_CLOCKEVENTS 398 help 399 This enables support for systems based on the Hilscher NetX Soc 400 401config ARCH_H720X 402 bool "Hynix HMS720x-based" 403 select CPU_ARM720T 404 select ISA_DMA_API 405 select ARCH_USES_GETTIMEOFFSET 406 help 407 This enables support for systems based on the Hynix HMS720x 408 409config ARCH_IOP13XX 410 bool "IOP13xx-based" 411 depends on MMU 412 select CPU_XSC3 413 select PLAT_IOP 414 select PCI 415 select ARCH_SUPPORTS_MSI 416 select VMSPLIT_1G 417 help 418 Support for Intel's IOP13XX (XScale) family of processors. 419 420config ARCH_IOP32X 421 bool "IOP32x-based" 422 depends on MMU 423 select CPU_XSCALE 424 select PLAT_IOP 425 select PCI 426 select ARCH_REQUIRE_GPIOLIB 427 help 428 Support for Intel's 80219 and IOP32X (XScale) family of 429 processors. 430 431config ARCH_IOP33X 432 bool "IOP33x-based" 433 depends on MMU 434 select CPU_XSCALE 435 select PLAT_IOP 436 select PCI 437 select ARCH_REQUIRE_GPIOLIB 438 help 439 Support for Intel's IOP33X (XScale) family of processors. 440 441config ARCH_IXP23XX 442 bool "IXP23XX-based" 443 depends on MMU 444 select CPU_XSC3 445 select PCI 446 select ARCH_USES_GETTIMEOFFSET 447 help 448 Support for Intel's IXP23xx (XScale) family of processors. 449 450config ARCH_IXP2000 451 bool "IXP2400/2800-based" 452 depends on MMU 453 select CPU_XSCALE 454 select PCI 455 select ARCH_USES_GETTIMEOFFSET 456 help 457 Support for Intel's IXP2400/2800 (XScale) family of processors. 458 459config ARCH_IXP4XX 460 bool "IXP4xx-based" 461 depends on MMU 462 select CLKSRC_MMIO 463 select CPU_XSCALE 464 select GENERIC_GPIO 465 select GENERIC_CLOCKEVENTS 466 select HAVE_SCHED_CLOCK 467 select MIGHT_HAVE_PCI 468 select DMABOUNCE if PCI 469 help 470 Support for Intel's IXP4XX (XScale) family of processors. 471 472config ARCH_DOVE 473 bool "Marvell Dove" 474 select CPU_V7 475 select PCI 476 select ARCH_REQUIRE_GPIOLIB 477 select GENERIC_CLOCKEVENTS 478 select PLAT_ORION 479 help 480 Support for the Marvell Dove SoC 88AP510 481 482config ARCH_KIRKWOOD 483 bool "Marvell Kirkwood" 484 select CPU_FEROCEON 485 select PCI 486 select ARCH_REQUIRE_GPIOLIB 487 select GENERIC_CLOCKEVENTS 488 select PLAT_ORION 489 help 490 Support for the following Marvell Kirkwood series SoCs: 491 88F6180, 88F6192 and 88F6281. 492 493config ARCH_LOKI 494 bool "Marvell Loki (88RC8480)" 495 select CPU_FEROCEON 496 select GENERIC_CLOCKEVENTS 497 select PLAT_ORION 498 help 499 Support for the Marvell Loki (88RC8480) SoC. 500 501config ARCH_LPC32XX 502 bool "NXP LPC32XX" 503 select CLKSRC_MMIO 504 select CPU_ARM926T 505 select ARCH_REQUIRE_GPIOLIB 506 select HAVE_IDE 507 select ARM_AMBA 508 select USB_ARCH_HAS_OHCI 509 select CLKDEV_LOOKUP 510 select GENERIC_TIME 511 select GENERIC_CLOCKEVENTS 512 help 513 Support for the NXP LPC32XX family of processors 514 515config ARCH_MV78XX0 516 bool "Marvell MV78xx0" 517 select CPU_FEROCEON 518 select PCI 519 select ARCH_REQUIRE_GPIOLIB 520 select GENERIC_CLOCKEVENTS 521 select PLAT_ORION 522 help 523 Support for the following Marvell MV78xx0 series SoCs: 524 MV781x0, MV782x0. 525 526config ARCH_ORION5X 527 bool "Marvell Orion" 528 depends on MMU 529 select CPU_FEROCEON 530 select PCI 531 select ARCH_REQUIRE_GPIOLIB 532 select GENERIC_CLOCKEVENTS 533 select PLAT_ORION 534 help 535 Support for the following Marvell Orion 5x series SoCs: 536 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 537 Orion-2 (5281), Orion-1-90 (6183). 538 539config ARCH_MMP 540 bool "Marvell PXA168/910/MMP2" 541 depends on MMU 542 select ARCH_REQUIRE_GPIOLIB 543 select CLKDEV_LOOKUP 544 select GENERIC_CLOCKEVENTS 545 select HAVE_SCHED_CLOCK 546 select TICK_ONESHOT 547 select PLAT_PXA 548 select SPARSE_IRQ 549 help 550 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 551 552config ARCH_KS8695 553 bool "Micrel/Kendin KS8695" 554 select CPU_ARM922T 555 select ARCH_REQUIRE_GPIOLIB 556 select ARCH_USES_GETTIMEOFFSET 557 help 558 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 559 System-on-Chip devices. 560 561config ARCH_W90X900 562 bool "Nuvoton W90X900 CPU" 563 select CPU_ARM926T 564 select ARCH_REQUIRE_GPIOLIB 565 select CLKDEV_LOOKUP 566 select CLKSRC_MMIO 567 select GENERIC_CLOCKEVENTS 568 help 569 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 570 At present, the w90x900 has been renamed nuc900, regarding 571 the ARM series product line, you can login the following 572 link address to know more. 573 574 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 575 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 576 577config ARCH_NUC93X 578 bool "Nuvoton NUC93X CPU" 579 select CPU_ARM926T 580 select CLKDEV_LOOKUP 581 help 582 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a 583 low-power and high performance MPEG-4/JPEG multimedia controller chip. 584 585config ARCH_TEGRA 586 bool "NVIDIA Tegra" 587 select CLKDEV_LOOKUP 588 select CLKSRC_MMIO 589 select GENERIC_TIME 590 select GENERIC_CLOCKEVENTS 591 select GENERIC_GPIO 592 select HAVE_CLK 593 select HAVE_SCHED_CLOCK 594 select ARCH_HAS_BARRIERS if CACHE_L2X0 595 select ARCH_HAS_CPUFREQ 596 help 597 This enables support for NVIDIA Tegra based systems (Tegra APX, 598 Tegra 6xx and Tegra 2 series). 599 600config ARCH_PNX4008 601 bool "Philips Nexperia PNX4008 Mobile" 602 select CPU_ARM926T 603 select CLKDEV_LOOKUP 604 select ARCH_USES_GETTIMEOFFSET 605 help 606 This enables support for Philips PNX4008 mobile platform. 607 608config ARCH_PXA 609 bool "PXA2xx/PXA3xx-based" 610 depends on MMU 611 select ARCH_MTD_XIP 612 select ARCH_HAS_CPUFREQ 613 select CLKDEV_LOOKUP 614 select CLKSRC_MMIO 615 select ARCH_REQUIRE_GPIOLIB 616 select GENERIC_CLOCKEVENTS 617 select HAVE_SCHED_CLOCK 618 select TICK_ONESHOT 619 select PLAT_PXA 620 select SPARSE_IRQ 621 help 622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 623 624config ARCH_MSM 625 bool "Qualcomm MSM" 626 select HAVE_CLK 627 select GENERIC_CLOCKEVENTS 628 select ARCH_REQUIRE_GPIOLIB 629 select CLKDEV_LOOKUP 630 help 631 Support for Qualcomm MSM/QSD based systems. This runs on the 632 apps processor of the MSM/QSD and depends on a shared memory 633 interface to the modem processor which runs the baseband 634 stack and controls some vital subsystems 635 (clock and power control, etc). 636 637config ARCH_SHMOBILE 638 bool "Renesas SH-Mobile / R-Mobile" 639 select HAVE_CLK 640 select CLKDEV_LOOKUP 641 select GENERIC_CLOCKEVENTS 642 select NO_IOPORT 643 select SPARSE_IRQ 644 select MULTI_IRQ_HANDLER 645 help 646 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 647 648config ARCH_RPC 649 bool "RiscPC" 650 select ARCH_ACORN 651 select FIQ 652 select TIMER_ACORN 653 select ARCH_MAY_HAVE_PC_FDC 654 select HAVE_PATA_PLATFORM 655 select ISA_DMA_API 656 select NO_IOPORT 657 select ARCH_SPARSEMEM_ENABLE 658 select ARCH_USES_GETTIMEOFFSET 659 help 660 On the Acorn Risc-PC, Linux can support the internal IDE disk and 661 CD-ROM interface, serial and parallel port, and the floppy drive. 662 663config ARCH_SA1100 664 bool "SA1100-based" 665 select CLKSRC_MMIO 666 select CPU_SA1100 667 select ISA 668 select ARCH_SPARSEMEM_ENABLE 669 select ARCH_MTD_XIP 670 select ARCH_HAS_CPUFREQ 671 select CPU_FREQ 672 select GENERIC_CLOCKEVENTS 673 select HAVE_CLK 674 select HAVE_SCHED_CLOCK 675 select TICK_ONESHOT 676 select ARCH_REQUIRE_GPIOLIB 677 help 678 Support for StrongARM 11x0 based boards. 679 680config ARCH_S3C2410 681 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450" 682 select GENERIC_GPIO 683 select ARCH_HAS_CPUFREQ 684 select HAVE_CLK 685 select ARCH_USES_GETTIMEOFFSET 686 select HAVE_S3C2410_I2C if I2C 687 help 688 Samsung S3C2410X CPU based systems, such as the Simtec Electronics 689 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or 690 the Samsung SMDK2410 development board (and derivatives). 691 692 Note, the S3C2416 and the S3C2450 are so close that they even share 693 the same SoC ID code. This means that there is no separate machine 694 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first. 695 696config ARCH_S3C64XX 697 bool "Samsung S3C64XX" 698 select PLAT_SAMSUNG 699 select CPU_V6 700 select ARM_VIC 701 select HAVE_CLK 702 select NO_IOPORT 703 select ARCH_USES_GETTIMEOFFSET 704 select ARCH_HAS_CPUFREQ 705 select ARCH_REQUIRE_GPIOLIB 706 select SAMSUNG_CLKSRC 707 select SAMSUNG_IRQ_VIC_TIMER 708 select SAMSUNG_IRQ_UART 709 select S3C_GPIO_TRACK 710 select S3C_GPIO_PULL_UPDOWN 711 select S3C_GPIO_CFG_S3C24XX 712 select S3C_GPIO_CFG_S3C64XX 713 select S3C_DEV_NAND 714 select USB_ARCH_HAS_OHCI 715 select SAMSUNG_GPIOLIB_4BIT 716 select HAVE_S3C2410_I2C if I2C 717 select HAVE_S3C2410_WATCHDOG if WATCHDOG 718 help 719 Samsung S3C64XX series based systems 720 721config ARCH_S5P64X0 722 bool "Samsung S5P6440 S5P6450" 723 select CPU_V6 724 select GENERIC_GPIO 725 select HAVE_CLK 726 select HAVE_S3C2410_WATCHDOG if WATCHDOG 727 select GENERIC_CLOCKEVENTS 728 select HAVE_SCHED_CLOCK 729 select HAVE_S3C2410_I2C if I2C 730 select HAVE_S3C_RTC if RTC_CLASS 731 help 732 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 733 SMDK6450. 734 735config ARCH_S5PC100 736 bool "Samsung S5PC100" 737 select GENERIC_GPIO 738 select HAVE_CLK 739 select CPU_V7 740 select ARM_L1_CACHE_SHIFT_6 741 select ARCH_USES_GETTIMEOFFSET 742 select HAVE_S3C2410_I2C if I2C 743 select HAVE_S3C_RTC if RTC_CLASS 744 select HAVE_S3C2410_WATCHDOG if WATCHDOG 745 help 746 Samsung S5PC100 series based systems 747 748config ARCH_S5PV210 749 bool "Samsung S5PV210/S5PC110" 750 select CPU_V7 751 select ARCH_SPARSEMEM_ENABLE 752 select GENERIC_GPIO 753 select HAVE_CLK 754 select ARM_L1_CACHE_SHIFT_6 755 select ARCH_HAS_CPUFREQ 756 select GENERIC_CLOCKEVENTS 757 select HAVE_SCHED_CLOCK 758 select HAVE_S3C2410_I2C if I2C 759 select HAVE_S3C_RTC if RTC_CLASS 760 select HAVE_S3C2410_WATCHDOG if WATCHDOG 761 help 762 Samsung S5PV210/S5PC110 series based systems 763 764config ARCH_EXYNOS4 765 bool "Samsung EXYNOS4" 766 select CPU_V7 767 select ARCH_SPARSEMEM_ENABLE 768 select GENERIC_GPIO 769 select HAVE_CLK 770 select ARCH_HAS_CPUFREQ 771 select GENERIC_CLOCKEVENTS 772 select HAVE_S3C_RTC if RTC_CLASS 773 select HAVE_S3C2410_I2C if I2C 774 select HAVE_S3C2410_WATCHDOG if WATCHDOG 775 help 776 Samsung EXYNOS4 series based systems 777 778config ARCH_SHARK 779 bool "Shark" 780 select CPU_SA110 781 select ISA 782 select ISA_DMA 783 select ZONE_DMA 784 select PCI 785 select ARCH_USES_GETTIMEOFFSET 786 help 787 Support for the StrongARM based Digital DNARD machine, also known 788 as "Shark" (<http://www.shark-linux.de/shark.html>). 789 790config ARCH_TCC_926 791 bool "Telechips TCC ARM926-based systems" 792 select CLKSRC_MMIO 793 select CPU_ARM926T 794 select HAVE_CLK 795 select CLKDEV_LOOKUP 796 select GENERIC_CLOCKEVENTS 797 help 798 Support for Telechips TCC ARM926-based systems. 799 800config ARCH_U300 801 bool "ST-Ericsson U300 Series" 802 depends on MMU 803 select CLKSRC_MMIO 804 select CPU_ARM926T 805 select HAVE_SCHED_CLOCK 806 select HAVE_TCM 807 select ARM_AMBA 808 select ARM_VIC 809 select GENERIC_CLOCKEVENTS 810 select CLKDEV_LOOKUP 811 select GENERIC_GPIO 812 help 813 Support for ST-Ericsson U300 series mobile platforms. 814 815config ARCH_U8500 816 bool "ST-Ericsson U8500 Series" 817 select CPU_V7 818 select ARM_AMBA 819 select GENERIC_CLOCKEVENTS 820 select CLKDEV_LOOKUP 821 select ARCH_REQUIRE_GPIOLIB 822 select ARCH_HAS_CPUFREQ 823 help 824 Support for ST-Ericsson's Ux500 architecture 825 826config ARCH_NOMADIK 827 bool "STMicroelectronics Nomadik" 828 select ARM_AMBA 829 select ARM_VIC 830 select CPU_ARM926T 831 select CLKDEV_LOOKUP 832 select GENERIC_CLOCKEVENTS 833 select ARCH_REQUIRE_GPIOLIB 834 help 835 Support for the Nomadik platform by ST-Ericsson 836 837config ARCH_DAVINCI 838 bool "TI DaVinci" 839 select GENERIC_CLOCKEVENTS 840 select ARCH_REQUIRE_GPIOLIB 841 select ZONE_DMA 842 select HAVE_IDE 843 select CLKDEV_LOOKUP 844 select GENERIC_ALLOCATOR 845 select GENERIC_IRQ_CHIP 846 select ARCH_HAS_HOLES_MEMORYMODEL 847 help 848 Support for TI's DaVinci platform. 849 850config ARCH_OMAP 851 bool "TI OMAP" 852 select HAVE_CLK 853 select ARCH_REQUIRE_GPIOLIB 854 select ARCH_HAS_CPUFREQ 855 select GENERIC_CLOCKEVENTS 856 select HAVE_SCHED_CLOCK 857 select ARCH_HAS_HOLES_MEMORYMODEL 858 help 859 Support for TI's OMAP platform (OMAP1/2/3/4). 860 861config PLAT_SPEAR 862 bool "ST SPEAr" 863 select ARM_AMBA 864 select ARCH_REQUIRE_GPIOLIB 865 select CLKDEV_LOOKUP 866 select CLKSRC_MMIO 867 select GENERIC_CLOCKEVENTS 868 select HAVE_CLK 869 help 870 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). 871 872config ARCH_VT8500 873 bool "VIA/WonderMedia 85xx" 874 select CPU_ARM926T 875 select GENERIC_GPIO 876 select ARCH_HAS_CPUFREQ 877 select GENERIC_CLOCKEVENTS 878 select ARCH_REQUIRE_GPIOLIB 879 select HAVE_PWM 880 help 881 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 882endchoice 883 884# 885# This is sorted alphabetically by mach-* pathname. However, plat-* 886# Kconfigs may be included either alphabetically (according to the 887# plat- suffix) or along side the corresponding mach-* source. 888# 889source "arch/arm/mach-at91/Kconfig" 890 891source "arch/arm/mach-bcmring/Kconfig" 892 893source "arch/arm/mach-clps711x/Kconfig" 894 895source "arch/arm/mach-cns3xxx/Kconfig" 896 897source "arch/arm/mach-davinci/Kconfig" 898 899source "arch/arm/mach-dove/Kconfig" 900 901source "arch/arm/mach-ep93xx/Kconfig" 902 903source "arch/arm/mach-footbridge/Kconfig" 904 905source "arch/arm/mach-gemini/Kconfig" 906 907source "arch/arm/mach-h720x/Kconfig" 908 909source "arch/arm/mach-integrator/Kconfig" 910 911source "arch/arm/mach-iop32x/Kconfig" 912 913source "arch/arm/mach-iop33x/Kconfig" 914 915source "arch/arm/mach-iop13xx/Kconfig" 916 917source "arch/arm/mach-ixp4xx/Kconfig" 918 919source "arch/arm/mach-ixp2000/Kconfig" 920 921source "arch/arm/mach-ixp23xx/Kconfig" 922 923source "arch/arm/mach-kirkwood/Kconfig" 924 925source "arch/arm/mach-ks8695/Kconfig" 926 927source "arch/arm/mach-loki/Kconfig" 928 929source "arch/arm/mach-lpc32xx/Kconfig" 930 931source "arch/arm/mach-msm/Kconfig" 932 933source "arch/arm/mach-mv78xx0/Kconfig" 934 935source "arch/arm/plat-mxc/Kconfig" 936 937source "arch/arm/mach-mxs/Kconfig" 938 939source "arch/arm/mach-netx/Kconfig" 940 941source "arch/arm/mach-nomadik/Kconfig" 942source "arch/arm/plat-nomadik/Kconfig" 943 944source "arch/arm/mach-nuc93x/Kconfig" 945 946source "arch/arm/plat-omap/Kconfig" 947 948source "arch/arm/mach-omap1/Kconfig" 949 950source "arch/arm/mach-omap2/Kconfig" 951 952source "arch/arm/mach-orion5x/Kconfig" 953 954source "arch/arm/mach-pxa/Kconfig" 955source "arch/arm/plat-pxa/Kconfig" 956 957source "arch/arm/mach-mmp/Kconfig" 958 959source "arch/arm/mach-realview/Kconfig" 960 961source "arch/arm/mach-sa1100/Kconfig" 962 963source "arch/arm/plat-samsung/Kconfig" 964source "arch/arm/plat-s3c24xx/Kconfig" 965source "arch/arm/plat-s5p/Kconfig" 966 967source "arch/arm/plat-spear/Kconfig" 968 969source "arch/arm/plat-tcc/Kconfig" 970 971if ARCH_S3C2410 972source "arch/arm/mach-s3c2400/Kconfig" 973source "arch/arm/mach-s3c2410/Kconfig" 974source "arch/arm/mach-s3c2412/Kconfig" 975source "arch/arm/mach-s3c2416/Kconfig" 976source "arch/arm/mach-s3c2440/Kconfig" 977source "arch/arm/mach-s3c2443/Kconfig" 978endif 979 980if ARCH_S3C64XX 981source "arch/arm/mach-s3c64xx/Kconfig" 982endif 983 984source "arch/arm/mach-s5p64x0/Kconfig" 985 986source "arch/arm/mach-s5pc100/Kconfig" 987 988source "arch/arm/mach-s5pv210/Kconfig" 989 990source "arch/arm/mach-exynos4/Kconfig" 991 992source "arch/arm/mach-shmobile/Kconfig" 993 994source "arch/arm/mach-tegra/Kconfig" 995 996source "arch/arm/mach-u300/Kconfig" 997 998source "arch/arm/mach-ux500/Kconfig" 999 1000source "arch/arm/mach-versatile/Kconfig" 1001 1002source "arch/arm/mach-vexpress/Kconfig" 1003source "arch/arm/plat-versatile/Kconfig" 1004 1005source "arch/arm/mach-vt8500/Kconfig" 1006 1007source "arch/arm/mach-w90x900/Kconfig" 1008 1009# Definitions to make life easier 1010config ARCH_ACORN 1011 bool 1012 1013config PLAT_IOP 1014 bool 1015 select GENERIC_CLOCKEVENTS 1016 select HAVE_SCHED_CLOCK 1017 1018config PLAT_ORION 1019 bool 1020 select CLKSRC_MMIO 1021 select GENERIC_IRQ_CHIP 1022 select HAVE_SCHED_CLOCK 1023 1024config PLAT_PXA 1025 bool 1026 1027config PLAT_VERSATILE 1028 bool 1029 1030config ARM_TIMER_SP804 1031 bool 1032 select CLKSRC_MMIO 1033 1034source arch/arm/mm/Kconfig 1035 1036config IWMMXT 1037 bool "Enable iWMMXt support" 1038 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 1039 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP 1040 help 1041 Enable support for iWMMXt context switching at run time if 1042 running on a CPU that supports it. 1043 1044# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER 1045config XSCALE_PMU 1046 bool 1047 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 1048 default y 1049 1050config CPU_HAS_PMU 1051 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ 1052 (!ARCH_OMAP3 || OMAP3_EMU) 1053 default y 1054 bool 1055 1056config MULTI_IRQ_HANDLER 1057 bool 1058 help 1059 Allow each machine to specify it's own IRQ handler at run time. 1060 1061if !MMU 1062source "arch/arm/Kconfig-nommu" 1063endif 1064 1065config ARM_ERRATA_411920 1066 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1067 depends on CPU_V6 || CPU_V6K 1068 help 1069 Invalidation of the Instruction Cache operation can 1070 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1071 It does not affect the MPCore. This option enables the ARM Ltd. 1072 recommended workaround. 1073 1074config ARM_ERRATA_430973 1075 bool "ARM errata: Stale prediction on replaced interworking branch" 1076 depends on CPU_V7 1077 help 1078 This option enables the workaround for the 430973 Cortex-A8 1079 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb 1080 interworking branch is replaced with another code sequence at the 1081 same virtual address, whether due to self-modifying code or virtual 1082 to physical address re-mapping, Cortex-A8 does not recover from the 1083 stale interworking branch prediction. This results in Cortex-A8 1084 executing the new code sequence in the incorrect ARM or Thumb state. 1085 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1086 and also flushes the branch target cache at every context switch. 1087 Note that setting specific bits in the ACTLR register may not be 1088 available in non-secure mode. 1089 1090config ARM_ERRATA_458693 1091 bool "ARM errata: Processor deadlock when a false hazard is created" 1092 depends on CPU_V7 1093 help 1094 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1095 erratum. For very specific sequences of memory operations, it is 1096 possible for a hazard condition intended for a cache line to instead 1097 be incorrectly associated with a different cache line. This false 1098 hazard might then cause a processor deadlock. The workaround enables 1099 the L1 caching of the NEON accesses and disables the PLD instruction 1100 in the ACTLR register. Note that setting specific bits in the ACTLR 1101 register may not be available in non-secure mode. 1102 1103config ARM_ERRATA_460075 1104 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1105 depends on CPU_V7 1106 help 1107 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1108 erratum. Any asynchronous access to the L2 cache may encounter a 1109 situation in which recent store transactions to the L2 cache are lost 1110 and overwritten with stale memory contents from external memory. The 1111 workaround disables the write-allocate mode for the L2 cache via the 1112 ACTLR register. Note that setting specific bits in the ACTLR register 1113 may not be available in non-secure mode. 1114 1115config ARM_ERRATA_742230 1116 bool "ARM errata: DMB operation may be faulty" 1117 depends on CPU_V7 && SMP 1118 help 1119 This option enables the workaround for the 742230 Cortex-A9 1120 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1121 between two write operations may not ensure the correct visibility 1122 ordering of the two writes. This workaround sets a specific bit in 1123 the diagnostic register of the Cortex-A9 which causes the DMB 1124 instruction to behave as a DSB, ensuring the correct behaviour of 1125 the two writes. 1126 1127config ARM_ERRATA_742231 1128 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1129 depends on CPU_V7 && SMP 1130 help 1131 This option enables the workaround for the 742231 Cortex-A9 1132 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1133 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1134 accessing some data located in the same cache line, may get corrupted 1135 data due to bad handling of the address hazard when the line gets 1136 replaced from one of the CPUs at the same time as another CPU is 1137 accessing it. This workaround sets specific bits in the diagnostic 1138 register of the Cortex-A9 which reduces the linefill issuing 1139 capabilities of the processor. 1140 1141config PL310_ERRATA_588369 1142 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1143 depends on CACHE_L2X0 1144 help 1145 The PL310 L2 cache controller implements three types of Clean & 1146 Invalidate maintenance operations: by Physical Address 1147 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 1148 They are architecturally defined to behave as the execution of a 1149 clean operation followed immediately by an invalidate operation, 1150 both performing to the same memory location. This functionality 1151 is not correctly implemented in PL310 as clean lines are not 1152 invalidated as a result of these operations. 1153 1154config ARM_ERRATA_720789 1155 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1156 depends on CPU_V7 && SMP 1157 help 1158 This option enables the workaround for the 720789 Cortex-A9 (prior to 1159 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1160 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1161 As a consequence of this erratum, some TLB entries which should be 1162 invalidated are not, resulting in an incoherency in the system page 1163 tables. The workaround changes the TLB flushing routines to invalidate 1164 entries regardless of the ASID. 1165 1166config PL310_ERRATA_727915 1167 bool "Background Clean & Invalidate by Way operation can cause data corruption" 1168 depends on CACHE_L2X0 1169 help 1170 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1171 operation (offset 0x7FC). This operation runs in background so that 1172 PL310 can handle normal accesses while it is in progress. Under very 1173 rare circumstances, due to this erratum, write data can be lost when 1174 PL310 treats a cacheable write transaction during a Clean & 1175 Invalidate by Way operation. 1176 1177config ARM_ERRATA_743622 1178 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1179 depends on CPU_V7 1180 help 1181 This option enables the workaround for the 743622 Cortex-A9 1182 (r2p0..r2p2) erratum. Under very rare conditions, a faulty 1183 optimisation in the Cortex-A9 Store Buffer may lead to data 1184 corruption. This workaround sets a specific bit in the diagnostic 1185 register of the Cortex-A9 which disables the Store Buffer 1186 optimisation, preventing the defect from occurring. This has no 1187 visible impact on the overall performance or power consumption of the 1188 processor. 1189 1190config ARM_ERRATA_751472 1191 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1192 depends on CPU_V7 && SMP 1193 help 1194 This option enables the workaround for the 751472 Cortex-A9 (prior 1195 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1196 completion of a following broadcasted operation if the second 1197 operation is received by a CPU before the ICIALLUIS has completed, 1198 potentially leading to corrupted entries in the cache or TLB. 1199 1200config ARM_ERRATA_753970 1201 bool "ARM errata: cache sync operation may be faulty" 1202 depends on CACHE_PL310 1203 help 1204 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1205 1206 Under some condition the effect of cache sync operation on 1207 the store buffer still remains when the operation completes. 1208 This means that the store buffer is always asked to drain and 1209 this prevents it from merging any further writes. The workaround 1210 is to replace the normal offset of cache sync operation (0x730) 1211 by another offset targeting an unmapped PL310 register 0x740. 1212 This has the same effect as the cache sync operation: store buffer 1213 drain and waiting for all buffers empty. 1214 1215config ARM_ERRATA_754322 1216 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1217 depends on CPU_V7 1218 help 1219 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1220 r3p*) erratum. A speculative memory access may cause a page table walk 1221 which starts prior to an ASID switch but completes afterwards. This 1222 can populate the micro-TLB with a stale entry which may be hit with 1223 the new ASID. This workaround places two dsb instructions in the mm 1224 switching code so that no page table walks can cross the ASID switch. 1225 1226config ARM_ERRATA_754327 1227 bool "ARM errata: no automatic Store Buffer drain" 1228 depends on CPU_V7 && SMP 1229 help 1230 This option enables the workaround for the 754327 Cortex-A9 (prior to 1231 r2p0) erratum. The Store Buffer does not have any automatic draining 1232 mechanism and therefore a livelock may occur if an external agent 1233 continuously polls a memory location waiting to observe an update. 1234 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1235 written polling loops from denying visibility of updates to memory. 1236 1237endmenu 1238 1239source "arch/arm/common/Kconfig" 1240 1241menu "Bus support" 1242 1243config ARM_AMBA 1244 bool 1245 1246config ISA 1247 bool 1248 help 1249 Find out whether you have ISA slots on your motherboard. ISA is the 1250 name of a bus system, i.e. the way the CPU talks to the other stuff 1251 inside your box. Other bus systems are PCI, EISA, MicroChannel 1252 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1253 newer boards don't support it. If you have ISA, say Y, otherwise N. 1254 1255# Select ISA DMA controller support 1256config ISA_DMA 1257 bool 1258 select ISA_DMA_API 1259 1260# Select ISA DMA interface 1261config ISA_DMA_API 1262 bool 1263 1264config PCI 1265 bool "PCI support" if MIGHT_HAVE_PCI 1266 help 1267 Find out whether you have a PCI motherboard. PCI is the name of a 1268 bus system, i.e. the way the CPU talks to the other stuff inside 1269 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1270 VESA. If you have PCI, say Y, otherwise N. 1271 1272config PCI_DOMAINS 1273 bool 1274 depends on PCI 1275 1276config PCI_NANOENGINE 1277 bool "BSE nanoEngine PCI support" 1278 depends on SA1100_NANOENGINE 1279 help 1280 Enable PCI on the BSE nanoEngine board. 1281 1282config PCI_SYSCALL 1283 def_bool PCI 1284 1285# Select the host bridge type 1286config PCI_HOST_VIA82C505 1287 bool 1288 depends on PCI && ARCH_SHARK 1289 default y 1290 1291config PCI_HOST_ITE8152 1292 bool 1293 depends on PCI && MACH_ARMCORE 1294 default y 1295 select DMABOUNCE 1296 1297source "drivers/pci/Kconfig" 1298 1299source "drivers/pcmcia/Kconfig" 1300 1301endmenu 1302 1303menu "Kernel Features" 1304 1305source "kernel/time/Kconfig" 1306 1307config SMP 1308 bool "Symmetric Multi-Processing" 1309 depends on CPU_V6K || CPU_V7 1310 depends on GENERIC_CLOCKEVENTS 1311 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1312 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1313 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1314 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE 1315 select USE_GENERIC_SMP_HELPERS 1316 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1317 help 1318 This enables support for systems with more than one CPU. If you have 1319 a system with only one CPU, like most personal computers, say N. If 1320 you have a system with more than one CPU, say Y. 1321 1322 If you say N here, the kernel will run on single and multiprocessor 1323 machines, but will use only one CPU of a multiprocessor machine. If 1324 you say Y here, the kernel will run on many, but not all, single 1325 processor machines. On a single processor machine, the kernel will 1326 run faster if you say N here. 1327 1328 See also <file:Documentation/i386/IO-APIC.txt>, 1329 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1330 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1331 1332 If you don't know what to do here, say N. 1333 1334config SMP_ON_UP 1335 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" 1336 depends on EXPERIMENTAL 1337 depends on SMP && !XIP_KERNEL 1338 default y 1339 help 1340 SMP kernels contain instructions which fail on non-SMP processors. 1341 Enabling this option allows the kernel to modify itself to make 1342 these instructions safe. Disabling it allows about 1K of space 1343 savings. 1344 1345 If you don't know what to do here, say Y. 1346 1347config HAVE_ARM_SCU 1348 bool 1349 depends on SMP 1350 help 1351 This option enables support for the ARM system coherency unit 1352 1353config HAVE_ARM_TWD 1354 bool 1355 depends on SMP 1356 select TICK_ONESHOT 1357 help 1358 This options enables support for the ARM timer and watchdog unit 1359 1360choice 1361 prompt "Memory split" 1362 default VMSPLIT_3G 1363 help 1364 Select the desired split between kernel and user memory. 1365 1366 If you are not absolutely sure what you are doing, leave this 1367 option alone! 1368 1369 config VMSPLIT_3G 1370 bool "3G/1G user/kernel split" 1371 config VMSPLIT_2G 1372 bool "2G/2G user/kernel split" 1373 config VMSPLIT_1G 1374 bool "1G/3G user/kernel split" 1375endchoice 1376 1377config PAGE_OFFSET 1378 hex 1379 default 0x40000000 if VMSPLIT_1G 1380 default 0x80000000 if VMSPLIT_2G 1381 default 0xC0000000 1382 1383config NR_CPUS 1384 int "Maximum number of CPUs (2-32)" 1385 range 2 32 1386 depends on SMP 1387 default "4" 1388 1389config HOTPLUG_CPU 1390 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" 1391 depends on SMP && HOTPLUG && EXPERIMENTAL 1392 help 1393 Say Y here to experiment with turning CPUs off and on. CPUs 1394 can be controlled through /sys/devices/system/cpu. 1395 1396config LOCAL_TIMERS 1397 bool "Use local timer interrupts" 1398 depends on SMP 1399 default y 1400 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) 1401 help 1402 Enable support for local timers on SMP platforms, rather then the 1403 legacy IPI broadcast method. Local timers allows the system 1404 accounting to be spread across the timer interval, preventing a 1405 "thundering herd" at every timer tick. 1406 1407source kernel/Kconfig.preempt 1408 1409config HZ 1410 int 1411 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1412 ARCH_S5PV210 || ARCH_EXYNOS4 1413 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1414 default AT91_TIMER_HZ if ARCH_AT91 1415 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1416 default 100 1417 1418config THUMB2_KERNEL 1419 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" 1420 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL 1421 select AEABI 1422 select ARM_ASM_UNIFIED 1423 help 1424 By enabling this option, the kernel will be compiled in 1425 Thumb-2 mode. A compiler/assembler that understand the unified 1426 ARM-Thumb syntax is needed. 1427 1428 If unsure, say N. 1429 1430config THUMB2_AVOID_R_ARM_THM_JUMP11 1431 bool "Work around buggy Thumb-2 short branch relocations in gas" 1432 depends on THUMB2_KERNEL && MODULES 1433 default y 1434 help 1435 Various binutils versions can resolve Thumb-2 branches to 1436 locally-defined, preemptible global symbols as short-range "b.n" 1437 branch instructions. 1438 1439 This is a problem, because there's no guarantee the final 1440 destination of the symbol, or any candidate locations for a 1441 trampoline, are within range of the branch. For this reason, the 1442 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1443 relocation in modules at all, and it makes little sense to add 1444 support. 1445 1446 The symptom is that the kernel fails with an "unsupported 1447 relocation" error when loading some modules. 1448 1449 Until fixed tools are available, passing 1450 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1451 code which hits this problem, at the cost of a bit of extra runtime 1452 stack usage in some cases. 1453 1454 The problem is described in more detail at: 1455 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1456 1457 Only Thumb-2 kernels are affected. 1458 1459 Unless you are sure your tools don't have this problem, say Y. 1460 1461config ARM_ASM_UNIFIED 1462 bool 1463 1464config AEABI 1465 bool "Use the ARM EABI to compile the kernel" 1466 help 1467 This option allows for the kernel to be compiled using the latest 1468 ARM ABI (aka EABI). This is only useful if you are using a user 1469 space environment that is also compiled with EABI. 1470 1471 Since there are major incompatibilities between the legacy ABI and 1472 EABI, especially with regard to structure member alignment, this 1473 option also changes the kernel syscall calling convention to 1474 disambiguate both ABIs and allow for backward compatibility support 1475 (selected with CONFIG_OABI_COMPAT). 1476 1477 To use this you need GCC version 4.0.0 or later. 1478 1479config OABI_COMPAT 1480 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1481 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL 1482 default y 1483 help 1484 This option preserves the old syscall interface along with the 1485 new (ARM EABI) one. It also provides a compatibility layer to 1486 intercept syscalls that have structure arguments which layout 1487 in memory differs between the legacy ABI and the new ARM EABI 1488 (only for non "thumb" binaries). This option adds a tiny 1489 overhead to all syscalls and produces a slightly larger kernel. 1490 If you know you'll be using only pure EABI user space then you 1491 can say N here. If this option is not selected and you attempt 1492 to execute a legacy ABI binary then the result will be 1493 UNPREDICTABLE (in fact it can be predicted that it won't work 1494 at all). If in doubt say Y. 1495 1496config ARCH_HAS_HOLES_MEMORYMODEL 1497 bool 1498 1499config ARCH_SPARSEMEM_ENABLE 1500 bool 1501 1502config ARCH_SPARSEMEM_DEFAULT 1503 def_bool ARCH_SPARSEMEM_ENABLE 1504 1505config ARCH_SELECT_MEMORY_MODEL 1506 def_bool ARCH_SPARSEMEM_ENABLE 1507 1508config HAVE_ARCH_PFN_VALID 1509 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1510 1511config HIGHMEM 1512 bool "High Memory Support" 1513 depends on MMU 1514 help 1515 The address space of ARM processors is only 4 Gigabytes large 1516 and it has to accommodate user address space, kernel address 1517 space as well as some memory mapped IO. That means that, if you 1518 have a large amount of physical memory and/or IO, not all of the 1519 memory can be "permanently mapped" by the kernel. The physical 1520 memory that is not permanently mapped is called "high memory". 1521 1522 Depending on the selected kernel/user memory split, minimum 1523 vmalloc space and actual amount of RAM, you may not need this 1524 option which should result in a slightly faster kernel. 1525 1526 If unsure, say n. 1527 1528config HIGHPTE 1529 bool "Allocate 2nd-level pagetables from highmem" 1530 depends on HIGHMEM 1531 1532config HW_PERF_EVENTS 1533 bool "Enable hardware performance counter support for perf events" 1534 depends on PERF_EVENTS && CPU_HAS_PMU 1535 default y 1536 help 1537 Enable hardware performance counter support for perf events. If 1538 disabled, perf events will use software events only. 1539 1540source "mm/Kconfig" 1541 1542config FORCE_MAX_ZONEORDER 1543 int "Maximum zone order" if ARCH_SHMOBILE 1544 range 11 64 if ARCH_SHMOBILE 1545 default "9" if SA1111 1546 default "11" 1547 help 1548 The kernel memory allocator divides physically contiguous memory 1549 blocks into "zones", where each zone is a power of two number of 1550 pages. This option selects the largest power of two that the kernel 1551 keeps in the memory allocator. If you need to allocate very large 1552 blocks of physically contiguous memory, then you may need to 1553 increase this value. 1554 1555 This config option is actually maximum order plus one. For example, 1556 a value of 11 means that the largest free memory block is 2^10 pages. 1557 1558config LEDS 1559 bool "Timer and CPU usage LEDs" 1560 depends on ARCH_CDB89712 || ARCH_EBSA110 || \ 1561 ARCH_EBSA285 || ARCH_INTEGRATOR || \ 1562 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 1563 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 1564 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 1565 ARCH_AT91 || ARCH_DAVINCI || \ 1566 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW 1567 help 1568 If you say Y here, the LEDs on your machine will be used 1569 to provide useful information about your current system status. 1570 1571 If you are compiling a kernel for a NetWinder or EBSA-285, you will 1572 be able to select which LEDs are active using the options below. If 1573 you are compiling a kernel for the EBSA-110 or the LART however, the 1574 red LED will simply flash regularly to indicate that the system is 1575 still functional. It is safe to say Y here if you have a CATS 1576 system, but the driver will do nothing. 1577 1578config LEDS_TIMER 1579 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ 1580 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1581 || MACH_OMAP_PERSEUS2 1582 depends on LEDS 1583 depends on !GENERIC_CLOCKEVENTS 1584 default y if ARCH_EBSA110 1585 help 1586 If you say Y here, one of the system LEDs (the green one on the 1587 NetWinder, the amber one on the EBSA285, or the red one on the LART) 1588 will flash regularly to indicate that the system is still 1589 operational. This is mainly useful to kernel hackers who are 1590 debugging unstable kernels. 1591 1592 The LART uses the same LED for both Timer LED and CPU usage LED 1593 functions. You may choose to use both, but the Timer LED function 1594 will overrule the CPU usage LED. 1595 1596config LEDS_CPU 1597 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ 1598 !ARCH_OMAP) \ 1599 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ 1600 || MACH_OMAP_PERSEUS2 1601 depends on LEDS 1602 help 1603 If you say Y here, the red LED will be used to give a good real 1604 time indication of CPU usage, by lighting whenever the idle task 1605 is not currently executing. 1606 1607 The LART uses the same LED for both Timer LED and CPU usage LED 1608 functions. You may choose to use both, but the Timer LED function 1609 will overrule the CPU usage LED. 1610 1611config ALIGNMENT_TRAP 1612 bool 1613 depends on CPU_CP15_MMU 1614 default y if !ARCH_EBSA110 1615 select HAVE_PROC_CPU if PROC_FS 1616 help 1617 ARM processors cannot fetch/store information which is not 1618 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1619 address divisible by 4. On 32-bit ARM processors, these non-aligned 1620 fetch/store instructions will be emulated in software if you say 1621 here, which has a severe performance impact. This is necessary for 1622 correct operation of some network protocols. With an IP-only 1623 configuration it is safe to say N, otherwise say Y. 1624 1625config UACCESS_WITH_MEMCPY 1626 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)" 1627 depends on MMU && EXPERIMENTAL 1628 default y if CPU_FEROCEON 1629 help 1630 Implement faster copy_to_user and clear_user methods for CPU 1631 cores where a 8-word STM instruction give significantly higher 1632 memory write throughput than a sequence of individual 32bit stores. 1633 1634 A possible side effect is a slight increase in scheduling latency 1635 between threads sharing the same address space if they invoke 1636 such copy operations with large buffers. 1637 1638 However, if the CPU data cache is using a write-allocate mode, 1639 this option is unlikely to provide any performance gain. 1640 1641config SECCOMP 1642 bool 1643 prompt "Enable seccomp to safely compute untrusted bytecode" 1644 ---help--- 1645 This kernel feature is useful for number crunching applications 1646 that may need to compute untrusted bytecode during their 1647 execution. By using pipes or other transports made available to 1648 the process as file descriptors supporting the read/write 1649 syscalls, it's possible to isolate those applications in 1650 their own address space using seccomp. Once seccomp is 1651 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1652 and the task is only allowed to execute a few safe syscalls 1653 defined by each seccomp mode. 1654 1655config CC_STACKPROTECTOR 1656 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1657 depends on EXPERIMENTAL 1658 help 1659 This option turns on the -fstack-protector GCC feature. This 1660 feature puts, at the beginning of functions, a canary value on 1661 the stack just before the return address, and validates 1662 the value just before actually returning. Stack based buffer 1663 overflows (that need to overwrite this return address) now also 1664 overwrite the canary, which gets detected and the attack is then 1665 neutralized via a kernel panic. 1666 This feature requires gcc version 4.2 or above. 1667 1668config DEPRECATED_PARAM_STRUCT 1669 bool "Provide old way to pass kernel parameters" 1670 help 1671 This was deprecated in 2001 and announced to live on for 5 years. 1672 Some old boot loaders still use this way. 1673 1674endmenu 1675 1676menu "Boot options" 1677 1678config USE_OF 1679 bool "Flattened Device Tree support" 1680 select OF 1681 select OF_EARLY_FLATTREE 1682 help 1683 Include support for flattened device tree machine descriptions. 1684 1685# Compressed boot loader in ROM. Yes, we really want to ask about 1686# TEXT and BSS so we preserve their values in the config files. 1687config ZBOOT_ROM_TEXT 1688 hex "Compressed ROM boot loader base address" 1689 default "0" 1690 help 1691 The physical address at which the ROM-able zImage is to be 1692 placed in the target. Platforms which normally make use of 1693 ROM-able zImage formats normally set this to a suitable 1694 value in their defconfig file. 1695 1696 If ZBOOT_ROM is not enabled, this has no effect. 1697 1698config ZBOOT_ROM_BSS 1699 hex "Compressed ROM boot loader BSS address" 1700 default "0" 1701 help 1702 The base address of an area of read/write memory in the target 1703 for the ROM-able zImage which must be available while the 1704 decompressor is running. It must be large enough to hold the 1705 entire decompressed kernel plus an additional 128 KiB. 1706 Platforms which normally make use of ROM-able zImage formats 1707 normally set this to a suitable value in their defconfig file. 1708 1709 If ZBOOT_ROM is not enabled, this has no effect. 1710 1711config ZBOOT_ROM 1712 bool "Compressed boot loader in ROM/flash" 1713 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1714 help 1715 Say Y here if you intend to execute your compressed kernel image 1716 (zImage) directly from ROM or flash. If unsure, say N. 1717 1718config ZBOOT_ROM_MMCIF 1719 bool "Include MMCIF loader in zImage (EXPERIMENTAL)" 1720 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL 1721 help 1722 Say Y here to include experimental MMCIF loading code in the 1723 ROM-able zImage. With this enabled it is possible to write the 1724 the ROM-able zImage kernel image to an MMC card and boot the 1725 kernel straight from the reset vector. At reset the processor 1726 Mask ROM will load the first part of the the ROM-able zImage 1727 which in turn loads the rest the kernel image to RAM using the 1728 MMCIF hardware block. 1729 1730config CMDLINE 1731 string "Default kernel command string" 1732 default "" 1733 help 1734 On some architectures (EBSA110 and CATS), there is currently no way 1735 for the boot loader to pass arguments to the kernel. For these 1736 architectures, you should supply some command-line options at build 1737 time by entering them here. As a minimum, you should specify the 1738 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1739 1740choice 1741 prompt "Kernel command line type" if CMDLINE != "" 1742 default CMDLINE_FROM_BOOTLOADER 1743 1744config CMDLINE_FROM_BOOTLOADER 1745 bool "Use bootloader kernel arguments if available" 1746 help 1747 Uses the command-line options passed by the boot loader. If 1748 the boot loader doesn't provide any, the default kernel command 1749 string provided in CMDLINE will be used. 1750 1751config CMDLINE_EXTEND 1752 bool "Extend bootloader kernel arguments" 1753 help 1754 The command-line arguments provided by the boot loader will be 1755 appended to the default kernel command string. 1756 1757config CMDLINE_FORCE 1758 bool "Always use the default kernel command string" 1759 help 1760 Always use the default kernel command string, even if the boot 1761 loader passes other arguments to the kernel. 1762 This is useful if you cannot or don't want to change the 1763 command-line options your boot loader passes to the kernel. 1764endchoice 1765 1766config XIP_KERNEL 1767 bool "Kernel Execute-In-Place from ROM" 1768 depends on !ZBOOT_ROM 1769 help 1770 Execute-In-Place allows the kernel to run from non-volatile storage 1771 directly addressable by the CPU, such as NOR flash. This saves RAM 1772 space since the text section of the kernel is not loaded from flash 1773 to RAM. Read-write sections, such as the data section and stack, 1774 are still copied to RAM. The XIP kernel is not compressed since 1775 it has to run directly from flash, so it will take more space to 1776 store it. The flash address used to link the kernel object files, 1777 and for storing it, is configuration dependent. Therefore, if you 1778 say Y here, you must know the proper physical address where to 1779 store the kernel image depending on your own flash memory usage. 1780 1781 Also note that the make target becomes "make xipImage" rather than 1782 "make zImage" or "make Image". The final kernel binary to put in 1783 ROM memory will be arch/arm/boot/xipImage. 1784 1785 If unsure, say N. 1786 1787config XIP_PHYS_ADDR 1788 hex "XIP Kernel Physical Location" 1789 depends on XIP_KERNEL 1790 default "0x00080000" 1791 help 1792 This is the physical address in your flash memory the kernel will 1793 be linked for and stored to. This address is dependent on your 1794 own flash usage. 1795 1796config KEXEC 1797 bool "Kexec system call (EXPERIMENTAL)" 1798 depends on EXPERIMENTAL 1799 help 1800 kexec is a system call that implements the ability to shutdown your 1801 current kernel, and to start another kernel. It is like a reboot 1802 but it is independent of the system firmware. And like a reboot 1803 you can start any kernel with it, not just Linux. 1804 1805 It is an ongoing process to be certain the hardware in a machine 1806 is properly shutdown, so do not be surprised if this code does not 1807 initially work for you. It may help to enable device hotplugging 1808 support. 1809 1810config ATAGS_PROC 1811 bool "Export atags in procfs" 1812 depends on KEXEC 1813 default y 1814 help 1815 Should the atags used to boot the kernel be exported in an "atags" 1816 file in procfs. Useful with kexec. 1817 1818config CRASH_DUMP 1819 bool "Build kdump crash kernel (EXPERIMENTAL)" 1820 depends on EXPERIMENTAL 1821 help 1822 Generate crash dump after being started by kexec. This should 1823 be normally only set in special crash dump kernels which are 1824 loaded in the main kernel with kexec-tools into a specially 1825 reserved region and then later executed after a crash by 1826 kdump/kexec. The crash dump kernel must be compiled to a 1827 memory address not used by the main kernel 1828 1829 For more details see Documentation/kdump/kdump.txt 1830 1831config AUTO_ZRELADDR 1832 bool "Auto calculation of the decompressed kernel image address" 1833 depends on !ZBOOT_ROM && !ARCH_U300 1834 help 1835 ZRELADDR is the physical address where the decompressed kernel 1836 image will be placed. If AUTO_ZRELADDR is selected, the address 1837 will be determined at run-time by masking the current IP with 1838 0xf8000000. This assumes the zImage being placed in the first 128MB 1839 from start of memory. 1840 1841endmenu 1842 1843menu "CPU Power Management" 1844 1845if ARCH_HAS_CPUFREQ 1846 1847source "drivers/cpufreq/Kconfig" 1848 1849config CPU_FREQ_IMX 1850 tristate "CPUfreq driver for i.MX CPUs" 1851 depends on ARCH_MXC && CPU_FREQ 1852 help 1853 This enables the CPUfreq driver for i.MX CPUs. 1854 1855config CPU_FREQ_SA1100 1856 bool 1857 1858config CPU_FREQ_SA1110 1859 bool 1860 1861config CPU_FREQ_INTEGRATOR 1862 tristate "CPUfreq driver for ARM Integrator CPUs" 1863 depends on ARCH_INTEGRATOR && CPU_FREQ 1864 default y 1865 help 1866 This enables the CPUfreq driver for ARM Integrator CPUs. 1867 1868 For details, take a look at <file:Documentation/cpu-freq>. 1869 1870 If in doubt, say Y. 1871 1872config CPU_FREQ_PXA 1873 bool 1874 depends on CPU_FREQ && ARCH_PXA && PXA25x 1875 default y 1876 select CPU_FREQ_DEFAULT_GOV_USERSPACE 1877 1878config CPU_FREQ_S3C64XX 1879 bool "CPUfreq support for Samsung S3C64XX CPUs" 1880 depends on CPU_FREQ && CPU_S3C6410 1881 1882config CPU_FREQ_S3C 1883 bool 1884 help 1885 Internal configuration node for common cpufreq on Samsung SoC 1886 1887config CPU_FREQ_S3C24XX 1888 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" 1889 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL 1890 select CPU_FREQ_S3C 1891 help 1892 This enables the CPUfreq driver for the Samsung S3C24XX family 1893 of CPUs. 1894 1895 For details, take a look at <file:Documentation/cpu-freq>. 1896 1897 If in doubt, say N. 1898 1899config CPU_FREQ_S3C24XX_PLL 1900 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" 1901 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL 1902 help 1903 Compile in support for changing the PLL frequency from the 1904 S3C24XX series CPUfreq driver. The PLL takes time to settle 1905 after a frequency change, so by default it is not enabled. 1906 1907 This also means that the PLL tables for the selected CPU(s) will 1908 be built which may increase the size of the kernel image. 1909 1910config CPU_FREQ_S3C24XX_DEBUG 1911 bool "Debug CPUfreq Samsung driver core" 1912 depends on CPU_FREQ_S3C24XX 1913 help 1914 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core 1915 1916config CPU_FREQ_S3C24XX_IODEBUG 1917 bool "Debug CPUfreq Samsung driver IO timing" 1918 depends on CPU_FREQ_S3C24XX 1919 help 1920 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core 1921 1922config CPU_FREQ_S3C24XX_DEBUGFS 1923 bool "Export debugfs for CPUFreq" 1924 depends on CPU_FREQ_S3C24XX && DEBUG_FS 1925 help 1926 Export status information via debugfs. 1927 1928endif 1929 1930source "drivers/cpuidle/Kconfig" 1931 1932endmenu 1933 1934menu "Floating point emulation" 1935 1936comment "At least one emulation must be selected" 1937 1938config FPE_NWFPE 1939 bool "NWFPE math emulation" 1940 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1941 ---help--- 1942 Say Y to include the NWFPE floating point emulator in the kernel. 1943 This is necessary to run most binaries. Linux does not currently 1944 support floating point hardware so you need to say Y here even if 1945 your machine has an FPA or floating point co-processor podule. 1946 1947 You may say N here if you are going to load the Acorn FPEmulator 1948 early in the bootup. 1949 1950config FPE_NWFPE_XP 1951 bool "Support extended precision" 1952 depends on FPE_NWFPE 1953 help 1954 Say Y to include 80-bit support in the kernel floating-point 1955 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1956 Note that gcc does not generate 80-bit operations by default, 1957 so in most cases this option only enlarges the size of the 1958 floating point emulator without any good reason. 1959 1960 You almost surely want to say N here. 1961 1962config FPE_FASTFPE 1963 bool "FastFPE math emulation (EXPERIMENTAL)" 1964 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL 1965 ---help--- 1966 Say Y here to include the FAST floating point emulator in the kernel. 1967 This is an experimental much faster emulator which now also has full 1968 precision for the mantissa. It does not support any exceptions. 1969 It is very simple, and approximately 3-6 times faster than NWFPE. 1970 1971 It should be sufficient for most programs. It may be not suitable 1972 for scientific calculations, but you have to check this for yourself. 1973 If you do not feel you need a faster FP emulation you should better 1974 choose NWFPE. 1975 1976config VFP 1977 bool "VFP-format floating point maths" 1978 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1979 help 1980 Say Y to include VFP support code in the kernel. This is needed 1981 if your hardware includes a VFP unit. 1982 1983 Please see <file:Documentation/arm/VFP/release-notes.txt> for 1984 release notes and additional status information. 1985 1986 Say N if your target does not have VFP hardware. 1987 1988config VFPv3 1989 bool 1990 depends on VFP 1991 default y if CPU_V7 1992 1993config NEON 1994 bool "Advanced SIMD (NEON) Extension support" 1995 depends on VFPv3 && CPU_V7 1996 help 1997 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1998 Extension. 1999 2000endmenu 2001 2002menu "Userspace binary formats" 2003 2004source "fs/Kconfig.binfmt" 2005 2006config ARTHUR 2007 tristate "RISC OS personality" 2008 depends on !AEABI 2009 help 2010 Say Y here to include the kernel code necessary if you want to run 2011 Acorn RISC OS/Arthur binaries under Linux. This code is still very 2012 experimental; if this sounds frightening, say N and sleep in peace. 2013 You can also say M here to compile this support as a module (which 2014 will be called arthur). 2015 2016endmenu 2017 2018menu "Power management options" 2019 2020source "kernel/power/Kconfig" 2021 2022config ARCH_SUSPEND_POSSIBLE 2023 depends on !ARCH_S5P64X0 && !ARCH_S5PC100 2024 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2025 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2026 def_bool y 2027 2028endmenu 2029 2030source "net/Kconfig" 2031 2032source "drivers/Kconfig" 2033 2034source "fs/Kconfig" 2035 2036source "arch/arm/Kconfig.debug" 2037 2038source "security/Kconfig" 2039 2040source "crypto/Kconfig" 2041 2042source "lib/Kconfig" 2043