1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 15 select ARCH_HAS_PHYS_TO_DMA 16 select ARCH_HAS_SETUP_DMA_OPS 17 select ARCH_HAS_SET_MEMORY 18 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 19 select ARCH_HAS_STRICT_MODULE_RWX if MMU 20 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 22 select ARCH_HAVE_CUSTOM_GPIO_H 23 select ARCH_HAS_GCOV_PROFILE_ALL 24 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 25 select ARCH_MIGHT_HAVE_PC_PARPORT 26 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 27 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 28 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 29 select ARCH_SUPPORTS_ATOMIC_RMW 30 select ARCH_USE_BUILTIN_BSWAP 31 select ARCH_USE_CMPXCHG_LOCKREF 32 select ARCH_WANT_IPC_PARSE_VERSION 33 select BUILDTIME_EXTABLE_SORT if MMU 34 select CLONE_BACKWARDS 35 select CPU_PM if SUSPEND || CPU_IDLE 36 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 37 select DMA_DECLARE_COHERENT 38 select DMA_REMAP if MMU 39 select EDAC_SUPPORT 40 select EDAC_ATOMIC_SCRUB 41 select GENERIC_ALLOCATOR 42 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 43 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 44 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 45 select GENERIC_CPU_AUTOPROBE 46 select GENERIC_EARLY_IOREMAP 47 select GENERIC_IDLE_POLL_SETUP 48 select GENERIC_IRQ_PROBE 49 select GENERIC_IRQ_SHOW 50 select GENERIC_IRQ_SHOW_LEVEL 51 select GENERIC_PCI_IOMAP 52 select GENERIC_SCHED_CLOCK 53 select GENERIC_SMP_IDLE_THREAD 54 select GENERIC_STRNCPY_FROM_USER 55 select GENERIC_STRNLEN_USER 56 select HANDLE_DOMAIN_IRQ 57 select HARDIRQS_SW_RESEND 58 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 59 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 60 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 61 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 62 select HAVE_ARCH_MMAP_RND_BITS if MMU 63 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 64 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 65 select HAVE_ARCH_TRACEHOOK 66 select HAVE_ARM_SMCCC if CPU_V7 67 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 68 select HAVE_CONTEXT_TRACKING 69 select HAVE_C_RECORDMCOUNT 70 select HAVE_DEBUG_KMEMLEAK 71 select HAVE_DMA_CONTIGUOUS if MMU 72 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 74 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 75 select HAVE_EXIT_THREAD 76 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 77 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 78 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 79 select HAVE_GCC_PLUGINS 80 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 81 select HAVE_IDE if PCI || ISA || PCMCIA 82 select HAVE_IRQ_TIME_ACCOUNTING 83 select HAVE_KERNEL_GZIP 84 select HAVE_KERNEL_LZ4 85 select HAVE_KERNEL_LZMA 86 select HAVE_KERNEL_LZO 87 select HAVE_KERNEL_XZ 88 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 89 select HAVE_KRETPROBES if HAVE_KPROBES 90 select HAVE_MOD_ARCH_SPECIFIC 91 select HAVE_NMI 92 select HAVE_OPROFILE if HAVE_PERF_EVENTS 93 select HAVE_OPTPROBES if !THUMB2_KERNEL 94 select HAVE_PERF_EVENTS 95 select HAVE_PERF_REGS 96 select HAVE_PERF_USER_STACK_DUMP 97 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 98 select HAVE_REGS_AND_STACK_ACCESS_API 99 select HAVE_RSEQ 100 select HAVE_STACKPROTECTOR 101 select HAVE_SYSCALL_TRACEPOINTS 102 select HAVE_UID16 103 select HAVE_VIRT_CPU_ACCOUNTING_GEN 104 select IRQ_FORCED_THREADING 105 select MODULES_USE_ELF_REL 106 select NEED_DMA_MAP_STATE 107 select OF_EARLY_FLATTREE if OF 108 select OLD_SIGACTION 109 select OLD_SIGSUSPEND3 110 select PCI_SYSCALL if PCI 111 select PERF_USE_VMALLOC 112 select REFCOUNT_FULL 113 select RTC_LIB 114 select SYS_SUPPORTS_APM_EMULATION 115 # Above selects are sorted alphabetically; please add new ones 116 # according to that. Thanks. 117 help 118 The ARM series is a line of low-power-consumption RISC chip designs 119 licensed by ARM Ltd and targeted at embedded applications and 120 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 121 manufactured, but legacy ARM-based PC hardware remains popular in 122 Europe. There is an ARM Linux project with a web page at 123 <http://www.arm.linux.org.uk/>. 124 125config ARM_HAS_SG_CHAIN 126 bool 127 128config ARM_DMA_USE_IOMMU 129 bool 130 select ARM_HAS_SG_CHAIN 131 select NEED_SG_DMA_LENGTH 132 133if ARM_DMA_USE_IOMMU 134 135config ARM_DMA_IOMMU_ALIGNMENT 136 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 137 range 4 9 138 default 8 139 help 140 DMA mapping framework by default aligns all buffers to the smallest 141 PAGE_SIZE order which is greater than or equal to the requested buffer 142 size. This works well for buffers up to a few hundreds kilobytes, but 143 for larger buffers it just a waste of address space. Drivers which has 144 relatively small addressing window (like 64Mib) might run out of 145 virtual space with just a few allocations. 146 147 With this parameter you can specify the maximum PAGE_SIZE order for 148 DMA IOMMU buffers. Larger buffers will be aligned only to this 149 specified order. The order is expressed as a power of two multiplied 150 by the PAGE_SIZE. 151 152endif 153 154config SYS_SUPPORTS_APM_EMULATION 155 bool 156 157config HAVE_TCM 158 bool 159 select GENERIC_ALLOCATOR 160 161config HAVE_PROC_CPU 162 bool 163 164config NO_IOPORT_MAP 165 bool 166 167config SBUS 168 bool 169 170config STACKTRACE_SUPPORT 171 bool 172 default y 173 174config LOCKDEP_SUPPORT 175 bool 176 default y 177 178config TRACE_IRQFLAGS_SUPPORT 179 bool 180 default !CPU_V7M 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config ARCH_SUPPORTS_UPROBES 209 def_bool y 210 211config ARCH_HAS_DMA_SET_COHERENT_MASK 212 bool 213 214config GENERIC_ISA_DMA 215 bool 216 217config FIQ 218 bool 219 220config NEED_RET_TO_USER 221 bool 222 223config ARCH_MTD_XIP 224 bool 225 226config ARM_PATCH_PHYS_VIRT 227 bool "Patch physical to virtual translations at runtime" if EMBEDDED 228 default y 229 depends on !XIP_KERNEL && MMU 230 help 231 Patch phys-to-virt and virt-to-phys translation functions at 232 boot and module load time according to the position of the 233 kernel in system memory. 234 235 This can only be used with non-XIP MMU kernels where the base 236 of physical memory is at a 16MB boundary. 237 238 Only disable this option if you know that you do not require 239 this feature (eg, building a kernel for a single machine) and 240 you need to shrink the kernel to the minimal size. 241 242config NEED_MACH_IO_H 243 bool 244 help 245 Select this when mach/io.h is required to provide special 246 definitions for this platform. The need for mach/io.h should 247 be avoided when possible. 248 249config NEED_MACH_MEMORY_H 250 bool 251 help 252 Select this when mach/memory.h is required to provide special 253 definitions for this platform. The need for mach/memory.h should 254 be avoided when possible. 255 256config PHYS_OFFSET 257 hex "Physical address of main memory" if MMU 258 depends on !ARM_PATCH_PHYS_VIRT 259 default DRAM_BASE if !MMU 260 default 0x00000000 if ARCH_EBSA110 || \ 261 ARCH_FOOTBRIDGE || \ 262 ARCH_INTEGRATOR || \ 263 ARCH_IOP13XX || \ 264 ARCH_KS8695 || \ 265 ARCH_REALVIEW 266 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 267 default 0x20000000 if ARCH_S5PV210 268 default 0xc0000000 if ARCH_SA1100 269 help 270 Please provide the physical address corresponding to the 271 location of main memory in your system. 272 273config GENERIC_BUG 274 def_bool y 275 depends on BUG 276 277config PGTABLE_LEVELS 278 int 279 default 3 if ARM_LPAE 280 default 2 281 282menu "System Type" 283 284config MMU 285 bool "MMU-based Paged Memory Management Support" 286 default y 287 help 288 Select if you want MMU-based virtualised addressing space 289 support by paged memory management. If unsure, say 'Y'. 290 291config ARCH_MMAP_RND_BITS_MIN 292 default 8 293 294config ARCH_MMAP_RND_BITS_MAX 295 default 14 if PAGE_OFFSET=0x40000000 296 default 15 if PAGE_OFFSET=0x80000000 297 default 16 298 299# 300# The "ARM system type" choice list is ordered alphabetically by option 301# text. Please add new entries in the option alphabetic order. 302# 303choice 304 prompt "ARM system type" 305 default ARM_SINGLE_ARMV7M if !MMU 306 default ARCH_MULTIPLATFORM if MMU 307 308config ARCH_MULTIPLATFORM 309 bool "Allow multiple platforms to be selected" 310 depends on MMU 311 select ARM_HAS_SG_CHAIN 312 select ARM_PATCH_PHYS_VIRT 313 select AUTO_ZRELADDR 314 select TIMER_OF 315 select COMMON_CLK 316 select GENERIC_CLOCKEVENTS 317 select GENERIC_IRQ_MULTI_HANDLER 318 select HAVE_PCI 319 select PCI_DOMAINS_GENERIC if PCI 320 select SPARSE_IRQ 321 select USE_OF 322 323config ARM_SINGLE_ARMV7M 324 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 325 depends on !MMU 326 select ARM_NVIC 327 select AUTO_ZRELADDR 328 select TIMER_OF 329 select COMMON_CLK 330 select CPU_V7M 331 select GENERIC_CLOCKEVENTS 332 select NO_IOPORT_MAP 333 select SPARSE_IRQ 334 select USE_OF 335 336config ARCH_EBSA110 337 bool "EBSA-110" 338 select ARCH_USES_GETTIMEOFFSET 339 select CPU_SA110 340 select ISA 341 select NEED_MACH_IO_H 342 select NEED_MACH_MEMORY_H 343 select NO_IOPORT_MAP 344 help 345 This is an evaluation board for the StrongARM processor available 346 from Digital. It has limited hardware on-board, including an 347 Ethernet interface, two PCMCIA sockets, two serial ports and a 348 parallel port. 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKDEV_LOOKUP 358 select CLKSRC_MMIO 359 select CPU_ARM920T 360 select GENERIC_CLOCKEVENTS 361 select GPIOLIB 362 help 363 This enables support for the Cirrus EP93xx series of CPUs. 364 365config ARCH_FOOTBRIDGE 366 bool "FootBridge" 367 select CPU_SA110 368 select FOOTBRIDGE 369 select GENERIC_CLOCKEVENTS 370 select HAVE_IDE 371 select NEED_MACH_IO_H if !MMU 372 select NEED_MACH_MEMORY_H 373 help 374 Support for systems based on the DC21285 companion chip 375 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 376 377config ARCH_IOP13XX 378 bool "IOP13xx-based" 379 depends on MMU 380 select CPU_XSC3 381 select NEED_MACH_MEMORY_H 382 select NEED_RET_TO_USER 383 select FORCE_PCI 384 select PLAT_IOP 385 select VMSPLIT_1G 386 select SPARSE_IRQ 387 help 388 Support for Intel's IOP13XX (XScale) family of processors. 389 390config ARCH_IOP32X 391 bool "IOP32x-based" 392 depends on MMU 393 select CPU_XSCALE 394 select GPIO_IOP 395 select GPIOLIB 396 select NEED_RET_TO_USER 397 select FORCE_PCI 398 select PLAT_IOP 399 help 400 Support for Intel's 80219 and IOP32X (XScale) family of 401 processors. 402 403config ARCH_IOP33X 404 bool "IOP33x-based" 405 depends on MMU 406 select CPU_XSCALE 407 select GPIO_IOP 408 select GPIOLIB 409 select NEED_RET_TO_USER 410 select FORCE_PCI 411 select PLAT_IOP 412 help 413 Support for Intel's IOP33X (XScale) family of processors. 414 415config ARCH_IXP4XX 416 bool "IXP4xx-based" 417 depends on MMU 418 select ARCH_HAS_DMA_SET_COHERENT_MASK 419 select ARCH_SUPPORTS_BIG_ENDIAN 420 select CPU_XSCALE 421 select DMABOUNCE if PCI 422 select GENERIC_CLOCKEVENTS 423 select GENERIC_IRQ_MULTI_HANDLER 424 select GPIO_IXP4XX 425 select GPIOLIB 426 select HAVE_PCI 427 select IXP4XX_IRQ 428 select IXP4XX_TIMER 429 select NEED_MACH_IO_H 430 select USB_EHCI_BIG_ENDIAN_DESC 431 select USB_EHCI_BIG_ENDIAN_MMIO 432 help 433 Support for Intel's IXP4XX (XScale) family of processors. 434 435config ARCH_DOVE 436 bool "Marvell Dove" 437 select CPU_PJ4 438 select GENERIC_CLOCKEVENTS 439 select GENERIC_IRQ_MULTI_HANDLER 440 select GPIOLIB 441 select HAVE_PCI 442 select MVEBU_MBUS 443 select PINCTRL 444 select PINCTRL_DOVE 445 select PLAT_ORION_LEGACY 446 select SPARSE_IRQ 447 select PM_GENERIC_DOMAINS if PM 448 help 449 Support for the Marvell Dove SoC 88AP510 450 451config ARCH_KS8695 452 bool "Micrel/Kendin KS8695" 453 select CLKSRC_MMIO 454 select CPU_ARM922T 455 select GENERIC_CLOCKEVENTS 456 select GPIOLIB 457 select NEED_MACH_MEMORY_H 458 help 459 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 460 System-on-Chip devices. 461 462config ARCH_W90X900 463 bool "Nuvoton W90X900 CPU" 464 select CLKDEV_LOOKUP 465 select CLKSRC_MMIO 466 select CPU_ARM926T 467 select GENERIC_CLOCKEVENTS 468 select GPIOLIB 469 help 470 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 471 At present, the w90x900 has been renamed nuc900, regarding 472 the ARM series product line, you can login the following 473 link address to know more. 474 475 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 476 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 477 478config ARCH_LPC32XX 479 bool "NXP LPC32XX" 480 select ARM_AMBA 481 select CLKDEV_LOOKUP 482 select CLKSRC_LPC32XX 483 select COMMON_CLK 484 select CPU_ARM926T 485 select GENERIC_CLOCKEVENTS 486 select GENERIC_IRQ_MULTI_HANDLER 487 select GPIOLIB 488 select SPARSE_IRQ 489 select USE_OF 490 help 491 Support for the NXP LPC32XX family of processors 492 493config ARCH_PXA 494 bool "PXA2xx/PXA3xx-based" 495 depends on MMU 496 select ARCH_MTD_XIP 497 select ARM_CPU_SUSPEND if PM 498 select AUTO_ZRELADDR 499 select COMMON_CLK 500 select CLKDEV_LOOKUP 501 select CLKSRC_PXA 502 select CLKSRC_MMIO 503 select TIMER_OF 504 select CPU_XSCALE if !CPU_XSC3 505 select GENERIC_CLOCKEVENTS 506 select GENERIC_IRQ_MULTI_HANDLER 507 select GPIO_PXA 508 select GPIOLIB 509 select HAVE_IDE 510 select IRQ_DOMAIN 511 select PLAT_PXA 512 select SPARSE_IRQ 513 help 514 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 515 516config ARCH_RPC 517 bool "RiscPC" 518 depends on MMU 519 select ARCH_ACORN 520 select ARCH_MAY_HAVE_PC_FDC 521 select ARCH_SPARSEMEM_ENABLE 522 select ARM_HAS_SG_CHAIN 523 select CPU_SA110 524 select FIQ 525 select HAVE_IDE 526 select HAVE_PATA_PLATFORM 527 select ISA_DMA_API 528 select NEED_MACH_IO_H 529 select NEED_MACH_MEMORY_H 530 select NO_IOPORT_MAP 531 help 532 On the Acorn Risc-PC, Linux can support the internal IDE disk and 533 CD-ROM interface, serial and parallel port, and the floppy drive. 534 535config ARCH_SA1100 536 bool "SA1100-based" 537 select ARCH_MTD_XIP 538 select ARCH_SPARSEMEM_ENABLE 539 select CLKDEV_LOOKUP 540 select CLKSRC_MMIO 541 select CLKSRC_PXA 542 select TIMER_OF if OF 543 select COMMON_CLK 544 select CPU_FREQ 545 select CPU_SA1100 546 select GENERIC_CLOCKEVENTS 547 select GENERIC_IRQ_MULTI_HANDLER 548 select GPIOLIB 549 select HAVE_IDE 550 select IRQ_DOMAIN 551 select ISA 552 select NEED_MACH_MEMORY_H 553 select SPARSE_IRQ 554 help 555 Support for StrongARM 11x0 based boards. 556 557config ARCH_S3C24XX 558 bool "Samsung S3C24XX SoCs" 559 select ATAGS 560 select CLKDEV_LOOKUP 561 select CLKSRC_SAMSUNG_PWM 562 select GENERIC_CLOCKEVENTS 563 select GPIO_SAMSUNG 564 select GPIOLIB 565 select GENERIC_IRQ_MULTI_HANDLER 566 select HAVE_S3C2410_I2C if I2C 567 select HAVE_S3C2410_WATCHDOG if WATCHDOG 568 select HAVE_S3C_RTC if RTC_CLASS 569 select NEED_MACH_IO_H 570 select SAMSUNG_ATAGS 571 select USE_OF 572 help 573 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 574 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 575 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 576 Samsung SMDK2410 development board (and derivatives). 577 578config ARCH_DAVINCI 579 bool "TI DaVinci" 580 select ARCH_HAS_HOLES_MEMORYMODEL 581 select COMMON_CLK 582 select CPU_ARM926T 583 select GENERIC_ALLOCATOR 584 select GENERIC_CLOCKEVENTS 585 select GENERIC_IRQ_CHIP 586 select GENERIC_IRQ_MULTI_HANDLER 587 select GPIOLIB 588 select HAVE_IDE 589 select PM_GENERIC_DOMAINS if PM 590 select PM_GENERIC_DOMAINS_OF if PM && OF 591 select REGMAP_MMIO 592 select RESET_CONTROLLER 593 select SPARSE_IRQ 594 select USE_OF 595 select ZONE_DMA 596 help 597 Support for TI's DaVinci platform. 598 599config ARCH_OMAP1 600 bool "TI OMAP1" 601 depends on MMU 602 select ARCH_HAS_HOLES_MEMORYMODEL 603 select ARCH_OMAP 604 select CLKDEV_LOOKUP 605 select CLKSRC_MMIO 606 select GENERIC_CLOCKEVENTS 607 select GENERIC_IRQ_CHIP 608 select GENERIC_IRQ_MULTI_HANDLER 609 select GPIOLIB 610 select HAVE_IDE 611 select IRQ_DOMAIN 612 select NEED_MACH_IO_H if PCCARD 613 select NEED_MACH_MEMORY_H 614 select SPARSE_IRQ 615 help 616 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 617 618endchoice 619 620menu "Multiple platform selection" 621 depends on ARCH_MULTIPLATFORM 622 623comment "CPU Core family selection" 624 625config ARCH_MULTI_V4 626 bool "ARMv4 based platforms (FA526)" 627 depends on !ARCH_MULTI_V6_V7 628 select ARCH_MULTI_V4_V5 629 select CPU_FA526 630 631config ARCH_MULTI_V4T 632 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 633 depends on !ARCH_MULTI_V6_V7 634 select ARCH_MULTI_V4_V5 635 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 636 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 637 CPU_ARM925T || CPU_ARM940T) 638 639config ARCH_MULTI_V5 640 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 641 depends on !ARCH_MULTI_V6_V7 642 select ARCH_MULTI_V4_V5 643 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 644 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 645 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 646 647config ARCH_MULTI_V4_V5 648 bool 649 650config ARCH_MULTI_V6 651 bool "ARMv6 based platforms (ARM11)" 652 select ARCH_MULTI_V6_V7 653 select CPU_V6K 654 655config ARCH_MULTI_V7 656 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 657 default y 658 select ARCH_MULTI_V6_V7 659 select CPU_V7 660 select HAVE_SMP 661 662config ARCH_MULTI_V6_V7 663 bool 664 select MIGHT_HAVE_CACHE_L2X0 665 666config ARCH_MULTI_CPU_AUTO 667 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 668 select ARCH_MULTI_V5 669 670endmenu 671 672config ARCH_VIRT 673 bool "Dummy Virtual Machine" 674 depends on ARCH_MULTI_V7 675 select ARM_AMBA 676 select ARM_GIC 677 select ARM_GIC_V2M if PCI 678 select ARM_GIC_V3 679 select ARM_GIC_V3_ITS if PCI 680 select ARM_PSCI 681 select HAVE_ARM_ARCH_TIMER 682 select ARCH_SUPPORTS_BIG_ENDIAN 683 684# 685# This is sorted alphabetically by mach-* pathname. However, plat-* 686# Kconfigs may be included either alphabetically (according to the 687# plat- suffix) or along side the corresponding mach-* source. 688# 689source "arch/arm/mach-actions/Kconfig" 690 691source "arch/arm/mach-alpine/Kconfig" 692 693source "arch/arm/mach-artpec/Kconfig" 694 695source "arch/arm/mach-asm9260/Kconfig" 696 697source "arch/arm/mach-aspeed/Kconfig" 698 699source "arch/arm/mach-at91/Kconfig" 700 701source "arch/arm/mach-axxia/Kconfig" 702 703source "arch/arm/mach-bcm/Kconfig" 704 705source "arch/arm/mach-berlin/Kconfig" 706 707source "arch/arm/mach-clps711x/Kconfig" 708 709source "arch/arm/mach-cns3xxx/Kconfig" 710 711source "arch/arm/mach-davinci/Kconfig" 712 713source "arch/arm/mach-digicolor/Kconfig" 714 715source "arch/arm/mach-dove/Kconfig" 716 717source "arch/arm/mach-ep93xx/Kconfig" 718 719source "arch/arm/mach-exynos/Kconfig" 720source "arch/arm/plat-samsung/Kconfig" 721 722source "arch/arm/mach-footbridge/Kconfig" 723 724source "arch/arm/mach-gemini/Kconfig" 725 726source "arch/arm/mach-highbank/Kconfig" 727 728source "arch/arm/mach-hisi/Kconfig" 729 730source "arch/arm/mach-imx/Kconfig" 731 732source "arch/arm/mach-integrator/Kconfig" 733 734source "arch/arm/mach-iop13xx/Kconfig" 735 736source "arch/arm/mach-iop32x/Kconfig" 737 738source "arch/arm/mach-iop33x/Kconfig" 739 740source "arch/arm/mach-ixp4xx/Kconfig" 741 742source "arch/arm/mach-keystone/Kconfig" 743 744source "arch/arm/mach-ks8695/Kconfig" 745 746source "arch/arm/mach-mediatek/Kconfig" 747 748source "arch/arm/mach-meson/Kconfig" 749 750source "arch/arm/mach-milbeaut/Kconfig" 751 752source "arch/arm/mach-mmp/Kconfig" 753 754source "arch/arm/mach-moxart/Kconfig" 755 756source "arch/arm/mach-mv78xx0/Kconfig" 757 758source "arch/arm/mach-mvebu/Kconfig" 759 760source "arch/arm/mach-mxs/Kconfig" 761 762source "arch/arm/mach-nomadik/Kconfig" 763 764source "arch/arm/mach-npcm/Kconfig" 765 766source "arch/arm/mach-nspire/Kconfig" 767 768source "arch/arm/plat-omap/Kconfig" 769 770source "arch/arm/mach-omap1/Kconfig" 771 772source "arch/arm/mach-omap2/Kconfig" 773 774source "arch/arm/mach-orion5x/Kconfig" 775 776source "arch/arm/mach-oxnas/Kconfig" 777 778source "arch/arm/mach-picoxcell/Kconfig" 779 780source "arch/arm/mach-prima2/Kconfig" 781 782source "arch/arm/mach-pxa/Kconfig" 783source "arch/arm/plat-pxa/Kconfig" 784 785source "arch/arm/mach-qcom/Kconfig" 786 787source "arch/arm/mach-rda/Kconfig" 788 789source "arch/arm/mach-realview/Kconfig" 790 791source "arch/arm/mach-rockchip/Kconfig" 792 793source "arch/arm/mach-s3c24xx/Kconfig" 794 795source "arch/arm/mach-s3c64xx/Kconfig" 796 797source "arch/arm/mach-s5pv210/Kconfig" 798 799source "arch/arm/mach-sa1100/Kconfig" 800 801source "arch/arm/mach-shmobile/Kconfig" 802 803source "arch/arm/mach-socfpga/Kconfig" 804 805source "arch/arm/mach-spear/Kconfig" 806 807source "arch/arm/mach-sti/Kconfig" 808 809source "arch/arm/mach-stm32/Kconfig" 810 811source "arch/arm/mach-sunxi/Kconfig" 812 813source "arch/arm/mach-tango/Kconfig" 814 815source "arch/arm/mach-tegra/Kconfig" 816 817source "arch/arm/mach-u300/Kconfig" 818 819source "arch/arm/mach-uniphier/Kconfig" 820 821source "arch/arm/mach-ux500/Kconfig" 822 823source "arch/arm/mach-versatile/Kconfig" 824 825source "arch/arm/mach-vexpress/Kconfig" 826source "arch/arm/plat-versatile/Kconfig" 827 828source "arch/arm/mach-vt8500/Kconfig" 829 830source "arch/arm/mach-w90x900/Kconfig" 831 832source "arch/arm/mach-zx/Kconfig" 833 834source "arch/arm/mach-zynq/Kconfig" 835 836# ARMv7-M architecture 837config ARCH_EFM32 838 bool "Energy Micro efm32" 839 depends on ARM_SINGLE_ARMV7M 840 select GPIOLIB 841 help 842 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 843 processors. 844 845config ARCH_LPC18XX 846 bool "NXP LPC18xx/LPC43xx" 847 depends on ARM_SINGLE_ARMV7M 848 select ARCH_HAS_RESET_CONTROLLER 849 select ARM_AMBA 850 select CLKSRC_LPC32XX 851 select PINCTRL 852 help 853 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 854 high performance microcontrollers. 855 856config ARCH_MPS2 857 bool "ARM MPS2 platform" 858 depends on ARM_SINGLE_ARMV7M 859 select ARM_AMBA 860 select CLKSRC_MPS2 861 help 862 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 863 with a range of available cores like Cortex-M3/M4/M7. 864 865 Please, note that depends which Application Note is used memory map 866 for the platform may vary, so adjustment of RAM base might be needed. 867 868# Definitions to make life easier 869config ARCH_ACORN 870 bool 871 872config PLAT_IOP 873 bool 874 select GENERIC_CLOCKEVENTS 875 876config PLAT_ORION 877 bool 878 select CLKSRC_MMIO 879 select COMMON_CLK 880 select GENERIC_IRQ_CHIP 881 select IRQ_DOMAIN 882 883config PLAT_ORION_LEGACY 884 bool 885 select PLAT_ORION 886 887config PLAT_PXA 888 bool 889 890config PLAT_VERSATILE 891 bool 892 893source "arch/arm/mm/Kconfig" 894 895config IWMMXT 896 bool "Enable iWMMXt support" 897 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 898 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 899 help 900 Enable support for iWMMXt context switching at run time if 901 running on a CPU that supports it. 902 903if !MMU 904source "arch/arm/Kconfig-nommu" 905endif 906 907config PJ4B_ERRATA_4742 908 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 909 depends on CPU_PJ4B && MACH_ARMADA_370 910 default y 911 help 912 When coming out of either a Wait for Interrupt (WFI) or a Wait for 913 Event (WFE) IDLE states, a specific timing sensitivity exists between 914 the retiring WFI/WFE instructions and the newly issued subsequent 915 instructions. This sensitivity can result in a CPU hang scenario. 916 Workaround: 917 The software must insert either a Data Synchronization Barrier (DSB) 918 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 919 instruction 920 921config ARM_ERRATA_326103 922 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 923 depends on CPU_V6 924 help 925 Executing a SWP instruction to read-only memory does not set bit 11 926 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 927 treat the access as a read, preventing a COW from occurring and 928 causing the faulting task to livelock. 929 930config ARM_ERRATA_411920 931 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 932 depends on CPU_V6 || CPU_V6K 933 help 934 Invalidation of the Instruction Cache operation can 935 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 936 It does not affect the MPCore. This option enables the ARM Ltd. 937 recommended workaround. 938 939config ARM_ERRATA_430973 940 bool "ARM errata: Stale prediction on replaced interworking branch" 941 depends on CPU_V7 942 help 943 This option enables the workaround for the 430973 Cortex-A8 944 r1p* erratum. If a code sequence containing an ARM/Thumb 945 interworking branch is replaced with another code sequence at the 946 same virtual address, whether due to self-modifying code or virtual 947 to physical address re-mapping, Cortex-A8 does not recover from the 948 stale interworking branch prediction. This results in Cortex-A8 949 executing the new code sequence in the incorrect ARM or Thumb state. 950 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 951 and also flushes the branch target cache at every context switch. 952 Note that setting specific bits in the ACTLR register may not be 953 available in non-secure mode. 954 955config ARM_ERRATA_458693 956 bool "ARM errata: Processor deadlock when a false hazard is created" 957 depends on CPU_V7 958 depends on !ARCH_MULTIPLATFORM 959 help 960 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 961 erratum. For very specific sequences of memory operations, it is 962 possible for a hazard condition intended for a cache line to instead 963 be incorrectly associated with a different cache line. This false 964 hazard might then cause a processor deadlock. The workaround enables 965 the L1 caching of the NEON accesses and disables the PLD instruction 966 in the ACTLR register. Note that setting specific bits in the ACTLR 967 register may not be available in non-secure mode. 968 969config ARM_ERRATA_460075 970 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 971 depends on CPU_V7 972 depends on !ARCH_MULTIPLATFORM 973 help 974 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 975 erratum. Any asynchronous access to the L2 cache may encounter a 976 situation in which recent store transactions to the L2 cache are lost 977 and overwritten with stale memory contents from external memory. The 978 workaround disables the write-allocate mode for the L2 cache via the 979 ACTLR register. Note that setting specific bits in the ACTLR register 980 may not be available in non-secure mode. 981 982config ARM_ERRATA_742230 983 bool "ARM errata: DMB operation may be faulty" 984 depends on CPU_V7 && SMP 985 depends on !ARCH_MULTIPLATFORM 986 help 987 This option enables the workaround for the 742230 Cortex-A9 988 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 989 between two write operations may not ensure the correct visibility 990 ordering of the two writes. This workaround sets a specific bit in 991 the diagnostic register of the Cortex-A9 which causes the DMB 992 instruction to behave as a DSB, ensuring the correct behaviour of 993 the two writes. 994 995config ARM_ERRATA_742231 996 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 997 depends on CPU_V7 && SMP 998 depends on !ARCH_MULTIPLATFORM 999 help 1000 This option enables the workaround for the 742231 Cortex-A9 1001 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1002 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1003 accessing some data located in the same cache line, may get corrupted 1004 data due to bad handling of the address hazard when the line gets 1005 replaced from one of the CPUs at the same time as another CPU is 1006 accessing it. This workaround sets specific bits in the diagnostic 1007 register of the Cortex-A9 which reduces the linefill issuing 1008 capabilities of the processor. 1009 1010config ARM_ERRATA_643719 1011 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1012 depends on CPU_V7 && SMP 1013 default y 1014 help 1015 This option enables the workaround for the 643719 Cortex-A9 (prior to 1016 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1017 register returns zero when it should return one. The workaround 1018 corrects this value, ensuring cache maintenance operations which use 1019 it behave as intended and avoiding data corruption. 1020 1021config ARM_ERRATA_720789 1022 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1023 depends on CPU_V7 1024 help 1025 This option enables the workaround for the 720789 Cortex-A9 (prior to 1026 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1027 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1028 As a consequence of this erratum, some TLB entries which should be 1029 invalidated are not, resulting in an incoherency in the system page 1030 tables. The workaround changes the TLB flushing routines to invalidate 1031 entries regardless of the ASID. 1032 1033config ARM_ERRATA_743622 1034 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1035 depends on CPU_V7 1036 depends on !ARCH_MULTIPLATFORM 1037 help 1038 This option enables the workaround for the 743622 Cortex-A9 1039 (r2p*) erratum. Under very rare conditions, a faulty 1040 optimisation in the Cortex-A9 Store Buffer may lead to data 1041 corruption. This workaround sets a specific bit in the diagnostic 1042 register of the Cortex-A9 which disables the Store Buffer 1043 optimisation, preventing the defect from occurring. This has no 1044 visible impact on the overall performance or power consumption of the 1045 processor. 1046 1047config ARM_ERRATA_751472 1048 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1049 depends on CPU_V7 1050 depends on !ARCH_MULTIPLATFORM 1051 help 1052 This option enables the workaround for the 751472 Cortex-A9 (prior 1053 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1054 completion of a following broadcasted operation if the second 1055 operation is received by a CPU before the ICIALLUIS has completed, 1056 potentially leading to corrupted entries in the cache or TLB. 1057 1058config ARM_ERRATA_754322 1059 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1060 depends on CPU_V7 1061 help 1062 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1063 r3p*) erratum. A speculative memory access may cause a page table walk 1064 which starts prior to an ASID switch but completes afterwards. This 1065 can populate the micro-TLB with a stale entry which may be hit with 1066 the new ASID. This workaround places two dsb instructions in the mm 1067 switching code so that no page table walks can cross the ASID switch. 1068 1069config ARM_ERRATA_754327 1070 bool "ARM errata: no automatic Store Buffer drain" 1071 depends on CPU_V7 && SMP 1072 help 1073 This option enables the workaround for the 754327 Cortex-A9 (prior to 1074 r2p0) erratum. The Store Buffer does not have any automatic draining 1075 mechanism and therefore a livelock may occur if an external agent 1076 continuously polls a memory location waiting to observe an update. 1077 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1078 written polling loops from denying visibility of updates to memory. 1079 1080config ARM_ERRATA_364296 1081 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1082 depends on CPU_V6 1083 help 1084 This options enables the workaround for the 364296 ARM1136 1085 r0p2 erratum (possible cache data corruption with 1086 hit-under-miss enabled). It sets the undocumented bit 31 in 1087 the auxiliary control register and the FI bit in the control 1088 register, thus disabling hit-under-miss without putting the 1089 processor into full low interrupt latency mode. ARM11MPCore 1090 is not affected. 1091 1092config ARM_ERRATA_764369 1093 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1094 depends on CPU_V7 && SMP 1095 help 1096 This option enables the workaround for erratum 764369 1097 affecting Cortex-A9 MPCore with two or more processors (all 1098 current revisions). Under certain timing circumstances, a data 1099 cache line maintenance operation by MVA targeting an Inner 1100 Shareable memory region may fail to proceed up to either the 1101 Point of Coherency or to the Point of Unification of the 1102 system. This workaround adds a DSB instruction before the 1103 relevant cache maintenance functions and sets a specific bit 1104 in the diagnostic control register of the SCU. 1105 1106config ARM_ERRATA_775420 1107 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1108 depends on CPU_V7 1109 help 1110 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1111 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1112 operation aborts with MMU exception, it might cause the processor 1113 to deadlock. This workaround puts DSB before executing ISB if 1114 an abort may occur on cache maintenance. 1115 1116config ARM_ERRATA_798181 1117 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1118 depends on CPU_V7 && SMP 1119 help 1120 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1121 adequately shooting down all use of the old entries. This 1122 option enables the Linux kernel workaround for this erratum 1123 which sends an IPI to the CPUs that are running the same ASID 1124 as the one being invalidated. 1125 1126config ARM_ERRATA_773022 1127 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1128 depends on CPU_V7 1129 help 1130 This option enables the workaround for the 773022 Cortex-A15 1131 (up to r0p4) erratum. In certain rare sequences of code, the 1132 loop buffer may deliver incorrect instructions. This 1133 workaround disables the loop buffer to avoid the erratum. 1134 1135config ARM_ERRATA_818325_852422 1136 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1137 depends on CPU_V7 1138 help 1139 This option enables the workaround for: 1140 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1141 instruction might deadlock. Fixed in r0p1. 1142 - Cortex-A12 852422: Execution of a sequence of instructions might 1143 lead to either a data corruption or a CPU deadlock. Not fixed in 1144 any Cortex-A12 cores yet. 1145 This workaround for all both errata involves setting bit[12] of the 1146 Feature Register. This bit disables an optimisation applied to a 1147 sequence of 2 instructions that use opposing condition codes. 1148 1149config ARM_ERRATA_821420 1150 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1151 depends on CPU_V7 1152 help 1153 This option enables the workaround for the 821420 Cortex-A12 1154 (all revs) erratum. In very rare timing conditions, a sequence 1155 of VMOV to Core registers instructions, for which the second 1156 one is in the shadow of a branch or abort, can lead to a 1157 deadlock when the VMOV instructions are issued out-of-order. 1158 1159config ARM_ERRATA_825619 1160 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1161 depends on CPU_V7 1162 help 1163 This option enables the workaround for the 825619 Cortex-A12 1164 (all revs) erratum. Within rare timing constraints, executing a 1165 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1166 and Device/Strongly-Ordered loads and stores might cause deadlock 1167 1168config ARM_ERRATA_852421 1169 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1170 depends on CPU_V7 1171 help 1172 This option enables the workaround for the 852421 Cortex-A17 1173 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1174 execution of a DMB ST instruction might fail to properly order 1175 stores from GroupA and stores from GroupB. 1176 1177config ARM_ERRATA_852423 1178 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1179 depends on CPU_V7 1180 help 1181 This option enables the workaround for: 1182 - Cortex-A17 852423: Execution of a sequence of instructions might 1183 lead to either a data corruption or a CPU deadlock. Not fixed in 1184 any Cortex-A17 cores yet. 1185 This is identical to Cortex-A12 erratum 852422. It is a separate 1186 config option from the A12 erratum due to the way errata are checked 1187 for and handled. 1188 1189endmenu 1190 1191source "arch/arm/common/Kconfig" 1192 1193menu "Bus support" 1194 1195config ISA 1196 bool 1197 help 1198 Find out whether you have ISA slots on your motherboard. ISA is the 1199 name of a bus system, i.e. the way the CPU talks to the other stuff 1200 inside your box. Other bus systems are PCI, EISA, MicroChannel 1201 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1202 newer boards don't support it. If you have ISA, say Y, otherwise N. 1203 1204# Select ISA DMA controller support 1205config ISA_DMA 1206 bool 1207 select ISA_DMA_API 1208 1209# Select ISA DMA interface 1210config ISA_DMA_API 1211 bool 1212 1213config PCI_NANOENGINE 1214 bool "BSE nanoEngine PCI support" 1215 depends on SA1100_NANOENGINE 1216 help 1217 Enable PCI on the BSE nanoEngine board. 1218 1219config PCI_HOST_ITE8152 1220 bool 1221 depends on PCI && MACH_ARMCORE 1222 default y 1223 select DMABOUNCE 1224 1225endmenu 1226 1227menu "Kernel Features" 1228 1229config HAVE_SMP 1230 bool 1231 help 1232 This option should be selected by machines which have an SMP- 1233 capable CPU. 1234 1235 The only effect of this option is to make the SMP-related 1236 options available to the user for configuration. 1237 1238config SMP 1239 bool "Symmetric Multi-Processing" 1240 depends on CPU_V6K || CPU_V7 1241 depends on GENERIC_CLOCKEVENTS 1242 depends on HAVE_SMP 1243 depends on MMU || ARM_MPU 1244 select IRQ_WORK 1245 help 1246 This enables support for systems with more than one CPU. If you have 1247 a system with only one CPU, say N. If you have a system with more 1248 than one CPU, say Y. 1249 1250 If you say N here, the kernel will run on uni- and multiprocessor 1251 machines, but will use only one CPU of a multiprocessor machine. If 1252 you say Y here, the kernel will run on many, but not all, 1253 uniprocessor machines. On a uniprocessor machine, the kernel 1254 will run faster if you say N here. 1255 1256 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1257 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1258 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1259 1260 If you don't know what to do here, say N. 1261 1262config SMP_ON_UP 1263 bool "Allow booting SMP kernel on uniprocessor systems" 1264 depends on SMP && !XIP_KERNEL && MMU 1265 default y 1266 help 1267 SMP kernels contain instructions which fail on non-SMP processors. 1268 Enabling this option allows the kernel to modify itself to make 1269 these instructions safe. Disabling it allows about 1K of space 1270 savings. 1271 1272 If you don't know what to do here, say Y. 1273 1274config ARM_CPU_TOPOLOGY 1275 bool "Support cpu topology definition" 1276 depends on SMP && CPU_V7 1277 default y 1278 help 1279 Support ARM cpu topology definition. The MPIDR register defines 1280 affinity between processors which is then used to describe the cpu 1281 topology of an ARM System. 1282 1283config SCHED_MC 1284 bool "Multi-core scheduler support" 1285 depends on ARM_CPU_TOPOLOGY 1286 help 1287 Multi-core scheduler support improves the CPU scheduler's decision 1288 making when dealing with multi-core CPU chips at a cost of slightly 1289 increased overhead in some places. If unsure say N here. 1290 1291config SCHED_SMT 1292 bool "SMT scheduler support" 1293 depends on ARM_CPU_TOPOLOGY 1294 help 1295 Improves the CPU scheduler's decision making when dealing with 1296 MultiThreading at a cost of slightly increased overhead in some 1297 places. If unsure say N here. 1298 1299config HAVE_ARM_SCU 1300 bool 1301 help 1302 This option enables support for the ARM snoop control unit 1303 1304config HAVE_ARM_ARCH_TIMER 1305 bool "Architected timer support" 1306 depends on CPU_V7 1307 select ARM_ARCH_TIMER 1308 select GENERIC_CLOCKEVENTS 1309 help 1310 This option enables support for the ARM architected timer 1311 1312config HAVE_ARM_TWD 1313 bool 1314 help 1315 This options enables support for the ARM timer and watchdog unit 1316 1317config MCPM 1318 bool "Multi-Cluster Power Management" 1319 depends on CPU_V7 && SMP 1320 help 1321 This option provides the common power management infrastructure 1322 for (multi-)cluster based systems, such as big.LITTLE based 1323 systems. 1324 1325config MCPM_QUAD_CLUSTER 1326 bool 1327 depends on MCPM 1328 help 1329 To avoid wasting resources unnecessarily, MCPM only supports up 1330 to 2 clusters by default. 1331 Platforms with 3 or 4 clusters that use MCPM must select this 1332 option to allow the additional clusters to be managed. 1333 1334config BIG_LITTLE 1335 bool "big.LITTLE support (Experimental)" 1336 depends on CPU_V7 && SMP 1337 select MCPM 1338 help 1339 This option enables support selections for the big.LITTLE 1340 system architecture. 1341 1342config BL_SWITCHER 1343 bool "big.LITTLE switcher support" 1344 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1345 select CPU_PM 1346 help 1347 The big.LITTLE "switcher" provides the core functionality to 1348 transparently handle transition between a cluster of A15's 1349 and a cluster of A7's in a big.LITTLE system. 1350 1351config BL_SWITCHER_DUMMY_IF 1352 tristate "Simple big.LITTLE switcher user interface" 1353 depends on BL_SWITCHER && DEBUG_KERNEL 1354 help 1355 This is a simple and dummy char dev interface to control 1356 the big.LITTLE switcher core code. It is meant for 1357 debugging purposes only. 1358 1359choice 1360 prompt "Memory split" 1361 depends on MMU 1362 default VMSPLIT_3G 1363 help 1364 Select the desired split between kernel and user memory. 1365 1366 If you are not absolutely sure what you are doing, leave this 1367 option alone! 1368 1369 config VMSPLIT_3G 1370 bool "3G/1G user/kernel split" 1371 config VMSPLIT_3G_OPT 1372 depends on !ARM_LPAE 1373 bool "3G/1G user/kernel split (for full 1G low memory)" 1374 config VMSPLIT_2G 1375 bool "2G/2G user/kernel split" 1376 config VMSPLIT_1G 1377 bool "1G/3G user/kernel split" 1378endchoice 1379 1380config PAGE_OFFSET 1381 hex 1382 default PHYS_OFFSET if !MMU 1383 default 0x40000000 if VMSPLIT_1G 1384 default 0x80000000 if VMSPLIT_2G 1385 default 0xB0000000 if VMSPLIT_3G_OPT 1386 default 0xC0000000 1387 1388config NR_CPUS 1389 int "Maximum number of CPUs (2-32)" 1390 range 2 32 1391 depends on SMP 1392 default "4" 1393 1394config HOTPLUG_CPU 1395 bool "Support for hot-pluggable CPUs" 1396 depends on SMP 1397 select GENERIC_IRQ_MIGRATION 1398 help 1399 Say Y here to experiment with turning CPUs off and on. CPUs 1400 can be controlled through /sys/devices/system/cpu. 1401 1402config ARM_PSCI 1403 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1404 depends on HAVE_ARM_SMCCC 1405 select ARM_PSCI_FW 1406 help 1407 Say Y here if you want Linux to communicate with system firmware 1408 implementing the PSCI specification for CPU-centric power 1409 management operations described in ARM document number ARM DEN 1410 0022A ("Power State Coordination Interface System Software on 1411 ARM processors"). 1412 1413# The GPIO number here must be sorted by descending number. In case of 1414# a multiplatform kernel, we just want the highest value required by the 1415# selected platforms. 1416config ARCH_NR_GPIO 1417 int 1418 default 2048 if ARCH_SOCFPGA 1419 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1420 ARCH_ZYNQ 1421 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1422 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1423 default 416 if ARCH_SUNXI 1424 default 392 if ARCH_U8500 1425 default 352 if ARCH_VT8500 1426 default 288 if ARCH_ROCKCHIP 1427 default 264 if MACH_H4700 1428 default 0 1429 help 1430 Maximum number of GPIOs in the system. 1431 1432 If unsure, leave the default value. 1433 1434config HZ_FIXED 1435 int 1436 default 200 if ARCH_EBSA110 1437 default 128 if SOC_AT91RM9200 1438 default 0 1439 1440choice 1441 depends on HZ_FIXED = 0 1442 prompt "Timer frequency" 1443 1444config HZ_100 1445 bool "100 Hz" 1446 1447config HZ_200 1448 bool "200 Hz" 1449 1450config HZ_250 1451 bool "250 Hz" 1452 1453config HZ_300 1454 bool "300 Hz" 1455 1456config HZ_500 1457 bool "500 Hz" 1458 1459config HZ_1000 1460 bool "1000 Hz" 1461 1462endchoice 1463 1464config HZ 1465 int 1466 default HZ_FIXED if HZ_FIXED != 0 1467 default 100 if HZ_100 1468 default 200 if HZ_200 1469 default 250 if HZ_250 1470 default 300 if HZ_300 1471 default 500 if HZ_500 1472 default 1000 1473 1474config SCHED_HRTICK 1475 def_bool HIGH_RES_TIMERS 1476 1477config THUMB2_KERNEL 1478 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1479 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1480 default y if CPU_THUMBONLY 1481 select ARM_UNWIND 1482 help 1483 By enabling this option, the kernel will be compiled in 1484 Thumb-2 mode. 1485 1486 If unsure, say N. 1487 1488config THUMB2_AVOID_R_ARM_THM_JUMP11 1489 bool "Work around buggy Thumb-2 short branch relocations in gas" 1490 depends on THUMB2_KERNEL && MODULES 1491 default y 1492 help 1493 Various binutils versions can resolve Thumb-2 branches to 1494 locally-defined, preemptible global symbols as short-range "b.n" 1495 branch instructions. 1496 1497 This is a problem, because there's no guarantee the final 1498 destination of the symbol, or any candidate locations for a 1499 trampoline, are within range of the branch. For this reason, the 1500 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1501 relocation in modules at all, and it makes little sense to add 1502 support. 1503 1504 The symptom is that the kernel fails with an "unsupported 1505 relocation" error when loading some modules. 1506 1507 Until fixed tools are available, passing 1508 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1509 code which hits this problem, at the cost of a bit of extra runtime 1510 stack usage in some cases. 1511 1512 The problem is described in more detail at: 1513 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1514 1515 Only Thumb-2 kernels are affected. 1516 1517 Unless you are sure your tools don't have this problem, say Y. 1518 1519config ARM_PATCH_IDIV 1520 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1521 depends on CPU_32v7 && !XIP_KERNEL 1522 default y 1523 help 1524 The ARM compiler inserts calls to __aeabi_idiv() and 1525 __aeabi_uidiv() when it needs to perform division on signed 1526 and unsigned integers. Some v7 CPUs have support for the sdiv 1527 and udiv instructions that can be used to implement those 1528 functions. 1529 1530 Enabling this option allows the kernel to modify itself to 1531 replace the first two instructions of these library functions 1532 with the sdiv or udiv plus "bx lr" instructions when the CPU 1533 it is running on supports them. Typically this will be faster 1534 and less power intensive than running the original library 1535 code to do integer division. 1536 1537config AEABI 1538 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1539 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1540 help 1541 This option allows for the kernel to be compiled using the latest 1542 ARM ABI (aka EABI). This is only useful if you are using a user 1543 space environment that is also compiled with EABI. 1544 1545 Since there are major incompatibilities between the legacy ABI and 1546 EABI, especially with regard to structure member alignment, this 1547 option also changes the kernel syscall calling convention to 1548 disambiguate both ABIs and allow for backward compatibility support 1549 (selected with CONFIG_OABI_COMPAT). 1550 1551 To use this you need GCC version 4.0.0 or later. 1552 1553config OABI_COMPAT 1554 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1555 depends on AEABI && !THUMB2_KERNEL 1556 help 1557 This option preserves the old syscall interface along with the 1558 new (ARM EABI) one. It also provides a compatibility layer to 1559 intercept syscalls that have structure arguments which layout 1560 in memory differs between the legacy ABI and the new ARM EABI 1561 (only for non "thumb" binaries). This option adds a tiny 1562 overhead to all syscalls and produces a slightly larger kernel. 1563 1564 The seccomp filter system will not be available when this is 1565 selected, since there is no way yet to sensibly distinguish 1566 between calling conventions during filtering. 1567 1568 If you know you'll be using only pure EABI user space then you 1569 can say N here. If this option is not selected and you attempt 1570 to execute a legacy ABI binary then the result will be 1571 UNPREDICTABLE (in fact it can be predicted that it won't work 1572 at all). If in doubt say N. 1573 1574config ARCH_HAS_HOLES_MEMORYMODEL 1575 bool 1576 1577config ARCH_SPARSEMEM_ENABLE 1578 bool 1579 1580config ARCH_SPARSEMEM_DEFAULT 1581 def_bool ARCH_SPARSEMEM_ENABLE 1582 1583config ARCH_SELECT_MEMORY_MODEL 1584 def_bool ARCH_SPARSEMEM_ENABLE 1585 1586config HAVE_ARCH_PFN_VALID 1587 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1588 1589config HAVE_GENERIC_GUP 1590 def_bool y 1591 depends on ARM_LPAE 1592 1593config HIGHMEM 1594 bool "High Memory Support" 1595 depends on MMU 1596 help 1597 The address space of ARM processors is only 4 Gigabytes large 1598 and it has to accommodate user address space, kernel address 1599 space as well as some memory mapped IO. That means that, if you 1600 have a large amount of physical memory and/or IO, not all of the 1601 memory can be "permanently mapped" by the kernel. The physical 1602 memory that is not permanently mapped is called "high memory". 1603 1604 Depending on the selected kernel/user memory split, minimum 1605 vmalloc space and actual amount of RAM, you may not need this 1606 option which should result in a slightly faster kernel. 1607 1608 If unsure, say n. 1609 1610config HIGHPTE 1611 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1612 depends on HIGHMEM 1613 default y 1614 help 1615 The VM uses one page of physical memory for each page table. 1616 For systems with a lot of processes, this can use a lot of 1617 precious low memory, eventually leading to low memory being 1618 consumed by page tables. Setting this option will allow 1619 user-space 2nd level page tables to reside in high memory. 1620 1621config CPU_SW_DOMAIN_PAN 1622 bool "Enable use of CPU domains to implement privileged no-access" 1623 depends on MMU && !ARM_LPAE 1624 default y 1625 help 1626 Increase kernel security by ensuring that normal kernel accesses 1627 are unable to access userspace addresses. This can help prevent 1628 use-after-free bugs becoming an exploitable privilege escalation 1629 by ensuring that magic values (such as LIST_POISON) will always 1630 fault when dereferenced. 1631 1632 CPUs with low-vector mappings use a best-efforts implementation. 1633 Their lower 1MB needs to remain accessible for the vectors, but 1634 the remainder of userspace will become appropriately inaccessible. 1635 1636config HW_PERF_EVENTS 1637 def_bool y 1638 depends on ARM_PMU 1639 1640config SYS_SUPPORTS_HUGETLBFS 1641 def_bool y 1642 depends on ARM_LPAE 1643 1644config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1645 def_bool y 1646 depends on ARM_LPAE 1647 1648config ARCH_WANT_GENERAL_HUGETLB 1649 def_bool y 1650 1651config ARM_MODULE_PLTS 1652 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1653 depends on MODULES 1654 default y 1655 help 1656 Allocate PLTs when loading modules so that jumps and calls whose 1657 targets are too far away for their relative offsets to be encoded 1658 in the instructions themselves can be bounced via veneers in the 1659 module's PLT. This allows modules to be allocated in the generic 1660 vmalloc area after the dedicated module memory area has been 1661 exhausted. The modules will use slightly more memory, but after 1662 rounding up to page size, the actual memory footprint is usually 1663 the same. 1664 1665 Disabling this is usually safe for small single-platform 1666 configurations. If unsure, say y. 1667 1668config FORCE_MAX_ZONEORDER 1669 int "Maximum zone order" 1670 default "12" if SOC_AM33XX 1671 default "9" if SA1111 || ARCH_EFM32 1672 default "11" 1673 help 1674 The kernel memory allocator divides physically contiguous memory 1675 blocks into "zones", where each zone is a power of two number of 1676 pages. This option selects the largest power of two that the kernel 1677 keeps in the memory allocator. If you need to allocate very large 1678 blocks of physically contiguous memory, then you may need to 1679 increase this value. 1680 1681 This config option is actually maximum order plus one. For example, 1682 a value of 11 means that the largest free memory block is 2^10 pages. 1683 1684config ALIGNMENT_TRAP 1685 bool 1686 depends on CPU_CP15_MMU 1687 default y if !ARCH_EBSA110 1688 select HAVE_PROC_CPU if PROC_FS 1689 help 1690 ARM processors cannot fetch/store information which is not 1691 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1692 address divisible by 4. On 32-bit ARM processors, these non-aligned 1693 fetch/store instructions will be emulated in software if you say 1694 here, which has a severe performance impact. This is necessary for 1695 correct operation of some network protocols. With an IP-only 1696 configuration it is safe to say N, otherwise say Y. 1697 1698config UACCESS_WITH_MEMCPY 1699 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1700 depends on MMU 1701 default y if CPU_FEROCEON 1702 help 1703 Implement faster copy_to_user and clear_user methods for CPU 1704 cores where a 8-word STM instruction give significantly higher 1705 memory write throughput than a sequence of individual 32bit stores. 1706 1707 A possible side effect is a slight increase in scheduling latency 1708 between threads sharing the same address space if they invoke 1709 such copy operations with large buffers. 1710 1711 However, if the CPU data cache is using a write-allocate mode, 1712 this option is unlikely to provide any performance gain. 1713 1714config SECCOMP 1715 bool 1716 prompt "Enable seccomp to safely compute untrusted bytecode" 1717 ---help--- 1718 This kernel feature is useful for number crunching applications 1719 that may need to compute untrusted bytecode during their 1720 execution. By using pipes or other transports made available to 1721 the process as file descriptors supporting the read/write 1722 syscalls, it's possible to isolate those applications in 1723 their own address space using seccomp. Once seccomp is 1724 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1725 and the task is only allowed to execute a few safe syscalls 1726 defined by each seccomp mode. 1727 1728config PARAVIRT 1729 bool "Enable paravirtualization code" 1730 help 1731 This changes the kernel so it can modify itself when it is run 1732 under a hypervisor, potentially improving performance significantly 1733 over full virtualization. 1734 1735config PARAVIRT_TIME_ACCOUNTING 1736 bool "Paravirtual steal time accounting" 1737 select PARAVIRT 1738 help 1739 Select this option to enable fine granularity task steal time 1740 accounting. Time spent executing other tasks in parallel with 1741 the current vCPU is discounted from the vCPU power. To account for 1742 that, there can be a small performance impact. 1743 1744 If in doubt, say N here. 1745 1746config XEN_DOM0 1747 def_bool y 1748 depends on XEN 1749 1750config XEN 1751 bool "Xen guest support on ARM" 1752 depends on ARM && AEABI && OF 1753 depends on CPU_V7 && !CPU_V6 1754 depends on !GENERIC_ATOMIC64 1755 depends on MMU 1756 select ARCH_DMA_ADDR_T_64BIT 1757 select ARM_PSCI 1758 select SWIOTLB 1759 select SWIOTLB_XEN 1760 select PARAVIRT 1761 help 1762 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1763 1764config STACKPROTECTOR_PER_TASK 1765 bool "Use a unique stack canary value for each task" 1766 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1767 select GCC_PLUGIN_ARM_SSP_PER_TASK 1768 default y 1769 help 1770 Due to the fact that GCC uses an ordinary symbol reference from 1771 which to load the value of the stack canary, this value can only 1772 change at reboot time on SMP systems, and all tasks running in the 1773 kernel's address space are forced to use the same canary value for 1774 the entire duration that the system is up. 1775 1776 Enable this option to switch to a different method that uses a 1777 different canary value for each task. 1778 1779endmenu 1780 1781menu "Boot options" 1782 1783config USE_OF 1784 bool "Flattened Device Tree support" 1785 select IRQ_DOMAIN 1786 select OF 1787 help 1788 Include support for flattened device tree machine descriptions. 1789 1790config ATAGS 1791 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1792 default y 1793 help 1794 This is the traditional way of passing data to the kernel at boot 1795 time. If you are solely relying on the flattened device tree (or 1796 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1797 to remove ATAGS support from your kernel binary. If unsure, 1798 leave this to y. 1799 1800config DEPRECATED_PARAM_STRUCT 1801 bool "Provide old way to pass kernel parameters" 1802 depends on ATAGS 1803 help 1804 This was deprecated in 2001 and announced to live on for 5 years. 1805 Some old boot loaders still use this way. 1806 1807# Compressed boot loader in ROM. Yes, we really want to ask about 1808# TEXT and BSS so we preserve their values in the config files. 1809config ZBOOT_ROM_TEXT 1810 hex "Compressed ROM boot loader base address" 1811 default "0" 1812 help 1813 The physical address at which the ROM-able zImage is to be 1814 placed in the target. Platforms which normally make use of 1815 ROM-able zImage formats normally set this to a suitable 1816 value in their defconfig file. 1817 1818 If ZBOOT_ROM is not enabled, this has no effect. 1819 1820config ZBOOT_ROM_BSS 1821 hex "Compressed ROM boot loader BSS address" 1822 default "0" 1823 help 1824 The base address of an area of read/write memory in the target 1825 for the ROM-able zImage which must be available while the 1826 decompressor is running. It must be large enough to hold the 1827 entire decompressed kernel plus an additional 128 KiB. 1828 Platforms which normally make use of ROM-able zImage formats 1829 normally set this to a suitable value in their defconfig file. 1830 1831 If ZBOOT_ROM is not enabled, this has no effect. 1832 1833config ZBOOT_ROM 1834 bool "Compressed boot loader in ROM/flash" 1835 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1836 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1837 help 1838 Say Y here if you intend to execute your compressed kernel image 1839 (zImage) directly from ROM or flash. If unsure, say N. 1840 1841config ARM_APPENDED_DTB 1842 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1843 depends on OF 1844 help 1845 With this option, the boot code will look for a device tree binary 1846 (DTB) appended to zImage 1847 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1848 1849 This is meant as a backward compatibility convenience for those 1850 systems with a bootloader that can't be upgraded to accommodate 1851 the documented boot protocol using a device tree. 1852 1853 Beware that there is very little in terms of protection against 1854 this option being confused by leftover garbage in memory that might 1855 look like a DTB header after a reboot if no actual DTB is appended 1856 to zImage. Do not leave this option active in a production kernel 1857 if you don't intend to always append a DTB. Proper passing of the 1858 location into r2 of a bootloader provided DTB is always preferable 1859 to this option. 1860 1861config ARM_ATAG_DTB_COMPAT 1862 bool "Supplement the appended DTB with traditional ATAG information" 1863 depends on ARM_APPENDED_DTB 1864 help 1865 Some old bootloaders can't be updated to a DTB capable one, yet 1866 they provide ATAGs with memory configuration, the ramdisk address, 1867 the kernel cmdline string, etc. Such information is dynamically 1868 provided by the bootloader and can't always be stored in a static 1869 DTB. To allow a device tree enabled kernel to be used with such 1870 bootloaders, this option allows zImage to extract the information 1871 from the ATAG list and store it at run time into the appended DTB. 1872 1873choice 1874 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1875 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1876 1877config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1878 bool "Use bootloader kernel arguments if available" 1879 help 1880 Uses the command-line options passed by the boot loader instead of 1881 the device tree bootargs property. If the boot loader doesn't provide 1882 any, the device tree bootargs property will be used. 1883 1884config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1885 bool "Extend with bootloader kernel arguments" 1886 help 1887 The command-line arguments provided by the boot loader will be 1888 appended to the the device tree bootargs property. 1889 1890endchoice 1891 1892config CMDLINE 1893 string "Default kernel command string" 1894 default "" 1895 help 1896 On some architectures (EBSA110 and CATS), there is currently no way 1897 for the boot loader to pass arguments to the kernel. For these 1898 architectures, you should supply some command-line options at build 1899 time by entering them here. As a minimum, you should specify the 1900 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1901 1902choice 1903 prompt "Kernel command line type" if CMDLINE != "" 1904 default CMDLINE_FROM_BOOTLOADER 1905 depends on ATAGS 1906 1907config CMDLINE_FROM_BOOTLOADER 1908 bool "Use bootloader kernel arguments if available" 1909 help 1910 Uses the command-line options passed by the boot loader. If 1911 the boot loader doesn't provide any, the default kernel command 1912 string provided in CMDLINE will be used. 1913 1914config CMDLINE_EXTEND 1915 bool "Extend bootloader kernel arguments" 1916 help 1917 The command-line arguments provided by the boot loader will be 1918 appended to the default kernel command string. 1919 1920config CMDLINE_FORCE 1921 bool "Always use the default kernel command string" 1922 help 1923 Always use the default kernel command string, even if the boot 1924 loader passes other arguments to the kernel. 1925 This is useful if you cannot or don't want to change the 1926 command-line options your boot loader passes to the kernel. 1927endchoice 1928 1929config XIP_KERNEL 1930 bool "Kernel Execute-In-Place from ROM" 1931 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1932 help 1933 Execute-In-Place allows the kernel to run from non-volatile storage 1934 directly addressable by the CPU, such as NOR flash. This saves RAM 1935 space since the text section of the kernel is not loaded from flash 1936 to RAM. Read-write sections, such as the data section and stack, 1937 are still copied to RAM. The XIP kernel is not compressed since 1938 it has to run directly from flash, so it will take more space to 1939 store it. The flash address used to link the kernel object files, 1940 and for storing it, is configuration dependent. Therefore, if you 1941 say Y here, you must know the proper physical address where to 1942 store the kernel image depending on your own flash memory usage. 1943 1944 Also note that the make target becomes "make xipImage" rather than 1945 "make zImage" or "make Image". The final kernel binary to put in 1946 ROM memory will be arch/arm/boot/xipImage. 1947 1948 If unsure, say N. 1949 1950config XIP_PHYS_ADDR 1951 hex "XIP Kernel Physical Location" 1952 depends on XIP_KERNEL 1953 default "0x00080000" 1954 help 1955 This is the physical address in your flash memory the kernel will 1956 be linked for and stored to. This address is dependent on your 1957 own flash usage. 1958 1959config XIP_DEFLATED_DATA 1960 bool "Store kernel .data section compressed in ROM" 1961 depends on XIP_KERNEL 1962 select ZLIB_INFLATE 1963 help 1964 Before the kernel is actually executed, its .data section has to be 1965 copied to RAM from ROM. This option allows for storing that data 1966 in compressed form and decompressed to RAM rather than merely being 1967 copied, saving some precious ROM space. A possible drawback is a 1968 slightly longer boot delay. 1969 1970config KEXEC 1971 bool "Kexec system call (EXPERIMENTAL)" 1972 depends on (!SMP || PM_SLEEP_SMP) 1973 depends on !CPU_V7M 1974 select KEXEC_CORE 1975 help 1976 kexec is a system call that implements the ability to shutdown your 1977 current kernel, and to start another kernel. It is like a reboot 1978 but it is independent of the system firmware. And like a reboot 1979 you can start any kernel with it, not just Linux. 1980 1981 It is an ongoing process to be certain the hardware in a machine 1982 is properly shutdown, so do not be surprised if this code does not 1983 initially work for you. 1984 1985config ATAGS_PROC 1986 bool "Export atags in procfs" 1987 depends on ATAGS && KEXEC 1988 default y 1989 help 1990 Should the atags used to boot the kernel be exported in an "atags" 1991 file in procfs. Useful with kexec. 1992 1993config CRASH_DUMP 1994 bool "Build kdump crash kernel (EXPERIMENTAL)" 1995 help 1996 Generate crash dump after being started by kexec. This should 1997 be normally only set in special crash dump kernels which are 1998 loaded in the main kernel with kexec-tools into a specially 1999 reserved region and then later executed after a crash by 2000 kdump/kexec. The crash dump kernel must be compiled to a 2001 memory address not used by the main kernel 2002 2003 For more details see Documentation/kdump/kdump.txt 2004 2005config AUTO_ZRELADDR 2006 bool "Auto calculation of the decompressed kernel image address" 2007 help 2008 ZRELADDR is the physical address where the decompressed kernel 2009 image will be placed. If AUTO_ZRELADDR is selected, the address 2010 will be determined at run-time by masking the current IP with 2011 0xf8000000. This assumes the zImage being placed in the first 128MB 2012 from start of memory. 2013 2014config EFI_STUB 2015 bool 2016 2017config EFI 2018 bool "UEFI runtime support" 2019 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2020 select UCS2_STRING 2021 select EFI_PARAMS_FROM_FDT 2022 select EFI_STUB 2023 select EFI_ARMSTUB 2024 select EFI_RUNTIME_WRAPPERS 2025 ---help--- 2026 This option provides support for runtime services provided 2027 by UEFI firmware (such as non-volatile variables, realtime 2028 clock, and platform reset). A UEFI stub is also provided to 2029 allow the kernel to be booted as an EFI application. This 2030 is only useful for kernels that may run on systems that have 2031 UEFI firmware. 2032 2033config DMI 2034 bool "Enable support for SMBIOS (DMI) tables" 2035 depends on EFI 2036 default y 2037 help 2038 This enables SMBIOS/DMI feature for systems. 2039 2040 This option is only useful on systems that have UEFI firmware. 2041 However, even with this option, the resultant kernel should 2042 continue to boot on existing non-UEFI platforms. 2043 2044 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2045 i.e., the the practice of identifying the platform via DMI to 2046 decide whether certain workarounds for buggy hardware and/or 2047 firmware need to be enabled. This would require the DMI subsystem 2048 to be enabled much earlier than we do on ARM, which is non-trivial. 2049 2050endmenu 2051 2052menu "CPU Power Management" 2053 2054source "drivers/cpufreq/Kconfig" 2055 2056source "drivers/cpuidle/Kconfig" 2057 2058endmenu 2059 2060menu "Floating point emulation" 2061 2062comment "At least one emulation must be selected" 2063 2064config FPE_NWFPE 2065 bool "NWFPE math emulation" 2066 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2067 ---help--- 2068 Say Y to include the NWFPE floating point emulator in the kernel. 2069 This is necessary to run most binaries. Linux does not currently 2070 support floating point hardware so you need to say Y here even if 2071 your machine has an FPA or floating point co-processor podule. 2072 2073 You may say N here if you are going to load the Acorn FPEmulator 2074 early in the bootup. 2075 2076config FPE_NWFPE_XP 2077 bool "Support extended precision" 2078 depends on FPE_NWFPE 2079 help 2080 Say Y to include 80-bit support in the kernel floating-point 2081 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2082 Note that gcc does not generate 80-bit operations by default, 2083 so in most cases this option only enlarges the size of the 2084 floating point emulator without any good reason. 2085 2086 You almost surely want to say N here. 2087 2088config FPE_FASTFPE 2089 bool "FastFPE math emulation (EXPERIMENTAL)" 2090 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2091 ---help--- 2092 Say Y here to include the FAST floating point emulator in the kernel. 2093 This is an experimental much faster emulator which now also has full 2094 precision for the mantissa. It does not support any exceptions. 2095 It is very simple, and approximately 3-6 times faster than NWFPE. 2096 2097 It should be sufficient for most programs. It may be not suitable 2098 for scientific calculations, but you have to check this for yourself. 2099 If you do not feel you need a faster FP emulation you should better 2100 choose NWFPE. 2101 2102config VFP 2103 bool "VFP-format floating point maths" 2104 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2105 help 2106 Say Y to include VFP support code in the kernel. This is needed 2107 if your hardware includes a VFP unit. 2108 2109 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2110 release notes and additional status information. 2111 2112 Say N if your target does not have VFP hardware. 2113 2114config VFPv3 2115 bool 2116 depends on VFP 2117 default y if CPU_V7 2118 2119config NEON 2120 bool "Advanced SIMD (NEON) Extension support" 2121 depends on VFPv3 && CPU_V7 2122 help 2123 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2124 Extension. 2125 2126config KERNEL_MODE_NEON 2127 bool "Support for NEON in kernel mode" 2128 depends on NEON && AEABI 2129 help 2130 Say Y to include support for NEON in kernel mode. 2131 2132endmenu 2133 2134menu "Power management options" 2135 2136source "kernel/power/Kconfig" 2137 2138config ARCH_SUSPEND_POSSIBLE 2139 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2140 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2141 def_bool y 2142 2143config ARM_CPU_SUSPEND 2144 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2145 depends on ARCH_SUSPEND_POSSIBLE 2146 2147config ARCH_HIBERNATION_POSSIBLE 2148 bool 2149 depends on MMU 2150 default y if ARCH_SUSPEND_POSSIBLE 2151 2152endmenu 2153 2154source "drivers/firmware/Kconfig" 2155 2156if CRYPTO 2157source "arch/arm/crypto/Kconfig" 2158endif 2159 2160source "arch/arm/kvm/Kconfig" 2161