1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP 72 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 74 select HAVE_ARCH_TRACEHOOK 75 select HAVE_ARM_SMCCC if CPU_V7 76 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 77 select HAVE_CONTEXT_TRACKING 78 select HAVE_C_RECORDMCOUNT 79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 80 select HAVE_DMA_CONTIGUOUS if MMU 81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 84 select HAVE_EXIT_THREAD 85 select HAVE_FAST_GUP if ARM_LPAE 86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 89 select HAVE_GCC_PLUGINS 90 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 91 select HAVE_IDE if PCI || ISA || PCMCIA 92 select HAVE_IRQ_TIME_ACCOUNTING 93 select HAVE_KERNEL_GZIP 94 select HAVE_KERNEL_LZ4 95 select HAVE_KERNEL_LZMA 96 select HAVE_KERNEL_LZO 97 select HAVE_KERNEL_XZ 98 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 99 select HAVE_KRETPROBES if HAVE_KPROBES 100 select HAVE_MOD_ARCH_SPECIFIC 101 select HAVE_NMI 102 select HAVE_OPROFILE if HAVE_PERF_EVENTS 103 select HAVE_OPTPROBES if !THUMB2_KERNEL 104 select HAVE_PERF_EVENTS 105 select HAVE_PERF_REGS 106 select HAVE_PERF_USER_STACK_DUMP 107 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 108 select HAVE_REGS_AND_STACK_ACCESS_API 109 select HAVE_RSEQ 110 select HAVE_STACKPROTECTOR 111 select HAVE_SYSCALL_TRACEPOINTS 112 select HAVE_UID16 113 select HAVE_VIRT_CPU_ACCOUNTING_GEN 114 select IRQ_FORCED_THREADING 115 select MODULES_USE_ELF_REL 116 select NEED_DMA_MAP_STATE 117 select OF_EARLY_FLATTREE if OF 118 select OLD_SIGACTION 119 select OLD_SIGSUSPEND3 120 select PCI_SYSCALL if PCI 121 select PERF_USE_VMALLOC 122 select RTC_LIB 123 select SYS_SUPPORTS_APM_EMULATION 124 # Above selects are sorted alphabetically; please add new ones 125 # according to that. Thanks. 126 help 127 The ARM series is a line of low-power-consumption RISC chip designs 128 licensed by ARM Ltd and targeted at embedded applications and 129 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 130 manufactured, but legacy ARM-based PC hardware remains popular in 131 Europe. There is an ARM Linux project with a web page at 132 <http://www.arm.linux.org.uk/>. 133 134config ARM_HAS_SG_CHAIN 135 bool 136 137config ARM_DMA_USE_IOMMU 138 bool 139 select ARM_HAS_SG_CHAIN 140 select NEED_SG_DMA_LENGTH 141 142if ARM_DMA_USE_IOMMU 143 144config ARM_DMA_IOMMU_ALIGNMENT 145 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 146 range 4 9 147 default 8 148 help 149 DMA mapping framework by default aligns all buffers to the smallest 150 PAGE_SIZE order which is greater than or equal to the requested buffer 151 size. This works well for buffers up to a few hundreds kilobytes, but 152 for larger buffers it just a waste of address space. Drivers which has 153 relatively small addressing window (like 64Mib) might run out of 154 virtual space with just a few allocations. 155 156 With this parameter you can specify the maximum PAGE_SIZE order for 157 DMA IOMMU buffers. Larger buffers will be aligned only to this 158 specified order. The order is expressed as a power of two multiplied 159 by the PAGE_SIZE. 160 161endif 162 163config SYS_SUPPORTS_APM_EMULATION 164 bool 165 166config HAVE_TCM 167 bool 168 select GENERIC_ALLOCATOR 169 170config HAVE_PROC_CPU 171 bool 172 173config NO_IOPORT_MAP 174 bool 175 176config SBUS 177 bool 178 179config STACKTRACE_SUPPORT 180 bool 181 default y 182 183config LOCKDEP_SUPPORT 184 bool 185 default y 186 187config TRACE_IRQFLAGS_SUPPORT 188 bool 189 default !CPU_V7M 190 191config ARCH_HAS_ILOG2_U32 192 bool 193 194config ARCH_HAS_ILOG2_U64 195 bool 196 197config ARCH_HAS_BANDGAP 198 bool 199 200config FIX_EARLYCON_MEM 201 def_bool y if MMU 202 203config GENERIC_HWEIGHT 204 bool 205 default y 206 207config GENERIC_CALIBRATE_DELAY 208 bool 209 default y 210 211config ARCH_MAY_HAVE_PC_FDC 212 bool 213 214config ZONE_DMA 215 bool 216 217config ARCH_SUPPORTS_UPROBES 218 def_bool y 219 220config ARCH_HAS_DMA_SET_COHERENT_MASK 221 bool 222 223config GENERIC_ISA_DMA 224 bool 225 226config FIQ 227 bool 228 229config NEED_RET_TO_USER 230 bool 231 232config ARCH_MTD_XIP 233 bool 234 235config ARM_PATCH_PHYS_VIRT 236 bool "Patch physical to virtual translations at runtime" if EMBEDDED 237 default y 238 depends on !XIP_KERNEL && MMU 239 help 240 Patch phys-to-virt and virt-to-phys translation functions at 241 boot and module load time according to the position of the 242 kernel in system memory. 243 244 This can only be used with non-XIP MMU kernels where the base 245 of physical memory is at a 16MB boundary. 246 247 Only disable this option if you know that you do not require 248 this feature (eg, building a kernel for a single machine) and 249 you need to shrink the kernel to the minimal size. 250 251config NEED_MACH_IO_H 252 bool 253 help 254 Select this when mach/io.h is required to provide special 255 definitions for this platform. The need for mach/io.h should 256 be avoided when possible. 257 258config NEED_MACH_MEMORY_H 259 bool 260 help 261 Select this when mach/memory.h is required to provide special 262 definitions for this platform. The need for mach/memory.h should 263 be avoided when possible. 264 265config PHYS_OFFSET 266 hex "Physical address of main memory" if MMU 267 depends on !ARM_PATCH_PHYS_VIRT 268 default DRAM_BASE if !MMU 269 default 0x00000000 if ARCH_EBSA110 || \ 270 ARCH_FOOTBRIDGE || \ 271 ARCH_INTEGRATOR || \ 272 ARCH_REALVIEW 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARCH_FLATMEM_ENABLE 319 select ARCH_SPARSEMEM_ENABLE 320 select ARCH_SELECT_MEMORY_MODEL 321 select ARM_HAS_SG_CHAIN 322 select ARM_PATCH_PHYS_VIRT 323 select AUTO_ZRELADDR 324 select TIMER_OF 325 select COMMON_CLK 326 select GENERIC_CLOCKEVENTS 327 select GENERIC_IRQ_MULTI_HANDLER 328 select HAVE_PCI 329 select PCI_DOMAINS_GENERIC if PCI 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARM_NVIC 337 select AUTO_ZRELADDR 338 select TIMER_OF 339 select COMMON_CLK 340 select CPU_V7M 341 select GENERIC_CLOCKEVENTS 342 select NO_IOPORT_MAP 343 select SPARSE_IRQ 344 select USE_OF 345 346config ARCH_EBSA110 347 bool "EBSA-110" 348 select ARCH_USES_GETTIMEOFFSET 349 select CPU_SA110 350 select ISA 351 select NEED_MACH_IO_H 352 select NEED_MACH_MEMORY_H 353 select NO_IOPORT_MAP 354 help 355 This is an evaluation board for the StrongARM processor available 356 from Digital. It has limited hardware on-board, including an 357 Ethernet interface, two PCMCIA sockets, two serial ports and a 358 parallel port. 359 360config ARCH_EP93XX 361 bool "EP93xx-based" 362 select ARCH_SPARSEMEM_ENABLE 363 select ARM_AMBA 364 imply ARM_PATCH_PHYS_VIRT 365 select ARM_VIC 366 select AUTO_ZRELADDR 367 select CLKDEV_LOOKUP 368 select CLKSRC_MMIO 369 select CPU_ARM920T 370 select GENERIC_CLOCKEVENTS 371 select GPIOLIB 372 select HAVE_LEGACY_CLK 373 help 374 This enables support for the Cirrus EP93xx series of CPUs. 375 376config ARCH_FOOTBRIDGE 377 bool "FootBridge" 378 select CPU_SA110 379 select FOOTBRIDGE 380 select GENERIC_CLOCKEVENTS 381 select HAVE_IDE 382 select NEED_MACH_IO_H if !MMU 383 select NEED_MACH_MEMORY_H 384 help 385 Support for systems based on the DC21285 companion chip 386 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 387 388config ARCH_IOP32X 389 bool "IOP32x-based" 390 depends on MMU 391 select CPU_XSCALE 392 select GPIO_IOP 393 select GPIOLIB 394 select NEED_RET_TO_USER 395 select FORCE_PCI 396 select PLAT_IOP 397 help 398 Support for Intel's 80219 and IOP32X (XScale) family of 399 processors. 400 401config ARCH_IXP4XX 402 bool "IXP4xx-based" 403 depends on MMU 404 select ARCH_HAS_DMA_SET_COHERENT_MASK 405 select ARCH_SUPPORTS_BIG_ENDIAN 406 select CPU_XSCALE 407 select DMABOUNCE if PCI 408 select GENERIC_CLOCKEVENTS 409 select GENERIC_IRQ_MULTI_HANDLER 410 select GPIO_IXP4XX 411 select GPIOLIB 412 select HAVE_PCI 413 select IXP4XX_IRQ 414 select IXP4XX_TIMER 415 select NEED_MACH_IO_H 416 select USB_EHCI_BIG_ENDIAN_DESC 417 select USB_EHCI_BIG_ENDIAN_MMIO 418 help 419 Support for Intel's IXP4XX (XScale) family of processors. 420 421config ARCH_DOVE 422 bool "Marvell Dove" 423 select CPU_PJ4 424 select GENERIC_CLOCKEVENTS 425 select GENERIC_IRQ_MULTI_HANDLER 426 select GPIOLIB 427 select HAVE_PCI 428 select MVEBU_MBUS 429 select PINCTRL 430 select PINCTRL_DOVE 431 select PLAT_ORION_LEGACY 432 select SPARSE_IRQ 433 select PM_GENERIC_DOMAINS if PM 434 help 435 Support for the Marvell Dove SoC 88AP510 436 437config ARCH_PXA 438 bool "PXA2xx/PXA3xx-based" 439 depends on MMU 440 select ARCH_MTD_XIP 441 select ARM_CPU_SUSPEND if PM 442 select AUTO_ZRELADDR 443 select COMMON_CLK 444 select CLKSRC_PXA 445 select CLKSRC_MMIO 446 select TIMER_OF 447 select CPU_XSCALE if !CPU_XSC3 448 select GENERIC_CLOCKEVENTS 449 select GENERIC_IRQ_MULTI_HANDLER 450 select GPIO_PXA 451 select GPIOLIB 452 select HAVE_IDE 453 select IRQ_DOMAIN 454 select PLAT_PXA 455 select SPARSE_IRQ 456 help 457 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 458 459config ARCH_RPC 460 bool "RiscPC" 461 depends on MMU 462 select ARCH_ACORN 463 select ARCH_MAY_HAVE_PC_FDC 464 select ARCH_SPARSEMEM_ENABLE 465 select ARM_HAS_SG_CHAIN 466 select CPU_SA110 467 select FIQ 468 select HAVE_IDE 469 select HAVE_PATA_PLATFORM 470 select ISA_DMA_API 471 select NEED_MACH_IO_H 472 select NEED_MACH_MEMORY_H 473 select NO_IOPORT_MAP 474 help 475 On the Acorn Risc-PC, Linux can support the internal IDE disk and 476 CD-ROM interface, serial and parallel port, and the floppy drive. 477 478config ARCH_SA1100 479 bool "SA1100-based" 480 select ARCH_MTD_XIP 481 select ARCH_SPARSEMEM_ENABLE 482 select CLKSRC_MMIO 483 select CLKSRC_PXA 484 select TIMER_OF if OF 485 select COMMON_CLK 486 select CPU_FREQ 487 select CPU_SA1100 488 select GENERIC_CLOCKEVENTS 489 select GENERIC_IRQ_MULTI_HANDLER 490 select GPIOLIB 491 select HAVE_IDE 492 select IRQ_DOMAIN 493 select ISA 494 select NEED_MACH_MEMORY_H 495 select SPARSE_IRQ 496 help 497 Support for StrongARM 11x0 based boards. 498 499config ARCH_S3C24XX 500 bool "Samsung S3C24XX SoCs" 501 select ATAGS 502 select CLKSRC_SAMSUNG_PWM 503 select GENERIC_CLOCKEVENTS 504 select GPIO_SAMSUNG 505 select GPIOLIB 506 select GENERIC_IRQ_MULTI_HANDLER 507 select HAVE_S3C2410_I2C if I2C 508 select HAVE_S3C2410_WATCHDOG if WATCHDOG 509 select HAVE_S3C_RTC if RTC_CLASS 510 select NEED_MACH_IO_H 511 select SAMSUNG_ATAGS 512 select USE_OF 513 help 514 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 515 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 516 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 517 Samsung SMDK2410 development board (and derivatives). 518 519config ARCH_OMAP1 520 bool "TI OMAP1" 521 depends on MMU 522 select ARCH_HAS_HOLES_MEMORYMODEL 523 select ARCH_OMAP 524 select CLKDEV_LOOKUP 525 select CLKSRC_MMIO 526 select GENERIC_CLOCKEVENTS 527 select GENERIC_IRQ_CHIP 528 select GENERIC_IRQ_MULTI_HANDLER 529 select GPIOLIB 530 select HAVE_IDE 531 select HAVE_LEGACY_CLK 532 select IRQ_DOMAIN 533 select NEED_MACH_IO_H if PCCARD 534 select NEED_MACH_MEMORY_H 535 select SPARSE_IRQ 536 help 537 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 538 539endchoice 540 541menu "Multiple platform selection" 542 depends on ARCH_MULTIPLATFORM 543 544comment "CPU Core family selection" 545 546config ARCH_MULTI_V4 547 bool "ARMv4 based platforms (FA526)" 548 depends on !ARCH_MULTI_V6_V7 549 select ARCH_MULTI_V4_V5 550 select CPU_FA526 551 552config ARCH_MULTI_V4T 553 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 554 depends on !ARCH_MULTI_V6_V7 555 select ARCH_MULTI_V4_V5 556 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 557 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 558 CPU_ARM925T || CPU_ARM940T) 559 560config ARCH_MULTI_V5 561 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 562 depends on !ARCH_MULTI_V6_V7 563 select ARCH_MULTI_V4_V5 564 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 565 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 566 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 567 568config ARCH_MULTI_V4_V5 569 bool 570 571config ARCH_MULTI_V6 572 bool "ARMv6 based platforms (ARM11)" 573 select ARCH_MULTI_V6_V7 574 select CPU_V6K 575 576config ARCH_MULTI_V7 577 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 578 default y 579 select ARCH_MULTI_V6_V7 580 select CPU_V7 581 select HAVE_SMP 582 583config ARCH_MULTI_V6_V7 584 bool 585 select MIGHT_HAVE_CACHE_L2X0 586 587config ARCH_MULTI_CPU_AUTO 588 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 589 select ARCH_MULTI_V5 590 591endmenu 592 593config ARCH_VIRT 594 bool "Dummy Virtual Machine" 595 depends on ARCH_MULTI_V7 596 select ARM_AMBA 597 select ARM_GIC 598 select ARM_GIC_V2M if PCI 599 select ARM_GIC_V3 600 select ARM_GIC_V3_ITS if PCI 601 select ARM_PSCI 602 select HAVE_ARM_ARCH_TIMER 603 select ARCH_SUPPORTS_BIG_ENDIAN 604 605# 606# This is sorted alphabetically by mach-* pathname. However, plat-* 607# Kconfigs may be included either alphabetically (according to the 608# plat- suffix) or along side the corresponding mach-* source. 609# 610source "arch/arm/mach-actions/Kconfig" 611 612source "arch/arm/mach-alpine/Kconfig" 613 614source "arch/arm/mach-artpec/Kconfig" 615 616source "arch/arm/mach-asm9260/Kconfig" 617 618source "arch/arm/mach-aspeed/Kconfig" 619 620source "arch/arm/mach-at91/Kconfig" 621 622source "arch/arm/mach-axxia/Kconfig" 623 624source "arch/arm/mach-bcm/Kconfig" 625 626source "arch/arm/mach-berlin/Kconfig" 627 628source "arch/arm/mach-clps711x/Kconfig" 629 630source "arch/arm/mach-cns3xxx/Kconfig" 631 632source "arch/arm/mach-davinci/Kconfig" 633 634source "arch/arm/mach-digicolor/Kconfig" 635 636source "arch/arm/mach-dove/Kconfig" 637 638source "arch/arm/mach-ep93xx/Kconfig" 639 640source "arch/arm/mach-exynos/Kconfig" 641source "arch/arm/plat-samsung/Kconfig" 642 643source "arch/arm/mach-footbridge/Kconfig" 644 645source "arch/arm/mach-gemini/Kconfig" 646 647source "arch/arm/mach-highbank/Kconfig" 648 649source "arch/arm/mach-hisi/Kconfig" 650 651source "arch/arm/mach-imx/Kconfig" 652 653source "arch/arm/mach-integrator/Kconfig" 654 655source "arch/arm/mach-iop32x/Kconfig" 656 657source "arch/arm/mach-ixp4xx/Kconfig" 658 659source "arch/arm/mach-keystone/Kconfig" 660 661source "arch/arm/mach-lpc32xx/Kconfig" 662 663source "arch/arm/mach-mediatek/Kconfig" 664 665source "arch/arm/mach-meson/Kconfig" 666 667source "arch/arm/mach-milbeaut/Kconfig" 668 669source "arch/arm/mach-mmp/Kconfig" 670 671source "arch/arm/mach-moxart/Kconfig" 672 673source "arch/arm/mach-mstar/Kconfig" 674 675source "arch/arm/mach-mv78xx0/Kconfig" 676 677source "arch/arm/mach-mvebu/Kconfig" 678 679source "arch/arm/mach-mxs/Kconfig" 680 681source "arch/arm/mach-nomadik/Kconfig" 682 683source "arch/arm/mach-npcm/Kconfig" 684 685source "arch/arm/mach-nspire/Kconfig" 686 687source "arch/arm/plat-omap/Kconfig" 688 689source "arch/arm/mach-omap1/Kconfig" 690 691source "arch/arm/mach-omap2/Kconfig" 692 693source "arch/arm/mach-orion5x/Kconfig" 694 695source "arch/arm/mach-oxnas/Kconfig" 696 697source "arch/arm/mach-picoxcell/Kconfig" 698 699source "arch/arm/mach-prima2/Kconfig" 700 701source "arch/arm/mach-pxa/Kconfig" 702source "arch/arm/plat-pxa/Kconfig" 703 704source "arch/arm/mach-qcom/Kconfig" 705 706source "arch/arm/mach-rda/Kconfig" 707 708source "arch/arm/mach-realtek/Kconfig" 709 710source "arch/arm/mach-realview/Kconfig" 711 712source "arch/arm/mach-rockchip/Kconfig" 713 714source "arch/arm/mach-s3c24xx/Kconfig" 715 716source "arch/arm/mach-s3c64xx/Kconfig" 717 718source "arch/arm/mach-s5pv210/Kconfig" 719 720source "arch/arm/mach-sa1100/Kconfig" 721 722source "arch/arm/mach-shmobile/Kconfig" 723 724source "arch/arm/mach-socfpga/Kconfig" 725 726source "arch/arm/mach-spear/Kconfig" 727 728source "arch/arm/mach-sti/Kconfig" 729 730source "arch/arm/mach-stm32/Kconfig" 731 732source "arch/arm/mach-sunxi/Kconfig" 733 734source "arch/arm/mach-tango/Kconfig" 735 736source "arch/arm/mach-tegra/Kconfig" 737 738source "arch/arm/mach-u300/Kconfig" 739 740source "arch/arm/mach-uniphier/Kconfig" 741 742source "arch/arm/mach-ux500/Kconfig" 743 744source "arch/arm/mach-versatile/Kconfig" 745 746source "arch/arm/mach-vexpress/Kconfig" 747 748source "arch/arm/mach-vt8500/Kconfig" 749 750source "arch/arm/mach-zx/Kconfig" 751 752source "arch/arm/mach-zynq/Kconfig" 753 754# ARMv7-M architecture 755config ARCH_EFM32 756 bool "Energy Micro efm32" 757 depends on ARM_SINGLE_ARMV7M 758 select GPIOLIB 759 help 760 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 761 processors. 762 763config ARCH_LPC18XX 764 bool "NXP LPC18xx/LPC43xx" 765 depends on ARM_SINGLE_ARMV7M 766 select ARCH_HAS_RESET_CONTROLLER 767 select ARM_AMBA 768 select CLKSRC_LPC32XX 769 select PINCTRL 770 help 771 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 772 high performance microcontrollers. 773 774config ARCH_MPS2 775 bool "ARM MPS2 platform" 776 depends on ARM_SINGLE_ARMV7M 777 select ARM_AMBA 778 select CLKSRC_MPS2 779 help 780 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 781 with a range of available cores like Cortex-M3/M4/M7. 782 783 Please, note that depends which Application Note is used memory map 784 for the platform may vary, so adjustment of RAM base might be needed. 785 786# Definitions to make life easier 787config ARCH_ACORN 788 bool 789 790config PLAT_IOP 791 bool 792 select GENERIC_CLOCKEVENTS 793 794config PLAT_ORION 795 bool 796 select CLKSRC_MMIO 797 select COMMON_CLK 798 select GENERIC_IRQ_CHIP 799 select IRQ_DOMAIN 800 801config PLAT_ORION_LEGACY 802 bool 803 select PLAT_ORION 804 805config PLAT_PXA 806 bool 807 808config PLAT_VERSATILE 809 bool 810 811source "arch/arm/mm/Kconfig" 812 813config IWMMXT 814 bool "Enable iWMMXt support" 815 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 816 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 817 help 818 Enable support for iWMMXt context switching at run time if 819 running on a CPU that supports it. 820 821if !MMU 822source "arch/arm/Kconfig-nommu" 823endif 824 825config PJ4B_ERRATA_4742 826 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 827 depends on CPU_PJ4B && MACH_ARMADA_370 828 default y 829 help 830 When coming out of either a Wait for Interrupt (WFI) or a Wait for 831 Event (WFE) IDLE states, a specific timing sensitivity exists between 832 the retiring WFI/WFE instructions and the newly issued subsequent 833 instructions. This sensitivity can result in a CPU hang scenario. 834 Workaround: 835 The software must insert either a Data Synchronization Barrier (DSB) 836 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 837 instruction 838 839config ARM_ERRATA_326103 840 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 841 depends on CPU_V6 842 help 843 Executing a SWP instruction to read-only memory does not set bit 11 844 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 845 treat the access as a read, preventing a COW from occurring and 846 causing the faulting task to livelock. 847 848config ARM_ERRATA_411920 849 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 850 depends on CPU_V6 || CPU_V6K 851 help 852 Invalidation of the Instruction Cache operation can 853 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 854 It does not affect the MPCore. This option enables the ARM Ltd. 855 recommended workaround. 856 857config ARM_ERRATA_430973 858 bool "ARM errata: Stale prediction on replaced interworking branch" 859 depends on CPU_V7 860 help 861 This option enables the workaround for the 430973 Cortex-A8 862 r1p* erratum. If a code sequence containing an ARM/Thumb 863 interworking branch is replaced with another code sequence at the 864 same virtual address, whether due to self-modifying code or virtual 865 to physical address re-mapping, Cortex-A8 does not recover from the 866 stale interworking branch prediction. This results in Cortex-A8 867 executing the new code sequence in the incorrect ARM or Thumb state. 868 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 869 and also flushes the branch target cache at every context switch. 870 Note that setting specific bits in the ACTLR register may not be 871 available in non-secure mode. 872 873config ARM_ERRATA_458693 874 bool "ARM errata: Processor deadlock when a false hazard is created" 875 depends on CPU_V7 876 depends on !ARCH_MULTIPLATFORM 877 help 878 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 879 erratum. For very specific sequences of memory operations, it is 880 possible for a hazard condition intended for a cache line to instead 881 be incorrectly associated with a different cache line. This false 882 hazard might then cause a processor deadlock. The workaround enables 883 the L1 caching of the NEON accesses and disables the PLD instruction 884 in the ACTLR register. Note that setting specific bits in the ACTLR 885 register may not be available in non-secure mode. 886 887config ARM_ERRATA_460075 888 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 889 depends on CPU_V7 890 depends on !ARCH_MULTIPLATFORM 891 help 892 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 893 erratum. Any asynchronous access to the L2 cache may encounter a 894 situation in which recent store transactions to the L2 cache are lost 895 and overwritten with stale memory contents from external memory. The 896 workaround disables the write-allocate mode for the L2 cache via the 897 ACTLR register. Note that setting specific bits in the ACTLR register 898 may not be available in non-secure mode. 899 900config ARM_ERRATA_742230 901 bool "ARM errata: DMB operation may be faulty" 902 depends on CPU_V7 && SMP 903 depends on !ARCH_MULTIPLATFORM 904 help 905 This option enables the workaround for the 742230 Cortex-A9 906 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 907 between two write operations may not ensure the correct visibility 908 ordering of the two writes. This workaround sets a specific bit in 909 the diagnostic register of the Cortex-A9 which causes the DMB 910 instruction to behave as a DSB, ensuring the correct behaviour of 911 the two writes. 912 913config ARM_ERRATA_742231 914 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 915 depends on CPU_V7 && SMP 916 depends on !ARCH_MULTIPLATFORM 917 help 918 This option enables the workaround for the 742231 Cortex-A9 919 (r2p0..r2p2) erratum. Under certain conditions, specific to the 920 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 921 accessing some data located in the same cache line, may get corrupted 922 data due to bad handling of the address hazard when the line gets 923 replaced from one of the CPUs at the same time as another CPU is 924 accessing it. This workaround sets specific bits in the diagnostic 925 register of the Cortex-A9 which reduces the linefill issuing 926 capabilities of the processor. 927 928config ARM_ERRATA_643719 929 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 930 depends on CPU_V7 && SMP 931 default y 932 help 933 This option enables the workaround for the 643719 Cortex-A9 (prior to 934 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 935 register returns zero when it should return one. The workaround 936 corrects this value, ensuring cache maintenance operations which use 937 it behave as intended and avoiding data corruption. 938 939config ARM_ERRATA_720789 940 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 941 depends on CPU_V7 942 help 943 This option enables the workaround for the 720789 Cortex-A9 (prior to 944 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 945 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 946 As a consequence of this erratum, some TLB entries which should be 947 invalidated are not, resulting in an incoherency in the system page 948 tables. The workaround changes the TLB flushing routines to invalidate 949 entries regardless of the ASID. 950 951config ARM_ERRATA_743622 952 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 953 depends on CPU_V7 954 depends on !ARCH_MULTIPLATFORM 955 help 956 This option enables the workaround for the 743622 Cortex-A9 957 (r2p*) erratum. Under very rare conditions, a faulty 958 optimisation in the Cortex-A9 Store Buffer may lead to data 959 corruption. This workaround sets a specific bit in the diagnostic 960 register of the Cortex-A9 which disables the Store Buffer 961 optimisation, preventing the defect from occurring. This has no 962 visible impact on the overall performance or power consumption of the 963 processor. 964 965config ARM_ERRATA_751472 966 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 967 depends on CPU_V7 968 depends on !ARCH_MULTIPLATFORM 969 help 970 This option enables the workaround for the 751472 Cortex-A9 (prior 971 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 972 completion of a following broadcasted operation if the second 973 operation is received by a CPU before the ICIALLUIS has completed, 974 potentially leading to corrupted entries in the cache or TLB. 975 976config ARM_ERRATA_754322 977 bool "ARM errata: possible faulty MMU translations following an ASID switch" 978 depends on CPU_V7 979 help 980 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 981 r3p*) erratum. A speculative memory access may cause a page table walk 982 which starts prior to an ASID switch but completes afterwards. This 983 can populate the micro-TLB with a stale entry which may be hit with 984 the new ASID. This workaround places two dsb instructions in the mm 985 switching code so that no page table walks can cross the ASID switch. 986 987config ARM_ERRATA_754327 988 bool "ARM errata: no automatic Store Buffer drain" 989 depends on CPU_V7 && SMP 990 help 991 This option enables the workaround for the 754327 Cortex-A9 (prior to 992 r2p0) erratum. The Store Buffer does not have any automatic draining 993 mechanism and therefore a livelock may occur if an external agent 994 continuously polls a memory location waiting to observe an update. 995 This workaround defines cpu_relax() as smp_mb(), preventing correctly 996 written polling loops from denying visibility of updates to memory. 997 998config ARM_ERRATA_364296 999 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1000 depends on CPU_V6 1001 help 1002 This options enables the workaround for the 364296 ARM1136 1003 r0p2 erratum (possible cache data corruption with 1004 hit-under-miss enabled). It sets the undocumented bit 31 in 1005 the auxiliary control register and the FI bit in the control 1006 register, thus disabling hit-under-miss without putting the 1007 processor into full low interrupt latency mode. ARM11MPCore 1008 is not affected. 1009 1010config ARM_ERRATA_764369 1011 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1012 depends on CPU_V7 && SMP 1013 help 1014 This option enables the workaround for erratum 764369 1015 affecting Cortex-A9 MPCore with two or more processors (all 1016 current revisions). Under certain timing circumstances, a data 1017 cache line maintenance operation by MVA targeting an Inner 1018 Shareable memory region may fail to proceed up to either the 1019 Point of Coherency or to the Point of Unification of the 1020 system. This workaround adds a DSB instruction before the 1021 relevant cache maintenance functions and sets a specific bit 1022 in the diagnostic control register of the SCU. 1023 1024config ARM_ERRATA_775420 1025 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1026 depends on CPU_V7 1027 help 1028 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1029 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1030 operation aborts with MMU exception, it might cause the processor 1031 to deadlock. This workaround puts DSB before executing ISB if 1032 an abort may occur on cache maintenance. 1033 1034config ARM_ERRATA_798181 1035 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1036 depends on CPU_V7 && SMP 1037 help 1038 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1039 adequately shooting down all use of the old entries. This 1040 option enables the Linux kernel workaround for this erratum 1041 which sends an IPI to the CPUs that are running the same ASID 1042 as the one being invalidated. 1043 1044config ARM_ERRATA_773022 1045 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1046 depends on CPU_V7 1047 help 1048 This option enables the workaround for the 773022 Cortex-A15 1049 (up to r0p4) erratum. In certain rare sequences of code, the 1050 loop buffer may deliver incorrect instructions. This 1051 workaround disables the loop buffer to avoid the erratum. 1052 1053config ARM_ERRATA_818325_852422 1054 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1055 depends on CPU_V7 1056 help 1057 This option enables the workaround for: 1058 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1059 instruction might deadlock. Fixed in r0p1. 1060 - Cortex-A12 852422: Execution of a sequence of instructions might 1061 lead to either a data corruption or a CPU deadlock. Not fixed in 1062 any Cortex-A12 cores yet. 1063 This workaround for all both errata involves setting bit[12] of the 1064 Feature Register. This bit disables an optimisation applied to a 1065 sequence of 2 instructions that use opposing condition codes. 1066 1067config ARM_ERRATA_821420 1068 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1069 depends on CPU_V7 1070 help 1071 This option enables the workaround for the 821420 Cortex-A12 1072 (all revs) erratum. In very rare timing conditions, a sequence 1073 of VMOV to Core registers instructions, for which the second 1074 one is in the shadow of a branch or abort, can lead to a 1075 deadlock when the VMOV instructions are issued out-of-order. 1076 1077config ARM_ERRATA_825619 1078 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1079 depends on CPU_V7 1080 help 1081 This option enables the workaround for the 825619 Cortex-A12 1082 (all revs) erratum. Within rare timing constraints, executing a 1083 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1084 and Device/Strongly-Ordered loads and stores might cause deadlock 1085 1086config ARM_ERRATA_857271 1087 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1088 depends on CPU_V7 1089 help 1090 This option enables the workaround for the 857271 Cortex-A12 1091 (all revs) erratum. Under very rare timing conditions, the CPU might 1092 hang. The workaround is expected to have a < 1% performance impact. 1093 1094config ARM_ERRATA_852421 1095 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1096 depends on CPU_V7 1097 help 1098 This option enables the workaround for the 852421 Cortex-A17 1099 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1100 execution of a DMB ST instruction might fail to properly order 1101 stores from GroupA and stores from GroupB. 1102 1103config ARM_ERRATA_852423 1104 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1105 depends on CPU_V7 1106 help 1107 This option enables the workaround for: 1108 - Cortex-A17 852423: Execution of a sequence of instructions might 1109 lead to either a data corruption or a CPU deadlock. Not fixed in 1110 any Cortex-A17 cores yet. 1111 This is identical to Cortex-A12 erratum 852422. It is a separate 1112 config option from the A12 erratum due to the way errata are checked 1113 for and handled. 1114 1115config ARM_ERRATA_857272 1116 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1117 depends on CPU_V7 1118 help 1119 This option enables the workaround for the 857272 Cortex-A17 erratum. 1120 This erratum is not known to be fixed in any A17 revision. 1121 This is identical to Cortex-A12 erratum 857271. It is a separate 1122 config option from the A12 erratum due to the way errata are checked 1123 for and handled. 1124 1125endmenu 1126 1127source "arch/arm/common/Kconfig" 1128 1129menu "Bus support" 1130 1131config ISA 1132 bool 1133 help 1134 Find out whether you have ISA slots on your motherboard. ISA is the 1135 name of a bus system, i.e. the way the CPU talks to the other stuff 1136 inside your box. Other bus systems are PCI, EISA, MicroChannel 1137 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1138 newer boards don't support it. If you have ISA, say Y, otherwise N. 1139 1140# Select ISA DMA controller support 1141config ISA_DMA 1142 bool 1143 select ISA_DMA_API 1144 1145# Select ISA DMA interface 1146config ISA_DMA_API 1147 bool 1148 1149config PCI_NANOENGINE 1150 bool "BSE nanoEngine PCI support" 1151 depends on SA1100_NANOENGINE 1152 help 1153 Enable PCI on the BSE nanoEngine board. 1154 1155config ARM_ERRATA_814220 1156 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1157 depends on CPU_V7 1158 help 1159 The v7 ARM states that all cache and branch predictor maintenance 1160 operations that do not specify an address execute, relative to 1161 each other, in program order. 1162 However, because of this erratum, an L2 set/way cache maintenance 1163 operation can overtake an L1 set/way cache maintenance operation. 1164 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1165 r0p4, r0p5. 1166 1167endmenu 1168 1169menu "Kernel Features" 1170 1171config HAVE_SMP 1172 bool 1173 help 1174 This option should be selected by machines which have an SMP- 1175 capable CPU. 1176 1177 The only effect of this option is to make the SMP-related 1178 options available to the user for configuration. 1179 1180config SMP 1181 bool "Symmetric Multi-Processing" 1182 depends on CPU_V6K || CPU_V7 1183 depends on GENERIC_CLOCKEVENTS 1184 depends on HAVE_SMP 1185 depends on MMU || ARM_MPU 1186 select IRQ_WORK 1187 help 1188 This enables support for systems with more than one CPU. If you have 1189 a system with only one CPU, say N. If you have a system with more 1190 than one CPU, say Y. 1191 1192 If you say N here, the kernel will run on uni- and multiprocessor 1193 machines, but will use only one CPU of a multiprocessor machine. If 1194 you say Y here, the kernel will run on many, but not all, 1195 uniprocessor machines. On a uniprocessor machine, the kernel 1196 will run faster if you say N here. 1197 1198 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1199 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1200 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1201 1202 If you don't know what to do here, say N. 1203 1204config SMP_ON_UP 1205 bool "Allow booting SMP kernel on uniprocessor systems" 1206 depends on SMP && !XIP_KERNEL && MMU 1207 default y 1208 help 1209 SMP kernels contain instructions which fail on non-SMP processors. 1210 Enabling this option allows the kernel to modify itself to make 1211 these instructions safe. Disabling it allows about 1K of space 1212 savings. 1213 1214 If you don't know what to do here, say Y. 1215 1216config ARM_CPU_TOPOLOGY 1217 bool "Support cpu topology definition" 1218 depends on SMP && CPU_V7 1219 default y 1220 help 1221 Support ARM cpu topology definition. The MPIDR register defines 1222 affinity between processors which is then used to describe the cpu 1223 topology of an ARM System. 1224 1225config SCHED_MC 1226 bool "Multi-core scheduler support" 1227 depends on ARM_CPU_TOPOLOGY 1228 help 1229 Multi-core scheduler support improves the CPU scheduler's decision 1230 making when dealing with multi-core CPU chips at a cost of slightly 1231 increased overhead in some places. If unsure say N here. 1232 1233config SCHED_SMT 1234 bool "SMT scheduler support" 1235 depends on ARM_CPU_TOPOLOGY 1236 help 1237 Improves the CPU scheduler's decision making when dealing with 1238 MultiThreading at a cost of slightly increased overhead in some 1239 places. If unsure say N here. 1240 1241config HAVE_ARM_SCU 1242 bool 1243 help 1244 This option enables support for the ARM snoop control unit 1245 1246config HAVE_ARM_ARCH_TIMER 1247 bool "Architected timer support" 1248 depends on CPU_V7 1249 select ARM_ARCH_TIMER 1250 help 1251 This option enables support for the ARM architected timer 1252 1253config HAVE_ARM_TWD 1254 bool 1255 help 1256 This options enables support for the ARM timer and watchdog unit 1257 1258config MCPM 1259 bool "Multi-Cluster Power Management" 1260 depends on CPU_V7 && SMP 1261 help 1262 This option provides the common power management infrastructure 1263 for (multi-)cluster based systems, such as big.LITTLE based 1264 systems. 1265 1266config MCPM_QUAD_CLUSTER 1267 bool 1268 depends on MCPM 1269 help 1270 To avoid wasting resources unnecessarily, MCPM only supports up 1271 to 2 clusters by default. 1272 Platforms with 3 or 4 clusters that use MCPM must select this 1273 option to allow the additional clusters to be managed. 1274 1275config BIG_LITTLE 1276 bool "big.LITTLE support (Experimental)" 1277 depends on CPU_V7 && SMP 1278 select MCPM 1279 help 1280 This option enables support selections for the big.LITTLE 1281 system architecture. 1282 1283config BL_SWITCHER 1284 bool "big.LITTLE switcher support" 1285 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1286 select CPU_PM 1287 help 1288 The big.LITTLE "switcher" provides the core functionality to 1289 transparently handle transition between a cluster of A15's 1290 and a cluster of A7's in a big.LITTLE system. 1291 1292config BL_SWITCHER_DUMMY_IF 1293 tristate "Simple big.LITTLE switcher user interface" 1294 depends on BL_SWITCHER && DEBUG_KERNEL 1295 help 1296 This is a simple and dummy char dev interface to control 1297 the big.LITTLE switcher core code. It is meant for 1298 debugging purposes only. 1299 1300choice 1301 prompt "Memory split" 1302 depends on MMU 1303 default VMSPLIT_3G 1304 help 1305 Select the desired split between kernel and user memory. 1306 1307 If you are not absolutely sure what you are doing, leave this 1308 option alone! 1309 1310 config VMSPLIT_3G 1311 bool "3G/1G user/kernel split" 1312 config VMSPLIT_3G_OPT 1313 depends on !ARM_LPAE 1314 bool "3G/1G user/kernel split (for full 1G low memory)" 1315 config VMSPLIT_2G 1316 bool "2G/2G user/kernel split" 1317 config VMSPLIT_1G 1318 bool "1G/3G user/kernel split" 1319endchoice 1320 1321config PAGE_OFFSET 1322 hex 1323 default PHYS_OFFSET if !MMU 1324 default 0x40000000 if VMSPLIT_1G 1325 default 0x80000000 if VMSPLIT_2G 1326 default 0xB0000000 if VMSPLIT_3G_OPT 1327 default 0xC0000000 1328 1329config NR_CPUS 1330 int "Maximum number of CPUs (2-32)" 1331 range 2 32 1332 depends on SMP 1333 default "4" 1334 1335config HOTPLUG_CPU 1336 bool "Support for hot-pluggable CPUs" 1337 depends on SMP 1338 select GENERIC_IRQ_MIGRATION 1339 help 1340 Say Y here to experiment with turning CPUs off and on. CPUs 1341 can be controlled through /sys/devices/system/cpu. 1342 1343config ARM_PSCI 1344 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1345 depends on HAVE_ARM_SMCCC 1346 select ARM_PSCI_FW 1347 help 1348 Say Y here if you want Linux to communicate with system firmware 1349 implementing the PSCI specification for CPU-centric power 1350 management operations described in ARM document number ARM DEN 1351 0022A ("Power State Coordination Interface System Software on 1352 ARM processors"). 1353 1354# The GPIO number here must be sorted by descending number. In case of 1355# a multiplatform kernel, we just want the highest value required by the 1356# selected platforms. 1357config ARCH_NR_GPIO 1358 int 1359 default 2048 if ARCH_SOCFPGA 1360 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1361 ARCH_ZYNQ || ARCH_ASPEED 1362 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1363 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1364 default 416 if ARCH_SUNXI 1365 default 392 if ARCH_U8500 1366 default 352 if ARCH_VT8500 1367 default 288 if ARCH_ROCKCHIP 1368 default 264 if MACH_H4700 1369 default 0 1370 help 1371 Maximum number of GPIOs in the system. 1372 1373 If unsure, leave the default value. 1374 1375config HZ_FIXED 1376 int 1377 default 200 if ARCH_EBSA110 1378 default 128 if SOC_AT91RM9200 1379 default 0 1380 1381choice 1382 depends on HZ_FIXED = 0 1383 prompt "Timer frequency" 1384 1385config HZ_100 1386 bool "100 Hz" 1387 1388config HZ_200 1389 bool "200 Hz" 1390 1391config HZ_250 1392 bool "250 Hz" 1393 1394config HZ_300 1395 bool "300 Hz" 1396 1397config HZ_500 1398 bool "500 Hz" 1399 1400config HZ_1000 1401 bool "1000 Hz" 1402 1403endchoice 1404 1405config HZ 1406 int 1407 default HZ_FIXED if HZ_FIXED != 0 1408 default 100 if HZ_100 1409 default 200 if HZ_200 1410 default 250 if HZ_250 1411 default 300 if HZ_300 1412 default 500 if HZ_500 1413 default 1000 1414 1415config SCHED_HRTICK 1416 def_bool HIGH_RES_TIMERS 1417 1418config THUMB2_KERNEL 1419 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1420 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1421 default y if CPU_THUMBONLY 1422 select ARM_UNWIND 1423 help 1424 By enabling this option, the kernel will be compiled in 1425 Thumb-2 mode. 1426 1427 If unsure, say N. 1428 1429config ARM_PATCH_IDIV 1430 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1431 depends on CPU_32v7 && !XIP_KERNEL 1432 default y 1433 help 1434 The ARM compiler inserts calls to __aeabi_idiv() and 1435 __aeabi_uidiv() when it needs to perform division on signed 1436 and unsigned integers. Some v7 CPUs have support for the sdiv 1437 and udiv instructions that can be used to implement those 1438 functions. 1439 1440 Enabling this option allows the kernel to modify itself to 1441 replace the first two instructions of these library functions 1442 with the sdiv or udiv plus "bx lr" instructions when the CPU 1443 it is running on supports them. Typically this will be faster 1444 and less power intensive than running the original library 1445 code to do integer division. 1446 1447config AEABI 1448 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1449 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1450 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1451 help 1452 This option allows for the kernel to be compiled using the latest 1453 ARM ABI (aka EABI). This is only useful if you are using a user 1454 space environment that is also compiled with EABI. 1455 1456 Since there are major incompatibilities between the legacy ABI and 1457 EABI, especially with regard to structure member alignment, this 1458 option also changes the kernel syscall calling convention to 1459 disambiguate both ABIs and allow for backward compatibility support 1460 (selected with CONFIG_OABI_COMPAT). 1461 1462 To use this you need GCC version 4.0.0 or later. 1463 1464config OABI_COMPAT 1465 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1466 depends on AEABI && !THUMB2_KERNEL 1467 help 1468 This option preserves the old syscall interface along with the 1469 new (ARM EABI) one. It also provides a compatibility layer to 1470 intercept syscalls that have structure arguments which layout 1471 in memory differs between the legacy ABI and the new ARM EABI 1472 (only for non "thumb" binaries). This option adds a tiny 1473 overhead to all syscalls and produces a slightly larger kernel. 1474 1475 The seccomp filter system will not be available when this is 1476 selected, since there is no way yet to sensibly distinguish 1477 between calling conventions during filtering. 1478 1479 If you know you'll be using only pure EABI user space then you 1480 can say N here. If this option is not selected and you attempt 1481 to execute a legacy ABI binary then the result will be 1482 UNPREDICTABLE (in fact it can be predicted that it won't work 1483 at all). If in doubt say N. 1484 1485config ARCH_HAS_HOLES_MEMORYMODEL 1486 bool 1487 1488config ARCH_SELECT_MEMORY_MODEL 1489 bool 1490 1491config ARCH_FLATMEM_ENABLE 1492 bool 1493 1494config ARCH_SPARSEMEM_ENABLE 1495 bool 1496 select SPARSEMEM_STATIC if SPARSEMEM 1497 1498config HAVE_ARCH_PFN_VALID 1499 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1500 1501config HIGHMEM 1502 bool "High Memory Support" 1503 depends on MMU 1504 help 1505 The address space of ARM processors is only 4 Gigabytes large 1506 and it has to accommodate user address space, kernel address 1507 space as well as some memory mapped IO. That means that, if you 1508 have a large amount of physical memory and/or IO, not all of the 1509 memory can be "permanently mapped" by the kernel. The physical 1510 memory that is not permanently mapped is called "high memory". 1511 1512 Depending on the selected kernel/user memory split, minimum 1513 vmalloc space and actual amount of RAM, you may not need this 1514 option which should result in a slightly faster kernel. 1515 1516 If unsure, say n. 1517 1518config HIGHPTE 1519 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1520 depends on HIGHMEM 1521 default y 1522 help 1523 The VM uses one page of physical memory for each page table. 1524 For systems with a lot of processes, this can use a lot of 1525 precious low memory, eventually leading to low memory being 1526 consumed by page tables. Setting this option will allow 1527 user-space 2nd level page tables to reside in high memory. 1528 1529config CPU_SW_DOMAIN_PAN 1530 bool "Enable use of CPU domains to implement privileged no-access" 1531 depends on MMU && !ARM_LPAE 1532 default y 1533 help 1534 Increase kernel security by ensuring that normal kernel accesses 1535 are unable to access userspace addresses. This can help prevent 1536 use-after-free bugs becoming an exploitable privilege escalation 1537 by ensuring that magic values (such as LIST_POISON) will always 1538 fault when dereferenced. 1539 1540 CPUs with low-vector mappings use a best-efforts implementation. 1541 Their lower 1MB needs to remain accessible for the vectors, but 1542 the remainder of userspace will become appropriately inaccessible. 1543 1544config HW_PERF_EVENTS 1545 def_bool y 1546 depends on ARM_PMU 1547 1548config SYS_SUPPORTS_HUGETLBFS 1549 def_bool y 1550 depends on ARM_LPAE 1551 1552config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1553 def_bool y 1554 depends on ARM_LPAE 1555 1556config ARCH_WANT_GENERAL_HUGETLB 1557 def_bool y 1558 1559config ARM_MODULE_PLTS 1560 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1561 depends on MODULES 1562 default y 1563 help 1564 Allocate PLTs when loading modules so that jumps and calls whose 1565 targets are too far away for their relative offsets to be encoded 1566 in the instructions themselves can be bounced via veneers in the 1567 module's PLT. This allows modules to be allocated in the generic 1568 vmalloc area after the dedicated module memory area has been 1569 exhausted. The modules will use slightly more memory, but after 1570 rounding up to page size, the actual memory footprint is usually 1571 the same. 1572 1573 Disabling this is usually safe for small single-platform 1574 configurations. If unsure, say y. 1575 1576config FORCE_MAX_ZONEORDER 1577 int "Maximum zone order" 1578 default "12" if SOC_AM33XX 1579 default "9" if SA1111 || ARCH_EFM32 1580 default "11" 1581 help 1582 The kernel memory allocator divides physically contiguous memory 1583 blocks into "zones", where each zone is a power of two number of 1584 pages. This option selects the largest power of two that the kernel 1585 keeps in the memory allocator. If you need to allocate very large 1586 blocks of physically contiguous memory, then you may need to 1587 increase this value. 1588 1589 This config option is actually maximum order plus one. For example, 1590 a value of 11 means that the largest free memory block is 2^10 pages. 1591 1592config ALIGNMENT_TRAP 1593 bool 1594 depends on CPU_CP15_MMU 1595 default y if !ARCH_EBSA110 1596 select HAVE_PROC_CPU if PROC_FS 1597 help 1598 ARM processors cannot fetch/store information which is not 1599 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1600 address divisible by 4. On 32-bit ARM processors, these non-aligned 1601 fetch/store instructions will be emulated in software if you say 1602 here, which has a severe performance impact. This is necessary for 1603 correct operation of some network protocols. With an IP-only 1604 configuration it is safe to say N, otherwise say Y. 1605 1606config UACCESS_WITH_MEMCPY 1607 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1608 depends on MMU 1609 default y if CPU_FEROCEON 1610 help 1611 Implement faster copy_to_user and clear_user methods for CPU 1612 cores where a 8-word STM instruction give significantly higher 1613 memory write throughput than a sequence of individual 32bit stores. 1614 1615 A possible side effect is a slight increase in scheduling latency 1616 between threads sharing the same address space if they invoke 1617 such copy operations with large buffers. 1618 1619 However, if the CPU data cache is using a write-allocate mode, 1620 this option is unlikely to provide any performance gain. 1621 1622config PARAVIRT 1623 bool "Enable paravirtualization code" 1624 help 1625 This changes the kernel so it can modify itself when it is run 1626 under a hypervisor, potentially improving performance significantly 1627 over full virtualization. 1628 1629config PARAVIRT_TIME_ACCOUNTING 1630 bool "Paravirtual steal time accounting" 1631 select PARAVIRT 1632 help 1633 Select this option to enable fine granularity task steal time 1634 accounting. Time spent executing other tasks in parallel with 1635 the current vCPU is discounted from the vCPU power. To account for 1636 that, there can be a small performance impact. 1637 1638 If in doubt, say N here. 1639 1640config XEN_DOM0 1641 def_bool y 1642 depends on XEN 1643 1644config XEN 1645 bool "Xen guest support on ARM" 1646 depends on ARM && AEABI && OF 1647 depends on CPU_V7 && !CPU_V6 1648 depends on !GENERIC_ATOMIC64 1649 depends on MMU 1650 select ARCH_DMA_ADDR_T_64BIT 1651 select ARM_PSCI 1652 select SWIOTLB 1653 select SWIOTLB_XEN 1654 select PARAVIRT 1655 help 1656 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1657 1658config STACKPROTECTOR_PER_TASK 1659 bool "Use a unique stack canary value for each task" 1660 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1661 select GCC_PLUGIN_ARM_SSP_PER_TASK 1662 default y 1663 help 1664 Due to the fact that GCC uses an ordinary symbol reference from 1665 which to load the value of the stack canary, this value can only 1666 change at reboot time on SMP systems, and all tasks running in the 1667 kernel's address space are forced to use the same canary value for 1668 the entire duration that the system is up. 1669 1670 Enable this option to switch to a different method that uses a 1671 different canary value for each task. 1672 1673endmenu 1674 1675menu "Boot options" 1676 1677config USE_OF 1678 bool "Flattened Device Tree support" 1679 select IRQ_DOMAIN 1680 select OF 1681 help 1682 Include support for flattened device tree machine descriptions. 1683 1684config ATAGS 1685 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1686 default y 1687 help 1688 This is the traditional way of passing data to the kernel at boot 1689 time. If you are solely relying on the flattened device tree (or 1690 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1691 to remove ATAGS support from your kernel binary. If unsure, 1692 leave this to y. 1693 1694config DEPRECATED_PARAM_STRUCT 1695 bool "Provide old way to pass kernel parameters" 1696 depends on ATAGS 1697 help 1698 This was deprecated in 2001 and announced to live on for 5 years. 1699 Some old boot loaders still use this way. 1700 1701# Compressed boot loader in ROM. Yes, we really want to ask about 1702# TEXT and BSS so we preserve their values in the config files. 1703config ZBOOT_ROM_TEXT 1704 hex "Compressed ROM boot loader base address" 1705 default 0x0 1706 help 1707 The physical address at which the ROM-able zImage is to be 1708 placed in the target. Platforms which normally make use of 1709 ROM-able zImage formats normally set this to a suitable 1710 value in their defconfig file. 1711 1712 If ZBOOT_ROM is not enabled, this has no effect. 1713 1714config ZBOOT_ROM_BSS 1715 hex "Compressed ROM boot loader BSS address" 1716 default 0x0 1717 help 1718 The base address of an area of read/write memory in the target 1719 for the ROM-able zImage which must be available while the 1720 decompressor is running. It must be large enough to hold the 1721 entire decompressed kernel plus an additional 128 KiB. 1722 Platforms which normally make use of ROM-able zImage formats 1723 normally set this to a suitable value in their defconfig file. 1724 1725 If ZBOOT_ROM is not enabled, this has no effect. 1726 1727config ZBOOT_ROM 1728 bool "Compressed boot loader in ROM/flash" 1729 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1730 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1731 help 1732 Say Y here if you intend to execute your compressed kernel image 1733 (zImage) directly from ROM or flash. If unsure, say N. 1734 1735config ARM_APPENDED_DTB 1736 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1737 depends on OF 1738 help 1739 With this option, the boot code will look for a device tree binary 1740 (DTB) appended to zImage 1741 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1742 1743 This is meant as a backward compatibility convenience for those 1744 systems with a bootloader that can't be upgraded to accommodate 1745 the documented boot protocol using a device tree. 1746 1747 Beware that there is very little in terms of protection against 1748 this option being confused by leftover garbage in memory that might 1749 look like a DTB header after a reboot if no actual DTB is appended 1750 to zImage. Do not leave this option active in a production kernel 1751 if you don't intend to always append a DTB. Proper passing of the 1752 location into r2 of a bootloader provided DTB is always preferable 1753 to this option. 1754 1755config ARM_ATAG_DTB_COMPAT 1756 bool "Supplement the appended DTB with traditional ATAG information" 1757 depends on ARM_APPENDED_DTB 1758 help 1759 Some old bootloaders can't be updated to a DTB capable one, yet 1760 they provide ATAGs with memory configuration, the ramdisk address, 1761 the kernel cmdline string, etc. Such information is dynamically 1762 provided by the bootloader and can't always be stored in a static 1763 DTB. To allow a device tree enabled kernel to be used with such 1764 bootloaders, this option allows zImage to extract the information 1765 from the ATAG list and store it at run time into the appended DTB. 1766 1767choice 1768 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1769 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1770 1771config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1772 bool "Use bootloader kernel arguments if available" 1773 help 1774 Uses the command-line options passed by the boot loader instead of 1775 the device tree bootargs property. If the boot loader doesn't provide 1776 any, the device tree bootargs property will be used. 1777 1778config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1779 bool "Extend with bootloader kernel arguments" 1780 help 1781 The command-line arguments provided by the boot loader will be 1782 appended to the the device tree bootargs property. 1783 1784endchoice 1785 1786config CMDLINE 1787 string "Default kernel command string" 1788 default "" 1789 help 1790 On some architectures (EBSA110 and CATS), there is currently no way 1791 for the boot loader to pass arguments to the kernel. For these 1792 architectures, you should supply some command-line options at build 1793 time by entering them here. As a minimum, you should specify the 1794 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1795 1796choice 1797 prompt "Kernel command line type" if CMDLINE != "" 1798 default CMDLINE_FROM_BOOTLOADER 1799 depends on ATAGS 1800 1801config CMDLINE_FROM_BOOTLOADER 1802 bool "Use bootloader kernel arguments if available" 1803 help 1804 Uses the command-line options passed by the boot loader. If 1805 the boot loader doesn't provide any, the default kernel command 1806 string provided in CMDLINE will be used. 1807 1808config CMDLINE_EXTEND 1809 bool "Extend bootloader kernel arguments" 1810 help 1811 The command-line arguments provided by the boot loader will be 1812 appended to the default kernel command string. 1813 1814config CMDLINE_FORCE 1815 bool "Always use the default kernel command string" 1816 help 1817 Always use the default kernel command string, even if the boot 1818 loader passes other arguments to the kernel. 1819 This is useful if you cannot or don't want to change the 1820 command-line options your boot loader passes to the kernel. 1821endchoice 1822 1823config XIP_KERNEL 1824 bool "Kernel Execute-In-Place from ROM" 1825 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1826 help 1827 Execute-In-Place allows the kernel to run from non-volatile storage 1828 directly addressable by the CPU, such as NOR flash. This saves RAM 1829 space since the text section of the kernel is not loaded from flash 1830 to RAM. Read-write sections, such as the data section and stack, 1831 are still copied to RAM. The XIP kernel is not compressed since 1832 it has to run directly from flash, so it will take more space to 1833 store it. The flash address used to link the kernel object files, 1834 and for storing it, is configuration dependent. Therefore, if you 1835 say Y here, you must know the proper physical address where to 1836 store the kernel image depending on your own flash memory usage. 1837 1838 Also note that the make target becomes "make xipImage" rather than 1839 "make zImage" or "make Image". The final kernel binary to put in 1840 ROM memory will be arch/arm/boot/xipImage. 1841 1842 If unsure, say N. 1843 1844config XIP_PHYS_ADDR 1845 hex "XIP Kernel Physical Location" 1846 depends on XIP_KERNEL 1847 default "0x00080000" 1848 help 1849 This is the physical address in your flash memory the kernel will 1850 be linked for and stored to. This address is dependent on your 1851 own flash usage. 1852 1853config XIP_DEFLATED_DATA 1854 bool "Store kernel .data section compressed in ROM" 1855 depends on XIP_KERNEL 1856 select ZLIB_INFLATE 1857 help 1858 Before the kernel is actually executed, its .data section has to be 1859 copied to RAM from ROM. This option allows for storing that data 1860 in compressed form and decompressed to RAM rather than merely being 1861 copied, saving some precious ROM space. A possible drawback is a 1862 slightly longer boot delay. 1863 1864config KEXEC 1865 bool "Kexec system call (EXPERIMENTAL)" 1866 depends on (!SMP || PM_SLEEP_SMP) 1867 depends on MMU 1868 select KEXEC_CORE 1869 help 1870 kexec is a system call that implements the ability to shutdown your 1871 current kernel, and to start another kernel. It is like a reboot 1872 but it is independent of the system firmware. And like a reboot 1873 you can start any kernel with it, not just Linux. 1874 1875 It is an ongoing process to be certain the hardware in a machine 1876 is properly shutdown, so do not be surprised if this code does not 1877 initially work for you. 1878 1879config ATAGS_PROC 1880 bool "Export atags in procfs" 1881 depends on ATAGS && KEXEC 1882 default y 1883 help 1884 Should the atags used to boot the kernel be exported in an "atags" 1885 file in procfs. Useful with kexec. 1886 1887config CRASH_DUMP 1888 bool "Build kdump crash kernel (EXPERIMENTAL)" 1889 help 1890 Generate crash dump after being started by kexec. This should 1891 be normally only set in special crash dump kernels which are 1892 loaded in the main kernel with kexec-tools into a specially 1893 reserved region and then later executed after a crash by 1894 kdump/kexec. The crash dump kernel must be compiled to a 1895 memory address not used by the main kernel 1896 1897 For more details see Documentation/admin-guide/kdump/kdump.rst 1898 1899config AUTO_ZRELADDR 1900 bool "Auto calculation of the decompressed kernel image address" 1901 help 1902 ZRELADDR is the physical address where the decompressed kernel 1903 image will be placed. If AUTO_ZRELADDR is selected, the address 1904 will be determined at run-time by masking the current IP with 1905 0xf8000000. This assumes the zImage being placed in the first 128MB 1906 from start of memory. 1907 1908config EFI_STUB 1909 bool 1910 1911config EFI 1912 bool "UEFI runtime support" 1913 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1914 select UCS2_STRING 1915 select EFI_PARAMS_FROM_FDT 1916 select EFI_STUB 1917 select EFI_GENERIC_STUB 1918 select EFI_RUNTIME_WRAPPERS 1919 help 1920 This option provides support for runtime services provided 1921 by UEFI firmware (such as non-volatile variables, realtime 1922 clock, and platform reset). A UEFI stub is also provided to 1923 allow the kernel to be booted as an EFI application. This 1924 is only useful for kernels that may run on systems that have 1925 UEFI firmware. 1926 1927config DMI 1928 bool "Enable support for SMBIOS (DMI) tables" 1929 depends on EFI 1930 default y 1931 help 1932 This enables SMBIOS/DMI feature for systems. 1933 1934 This option is only useful on systems that have UEFI firmware. 1935 However, even with this option, the resultant kernel should 1936 continue to boot on existing non-UEFI platforms. 1937 1938 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1939 i.e., the the practice of identifying the platform via DMI to 1940 decide whether certain workarounds for buggy hardware and/or 1941 firmware need to be enabled. This would require the DMI subsystem 1942 to be enabled much earlier than we do on ARM, which is non-trivial. 1943 1944endmenu 1945 1946menu "CPU Power Management" 1947 1948source "drivers/cpufreq/Kconfig" 1949 1950source "drivers/cpuidle/Kconfig" 1951 1952endmenu 1953 1954menu "Floating point emulation" 1955 1956comment "At least one emulation must be selected" 1957 1958config FPE_NWFPE 1959 bool "NWFPE math emulation" 1960 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1961 help 1962 Say Y to include the NWFPE floating point emulator in the kernel. 1963 This is necessary to run most binaries. Linux does not currently 1964 support floating point hardware so you need to say Y here even if 1965 your machine has an FPA or floating point co-processor podule. 1966 1967 You may say N here if you are going to load the Acorn FPEmulator 1968 early in the bootup. 1969 1970config FPE_NWFPE_XP 1971 bool "Support extended precision" 1972 depends on FPE_NWFPE 1973 help 1974 Say Y to include 80-bit support in the kernel floating-point 1975 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1976 Note that gcc does not generate 80-bit operations by default, 1977 so in most cases this option only enlarges the size of the 1978 floating point emulator without any good reason. 1979 1980 You almost surely want to say N here. 1981 1982config FPE_FASTFPE 1983 bool "FastFPE math emulation (EXPERIMENTAL)" 1984 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1985 help 1986 Say Y here to include the FAST floating point emulator in the kernel. 1987 This is an experimental much faster emulator which now also has full 1988 precision for the mantissa. It does not support any exceptions. 1989 It is very simple, and approximately 3-6 times faster than NWFPE. 1990 1991 It should be sufficient for most programs. It may be not suitable 1992 for scientific calculations, but you have to check this for yourself. 1993 If you do not feel you need a faster FP emulation you should better 1994 choose NWFPE. 1995 1996config VFP 1997 bool "VFP-format floating point maths" 1998 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1999 help 2000 Say Y to include VFP support code in the kernel. This is needed 2001 if your hardware includes a VFP unit. 2002 2003 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2004 release notes and additional status information. 2005 2006 Say N if your target does not have VFP hardware. 2007 2008config VFPv3 2009 bool 2010 depends on VFP 2011 default y if CPU_V7 2012 2013config NEON 2014 bool "Advanced SIMD (NEON) Extension support" 2015 depends on VFPv3 && CPU_V7 2016 help 2017 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2018 Extension. 2019 2020config KERNEL_MODE_NEON 2021 bool "Support for NEON in kernel mode" 2022 depends on NEON && AEABI 2023 help 2024 Say Y to include support for NEON in kernel mode. 2025 2026endmenu 2027 2028menu "Power management options" 2029 2030source "kernel/power/Kconfig" 2031 2032config ARCH_SUSPEND_POSSIBLE 2033 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2034 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2035 def_bool y 2036 2037config ARM_CPU_SUSPEND 2038 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2039 depends on ARCH_SUSPEND_POSSIBLE 2040 2041config ARCH_HIBERNATION_POSSIBLE 2042 bool 2043 depends on MMU 2044 default y if ARCH_SUSPEND_POSSIBLE 2045 2046endmenu 2047 2048source "drivers/firmware/Kconfig" 2049 2050if CRYPTO 2051source "arch/arm/crypto/Kconfig" 2052endif 2053 2054source "arch/arm/Kconfig.assembler" 2055