xref: /openbmc/linux/arch/arm/Kconfig (revision 78700c0a)
1config ARM
2	bool
3	default y
4	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5	select ARCH_HAS_DEVMEM_IS_ALLOWED
6	select ARCH_HAS_ELF_RANDOMIZE
7	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8	select ARCH_HAVE_CUSTOM_GPIO_H
9	select ARCH_HAS_GCOV_PROFILE_ALL
10	select ARCH_MIGHT_HAVE_PC_PARPORT
11	select ARCH_SUPPORTS_ATOMIC_RMW
12	select ARCH_USE_BUILTIN_BSWAP
13	select ARCH_USE_CMPXCHG_LOCKREF
14	select ARCH_WANT_IPC_PARSE_VERSION
15	select BUILDTIME_EXTABLE_SORT if MMU
16	select CLONE_BACKWARDS
17	select CPU_PM if (SUSPEND || CPU_IDLE)
18	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19	select EDAC_SUPPORT
20	select EDAC_ATOMIC_SCRUB
21	select GENERIC_ALLOCATOR
22	select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
23	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
24	select GENERIC_EARLY_IOREMAP
25	select GENERIC_IDLE_POLL_SETUP
26	select GENERIC_IRQ_PROBE
27	select GENERIC_IRQ_SHOW
28	select GENERIC_IRQ_SHOW_LEVEL
29	select GENERIC_PCI_IOMAP
30	select GENERIC_SCHED_CLOCK
31	select GENERIC_SMP_IDLE_THREAD
32	select GENERIC_STRNCPY_FROM_USER
33	select GENERIC_STRNLEN_USER
34	select HANDLE_DOMAIN_IRQ
35	select HARDIRQS_SW_RESEND
36	select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
37	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
38	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
39	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
40	select HAVE_ARCH_MMAP_RND_BITS if MMU
41	select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
42	select HAVE_ARCH_TRACEHOOK
43	select HAVE_ARM_SMCCC if CPU_V7
44	select HAVE_CBPF_JIT
45	select HAVE_CC_STACKPROTECTOR
46	select HAVE_CONTEXT_TRACKING
47	select HAVE_C_RECORDMCOUNT
48	select HAVE_DEBUG_KMEMLEAK
49	select HAVE_DMA_API_DEBUG
50	select HAVE_DMA_CONTIGUOUS if MMU
51	select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
52	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53	select HAVE_EXIT_THREAD
54	select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
55	select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
56	select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
57	select HAVE_GENERIC_DMA_COHERENT
58	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
59	select HAVE_IDE if PCI || ISA || PCMCIA
60	select HAVE_IRQ_TIME_ACCOUNTING
61	select HAVE_KERNEL_GZIP
62	select HAVE_KERNEL_LZ4
63	select HAVE_KERNEL_LZMA
64	select HAVE_KERNEL_LZO
65	select HAVE_KERNEL_XZ
66	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
67	select HAVE_KRETPROBES if (HAVE_KPROBES)
68	select HAVE_MEMBLOCK
69	select HAVE_MOD_ARCH_SPECIFIC
70	select HAVE_NMI
71	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
72	select HAVE_OPTPROBES if !THUMB2_KERNEL
73	select HAVE_PERF_EVENTS
74	select HAVE_PERF_REGS
75	select HAVE_PERF_USER_STACK_DUMP
76	select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
77	select HAVE_REGS_AND_STACK_ACCESS_API
78	select HAVE_SYSCALL_TRACEPOINTS
79	select HAVE_UID16
80	select HAVE_VIRT_CPU_ACCOUNTING_GEN
81	select IRQ_FORCED_THREADING
82	select MODULES_USE_ELF_REL
83	select NO_BOOTMEM
84	select OF_EARLY_FLATTREE if OF
85	select OF_RESERVED_MEM if OF
86	select OLD_SIGACTION
87	select OLD_SIGSUSPEND3
88	select PERF_USE_VMALLOC
89	select RTC_LIB
90	select SYS_SUPPORTS_APM_EMULATION
91	# Above selects are sorted alphabetically; please add new ones
92	# according to that.  Thanks.
93	help
94	  The ARM series is a line of low-power-consumption RISC chip designs
95	  licensed by ARM Ltd and targeted at embedded applications and
96	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
97	  manufactured, but legacy ARM-based PC hardware remains popular in
98	  Europe.  There is an ARM Linux project with a web page at
99	  <http://www.arm.linux.org.uk/>.
100
101config ARM_HAS_SG_CHAIN
102	select ARCH_HAS_SG_CHAIN
103	bool
104
105config NEED_SG_DMA_LENGTH
106	bool
107
108config ARM_DMA_USE_IOMMU
109	bool
110	select ARM_HAS_SG_CHAIN
111	select NEED_SG_DMA_LENGTH
112
113if ARM_DMA_USE_IOMMU
114
115config ARM_DMA_IOMMU_ALIGNMENT
116	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
117	range 4 9
118	default 8
119	help
120	  DMA mapping framework by default aligns all buffers to the smallest
121	  PAGE_SIZE order which is greater than or equal to the requested buffer
122	  size. This works well for buffers up to a few hundreds kilobytes, but
123	  for larger buffers it just a waste of address space. Drivers which has
124	  relatively small addressing window (like 64Mib) might run out of
125	  virtual space with just a few allocations.
126
127	  With this parameter you can specify the maximum PAGE_SIZE order for
128	  DMA IOMMU buffers. Larger buffers will be aligned only to this
129	  specified order. The order is expressed as a power of two multiplied
130	  by the PAGE_SIZE.
131
132endif
133
134config MIGHT_HAVE_PCI
135	bool
136
137config SYS_SUPPORTS_APM_EMULATION
138	bool
139
140config HAVE_TCM
141	bool
142	select GENERIC_ALLOCATOR
143
144config HAVE_PROC_CPU
145	bool
146
147config NO_IOPORT_MAP
148	bool
149
150config EISA
151	bool
152	---help---
153	  The Extended Industry Standard Architecture (EISA) bus was
154	  developed as an open alternative to the IBM MicroChannel bus.
155
156	  The EISA bus provided some of the features of the IBM MicroChannel
157	  bus while maintaining backward compatibility with cards made for
158	  the older ISA bus.  The EISA bus saw limited use between 1988 and
159	  1995 when it was made obsolete by the PCI bus.
160
161	  Say Y here if you are building a kernel for an EISA-based machine.
162
163	  Otherwise, say N.
164
165config SBUS
166	bool
167
168config STACKTRACE_SUPPORT
169	bool
170	default y
171
172config LOCKDEP_SUPPORT
173	bool
174	default y
175
176config TRACE_IRQFLAGS_SUPPORT
177	bool
178	default !CPU_V7M
179
180config RWSEM_XCHGADD_ALGORITHM
181	bool
182	default y
183
184config ARCH_HAS_ILOG2_U32
185	bool
186
187config ARCH_HAS_ILOG2_U64
188	bool
189
190config ARCH_HAS_BANDGAP
191	bool
192
193config FIX_EARLYCON_MEM
194	def_bool y if MMU
195
196config GENERIC_HWEIGHT
197	bool
198	default y
199
200config GENERIC_CALIBRATE_DELAY
201	bool
202	default y
203
204config ARCH_MAY_HAVE_PC_FDC
205	bool
206
207config ZONE_DMA
208	bool
209
210config NEED_DMA_MAP_STATE
211       def_bool y
212
213config ARCH_SUPPORTS_UPROBES
214	def_bool y
215
216config ARCH_HAS_DMA_SET_COHERENT_MASK
217	bool
218
219config GENERIC_ISA_DMA
220	bool
221
222config FIQ
223	bool
224
225config NEED_RET_TO_USER
226	bool
227
228config ARCH_MTD_XIP
229	bool
230
231config VECTORS_BASE
232	hex
233	default 0xffff0000 if MMU || CPU_HIGH_VECTOR
234	default DRAM_BASE if REMAP_VECTORS_TO_RAM
235	default 0x00000000
236	help
237	  The base address of exception vectors.  This must be two pages
238	  in size.
239
240config ARM_PATCH_PHYS_VIRT
241	bool "Patch physical to virtual translations at runtime" if EMBEDDED
242	default y
243	depends on !XIP_KERNEL && MMU
244	help
245	  Patch phys-to-virt and virt-to-phys translation functions at
246	  boot and module load time according to the position of the
247	  kernel in system memory.
248
249	  This can only be used with non-XIP MMU kernels where the base
250	  of physical memory is at a 16MB boundary.
251
252	  Only disable this option if you know that you do not require
253	  this feature (eg, building a kernel for a single machine) and
254	  you need to shrink the kernel to the minimal size.
255
256config NEED_MACH_IO_H
257	bool
258	help
259	  Select this when mach/io.h is required to provide special
260	  definitions for this platform.  The need for mach/io.h should
261	  be avoided when possible.
262
263config NEED_MACH_MEMORY_H
264	bool
265	help
266	  Select this when mach/memory.h is required to provide special
267	  definitions for this platform.  The need for mach/memory.h should
268	  be avoided when possible.
269
270config PHYS_OFFSET
271	hex "Physical address of main memory" if MMU
272	depends on !ARM_PATCH_PHYS_VIRT
273	default DRAM_BASE if !MMU
274	default 0x00000000 if ARCH_EBSA110 || \
275			ARCH_FOOTBRIDGE || \
276			ARCH_INTEGRATOR || \
277			ARCH_IOP13XX || \
278			ARCH_KS8695 || \
279			(ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
280	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
281	default 0x20000000 if ARCH_S5PV210
282	default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
283	default 0xc0000000 if ARCH_SA1100
284	help
285	  Please provide the physical address corresponding to the
286	  location of main memory in your system.
287
288config GENERIC_BUG
289	def_bool y
290	depends on BUG
291
292config PGTABLE_LEVELS
293	int
294	default 3 if ARM_LPAE
295	default 2
296
297source "init/Kconfig"
298
299source "kernel/Kconfig.freezer"
300
301menu "System Type"
302
303config MMU
304	bool "MMU-based Paged Memory Management Support"
305	default y
306	help
307	  Select if you want MMU-based virtualised addressing space
308	  support by paged memory management. If unsure, say 'Y'.
309
310config ARCH_MMAP_RND_BITS_MIN
311	default 8
312
313config ARCH_MMAP_RND_BITS_MAX
314	default 14 if PAGE_OFFSET=0x40000000
315	default 15 if PAGE_OFFSET=0x80000000
316	default 16
317
318#
319# The "ARM system type" choice list is ordered alphabetically by option
320# text.  Please add new entries in the option alphabetic order.
321#
322choice
323	prompt "ARM system type"
324	default ARM_SINGLE_ARMV7M if !MMU
325	default ARCH_MULTIPLATFORM if MMU
326
327config ARCH_MULTIPLATFORM
328	bool "Allow multiple platforms to be selected"
329	depends on MMU
330	select ARCH_WANT_OPTIONAL_GPIOLIB
331	select ARM_HAS_SG_CHAIN
332	select ARM_PATCH_PHYS_VIRT
333	select AUTO_ZRELADDR
334	select CLKSRC_OF
335	select COMMON_CLK
336	select GENERIC_CLOCKEVENTS
337	select MIGHT_HAVE_PCI
338	select MULTI_IRQ_HANDLER
339	select SPARSE_IRQ
340	select USE_OF
341
342config ARM_SINGLE_ARMV7M
343	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
344	depends on !MMU
345	select ARCH_WANT_OPTIONAL_GPIOLIB
346	select ARM_NVIC
347	select AUTO_ZRELADDR
348	select CLKSRC_OF
349	select COMMON_CLK
350	select CPU_V7M
351	select GENERIC_CLOCKEVENTS
352	select NO_IOPORT_MAP
353	select SPARSE_IRQ
354	select USE_OF
355
356
357config ARCH_CLPS711X
358	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
359	select ARCH_REQUIRE_GPIOLIB
360	select AUTO_ZRELADDR
361	select CLKSRC_MMIO
362	select COMMON_CLK
363	select CPU_ARM720T
364	select GENERIC_CLOCKEVENTS
365	select MFD_SYSCON
366	select SOC_BUS
367	help
368	  Support for Cirrus Logic 711x/721x/731x based boards.
369
370config ARCH_GEMINI
371	bool "Cortina Systems Gemini"
372	select ARCH_REQUIRE_GPIOLIB
373	select CLKSRC_MMIO
374	select CPU_FA526
375	select GENERIC_CLOCKEVENTS
376	help
377	  Support for the Cortina Systems Gemini family SoCs
378
379config ARCH_EBSA110
380	bool "EBSA-110"
381	select ARCH_USES_GETTIMEOFFSET
382	select CPU_SA110
383	select ISA
384	select NEED_MACH_IO_H
385	select NEED_MACH_MEMORY_H
386	select NO_IOPORT_MAP
387	help
388	  This is an evaluation board for the StrongARM processor available
389	  from Digital. It has limited hardware on-board, including an
390	  Ethernet interface, two PCMCIA sockets, two serial ports and a
391	  parallel port.
392
393config ARCH_EP93XX
394	bool "EP93xx-based"
395	select ARCH_HAS_HOLES_MEMORYMODEL
396	select ARCH_REQUIRE_GPIOLIB
397	select ARM_AMBA
398	select ARM_PATCH_PHYS_VIRT
399	select ARM_VIC
400	select AUTO_ZRELADDR
401	select CLKDEV_LOOKUP
402	select CLKSRC_MMIO
403	select CPU_ARM920T
404	select GENERIC_CLOCKEVENTS
405	help
406	  This enables support for the Cirrus EP93xx series of CPUs.
407
408config ARCH_FOOTBRIDGE
409	bool "FootBridge"
410	select CPU_SA110
411	select FOOTBRIDGE
412	select GENERIC_CLOCKEVENTS
413	select HAVE_IDE
414	select NEED_MACH_IO_H if !MMU
415	select NEED_MACH_MEMORY_H
416	help
417	  Support for systems based on the DC21285 companion chip
418	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
419
420config ARCH_NETX
421	bool "Hilscher NetX based"
422	select ARM_VIC
423	select CLKSRC_MMIO
424	select CPU_ARM926T
425	select GENERIC_CLOCKEVENTS
426	help
427	  This enables support for systems based on the Hilscher NetX Soc
428
429config ARCH_IOP13XX
430	bool "IOP13xx-based"
431	depends on MMU
432	select CPU_XSC3
433	select NEED_MACH_MEMORY_H
434	select NEED_RET_TO_USER
435	select PCI
436	select PLAT_IOP
437	select VMSPLIT_1G
438	select SPARSE_IRQ
439	help
440	  Support for Intel's IOP13XX (XScale) family of processors.
441
442config ARCH_IOP32X
443	bool "IOP32x-based"
444	depends on MMU
445	select ARCH_REQUIRE_GPIOLIB
446	select CPU_XSCALE
447	select GPIO_IOP
448	select NEED_RET_TO_USER
449	select PCI
450	select PLAT_IOP
451	help
452	  Support for Intel's 80219 and IOP32X (XScale) family of
453	  processors.
454
455config ARCH_IOP33X
456	bool "IOP33x-based"
457	depends on MMU
458	select ARCH_REQUIRE_GPIOLIB
459	select CPU_XSCALE
460	select GPIO_IOP
461	select NEED_RET_TO_USER
462	select PCI
463	select PLAT_IOP
464	help
465	  Support for Intel's IOP33X (XScale) family of processors.
466
467config ARCH_IXP4XX
468	bool "IXP4xx-based"
469	depends on MMU
470	select ARCH_HAS_DMA_SET_COHERENT_MASK
471	select ARCH_REQUIRE_GPIOLIB
472	select ARCH_SUPPORTS_BIG_ENDIAN
473	select CLKSRC_MMIO
474	select CPU_XSCALE
475	select DMABOUNCE if PCI
476	select GENERIC_CLOCKEVENTS
477	select MIGHT_HAVE_PCI
478	select NEED_MACH_IO_H
479	select USB_EHCI_BIG_ENDIAN_DESC
480	select USB_EHCI_BIG_ENDIAN_MMIO
481	help
482	  Support for Intel's IXP4XX (XScale) family of processors.
483
484config ARCH_DOVE
485	bool "Marvell Dove"
486	select ARCH_REQUIRE_GPIOLIB
487	select CPU_PJ4
488	select GENERIC_CLOCKEVENTS
489	select MIGHT_HAVE_PCI
490	select MULTI_IRQ_HANDLER
491	select MVEBU_MBUS
492	select PINCTRL
493	select PINCTRL_DOVE
494	select PLAT_ORION_LEGACY
495	select SPARSE_IRQ
496	select PM_GENERIC_DOMAINS if PM
497	help
498	  Support for the Marvell Dove SoC 88AP510
499
500config ARCH_KS8695
501	bool "Micrel/Kendin KS8695"
502	select ARCH_REQUIRE_GPIOLIB
503	select CLKSRC_MMIO
504	select CPU_ARM922T
505	select GENERIC_CLOCKEVENTS
506	select NEED_MACH_MEMORY_H
507	help
508	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
509	  System-on-Chip devices.
510
511config ARCH_W90X900
512	bool "Nuvoton W90X900 CPU"
513	select ARCH_REQUIRE_GPIOLIB
514	select CLKDEV_LOOKUP
515	select CLKSRC_MMIO
516	select CPU_ARM926T
517	select GENERIC_CLOCKEVENTS
518	help
519	  Support for Nuvoton (Winbond logic dept.) ARM9 processor,
520	  At present, the w90x900 has been renamed nuc900, regarding
521	  the ARM series product line, you can login the following
522	  link address to know more.
523
524	  <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
525		ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
526
527config ARCH_LPC32XX
528	bool "NXP LPC32XX"
529	select ARCH_REQUIRE_GPIOLIB
530	select ARM_AMBA
531	select CLKDEV_LOOKUP
532	select CLKSRC_LPC32XX
533	select COMMON_CLK
534	select CPU_ARM926T
535	select GENERIC_CLOCKEVENTS
536	select MULTI_IRQ_HANDLER
537	select SPARSE_IRQ
538	select USE_OF
539	help
540	  Support for the NXP LPC32XX family of processors
541
542config ARCH_PXA
543	bool "PXA2xx/PXA3xx-based"
544	depends on MMU
545	select ARCH_MTD_XIP
546	select ARCH_REQUIRE_GPIOLIB
547	select ARM_CPU_SUSPEND if PM
548	select AUTO_ZRELADDR
549	select COMMON_CLK
550	select CLKDEV_LOOKUP
551	select CLKSRC_PXA
552	select CLKSRC_MMIO
553	select CLKSRC_OF
554	select CPU_XSCALE if !CPU_XSC3
555	select GENERIC_CLOCKEVENTS
556	select GPIO_PXA
557	select HAVE_IDE
558	select IRQ_DOMAIN
559	select MULTI_IRQ_HANDLER
560	select PLAT_PXA
561	select SPARSE_IRQ
562	help
563	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
564
565config ARCH_RPC
566	bool "RiscPC"
567	depends on MMU
568	select ARCH_ACORN
569	select ARCH_MAY_HAVE_PC_FDC
570	select ARCH_SPARSEMEM_ENABLE
571	select ARCH_USES_GETTIMEOFFSET
572	select CPU_SA110
573	select FIQ
574	select HAVE_IDE
575	select HAVE_PATA_PLATFORM
576	select ISA_DMA_API
577	select NEED_MACH_IO_H
578	select NEED_MACH_MEMORY_H
579	select NO_IOPORT_MAP
580	help
581	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
582	  CD-ROM interface, serial and parallel port, and the floppy drive.
583
584config ARCH_SA1100
585	bool "SA1100-based"
586	select ARCH_MTD_XIP
587	select ARCH_REQUIRE_GPIOLIB
588	select ARCH_SPARSEMEM_ENABLE
589	select CLKDEV_LOOKUP
590	select CLKSRC_MMIO
591	select CLKSRC_PXA
592	select CLKSRC_OF if OF
593	select CPU_FREQ
594	select CPU_SA1100
595	select GENERIC_CLOCKEVENTS
596	select HAVE_IDE
597	select IRQ_DOMAIN
598	select ISA
599	select MULTI_IRQ_HANDLER
600	select NEED_MACH_MEMORY_H
601	select SPARSE_IRQ
602	help
603	  Support for StrongARM 11x0 based boards.
604
605config ARCH_S3C24XX
606	bool "Samsung S3C24XX SoCs"
607	select ARCH_REQUIRE_GPIOLIB
608	select ATAGS
609	select CLKDEV_LOOKUP
610	select CLKSRC_SAMSUNG_PWM
611	select GENERIC_CLOCKEVENTS
612	select GPIO_SAMSUNG
613	select HAVE_S3C2410_I2C if I2C
614	select HAVE_S3C2410_WATCHDOG if WATCHDOG
615	select HAVE_S3C_RTC if RTC_CLASS
616	select MULTI_IRQ_HANDLER
617	select NEED_MACH_IO_H
618	select SAMSUNG_ATAGS
619	help
620	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
621	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
622	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
623	  Samsung SMDK2410 development board (and derivatives).
624
625config ARCH_DAVINCI
626	bool "TI DaVinci"
627	select ARCH_HAS_HOLES_MEMORYMODEL
628	select ARCH_REQUIRE_GPIOLIB
629	select CLKDEV_LOOKUP
630	select CPU_ARM926T
631	select GENERIC_ALLOCATOR
632	select GENERIC_CLOCKEVENTS
633	select GENERIC_IRQ_CHIP
634	select HAVE_IDE
635	select USE_OF
636	select ZONE_DMA
637	help
638	  Support for TI's DaVinci platform.
639
640config ARCH_OMAP1
641	bool "TI OMAP1"
642	depends on MMU
643	select ARCH_HAS_HOLES_MEMORYMODEL
644	select ARCH_OMAP
645	select ARCH_REQUIRE_GPIOLIB
646	select CLKDEV_LOOKUP
647	select CLKSRC_MMIO
648	select GENERIC_CLOCKEVENTS
649	select GENERIC_IRQ_CHIP
650	select HAVE_IDE
651	select IRQ_DOMAIN
652	select MULTI_IRQ_HANDLER
653	select NEED_MACH_IO_H if PCCARD
654	select NEED_MACH_MEMORY_H
655	select SPARSE_IRQ
656	help
657	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
658
659endchoice
660
661menu "Multiple platform selection"
662	depends on ARCH_MULTIPLATFORM
663
664comment "CPU Core family selection"
665
666config ARCH_MULTI_V4
667	bool "ARMv4 based platforms (FA526)"
668	depends on !ARCH_MULTI_V6_V7
669	select ARCH_MULTI_V4_V5
670	select CPU_FA526
671
672config ARCH_MULTI_V4T
673	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
674	depends on !ARCH_MULTI_V6_V7
675	select ARCH_MULTI_V4_V5
676	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
677		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
678		CPU_ARM925T || CPU_ARM940T)
679
680config ARCH_MULTI_V5
681	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
682	depends on !ARCH_MULTI_V6_V7
683	select ARCH_MULTI_V4_V5
684	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
685		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
686		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
687
688config ARCH_MULTI_V4_V5
689	bool
690
691config ARCH_MULTI_V6
692	bool "ARMv6 based platforms (ARM11)"
693	select ARCH_MULTI_V6_V7
694	select CPU_V6K
695
696config ARCH_MULTI_V7
697	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
698	default y
699	select ARCH_MULTI_V6_V7
700	select CPU_V7
701	select HAVE_SMP
702
703config ARCH_MULTI_V6_V7
704	bool
705	select MIGHT_HAVE_CACHE_L2X0
706
707config ARCH_MULTI_CPU_AUTO
708	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
709	select ARCH_MULTI_V5
710
711endmenu
712
713config ARCH_VIRT
714	bool "Dummy Virtual Machine"
715	depends on ARCH_MULTI_V7
716	select ARM_AMBA
717	select ARM_GIC
718	select ARM_GIC_V2M if PCI_MSI
719	select ARM_GIC_V3
720	select ARM_PSCI
721	select HAVE_ARM_ARCH_TIMER
722
723#
724# This is sorted alphabetically by mach-* pathname.  However, plat-*
725# Kconfigs may be included either alphabetically (according to the
726# plat- suffix) or along side the corresponding mach-* source.
727#
728source "arch/arm/mach-mvebu/Kconfig"
729
730source "arch/arm/mach-alpine/Kconfig"
731
732source "arch/arm/mach-artpec/Kconfig"
733
734source "arch/arm/mach-asm9260/Kconfig"
735
736source "arch/arm/mach-at91/Kconfig"
737
738source "arch/arm/mach-axxia/Kconfig"
739
740source "arch/arm/mach-bcm/Kconfig"
741
742source "arch/arm/mach-berlin/Kconfig"
743
744source "arch/arm/mach-clps711x/Kconfig"
745
746source "arch/arm/mach-cns3xxx/Kconfig"
747
748source "arch/arm/mach-davinci/Kconfig"
749
750source "arch/arm/mach-digicolor/Kconfig"
751
752source "arch/arm/mach-dove/Kconfig"
753
754source "arch/arm/mach-ep93xx/Kconfig"
755
756source "arch/arm/mach-footbridge/Kconfig"
757
758source "arch/arm/mach-gemini/Kconfig"
759
760source "arch/arm/mach-highbank/Kconfig"
761
762source "arch/arm/mach-hisi/Kconfig"
763
764source "arch/arm/mach-integrator/Kconfig"
765
766source "arch/arm/mach-iop32x/Kconfig"
767
768source "arch/arm/mach-iop33x/Kconfig"
769
770source "arch/arm/mach-iop13xx/Kconfig"
771
772source "arch/arm/mach-ixp4xx/Kconfig"
773
774source "arch/arm/mach-keystone/Kconfig"
775
776source "arch/arm/mach-ks8695/Kconfig"
777
778source "arch/arm/mach-meson/Kconfig"
779
780source "arch/arm/mach-moxart/Kconfig"
781
782source "arch/arm/mach-aspeed/Kconfig"
783
784source "arch/arm/mach-mv78xx0/Kconfig"
785
786source "arch/arm/mach-imx/Kconfig"
787
788source "arch/arm/mach-mediatek/Kconfig"
789
790source "arch/arm/mach-mxs/Kconfig"
791
792source "arch/arm/mach-netx/Kconfig"
793
794source "arch/arm/mach-nomadik/Kconfig"
795
796source "arch/arm/mach-nspire/Kconfig"
797
798source "arch/arm/plat-omap/Kconfig"
799
800source "arch/arm/mach-omap1/Kconfig"
801
802source "arch/arm/mach-omap2/Kconfig"
803
804source "arch/arm/mach-orion5x/Kconfig"
805
806source "arch/arm/mach-picoxcell/Kconfig"
807
808source "arch/arm/mach-pxa/Kconfig"
809source "arch/arm/plat-pxa/Kconfig"
810
811source "arch/arm/mach-mmp/Kconfig"
812
813source "arch/arm/mach-oxnas/Kconfig"
814
815source "arch/arm/mach-qcom/Kconfig"
816
817source "arch/arm/mach-realview/Kconfig"
818
819source "arch/arm/mach-rockchip/Kconfig"
820
821source "arch/arm/mach-sa1100/Kconfig"
822
823source "arch/arm/mach-socfpga/Kconfig"
824
825source "arch/arm/mach-spear/Kconfig"
826
827source "arch/arm/mach-sti/Kconfig"
828
829source "arch/arm/mach-s3c24xx/Kconfig"
830
831source "arch/arm/mach-s3c64xx/Kconfig"
832
833source "arch/arm/mach-s5pv210/Kconfig"
834
835source "arch/arm/mach-exynos/Kconfig"
836source "arch/arm/plat-samsung/Kconfig"
837
838source "arch/arm/mach-shmobile/Kconfig"
839
840source "arch/arm/mach-sunxi/Kconfig"
841
842source "arch/arm/mach-prima2/Kconfig"
843
844source "arch/arm/mach-tango/Kconfig"
845
846source "arch/arm/mach-tegra/Kconfig"
847
848source "arch/arm/mach-u300/Kconfig"
849
850source "arch/arm/mach-uniphier/Kconfig"
851
852source "arch/arm/mach-ux500/Kconfig"
853
854source "arch/arm/mach-versatile/Kconfig"
855
856source "arch/arm/mach-vexpress/Kconfig"
857source "arch/arm/plat-versatile/Kconfig"
858
859source "arch/arm/mach-vt8500/Kconfig"
860
861source "arch/arm/mach-w90x900/Kconfig"
862
863source "arch/arm/mach-zx/Kconfig"
864
865source "arch/arm/mach-zynq/Kconfig"
866
867# ARMv7-M architecture
868config ARCH_EFM32
869	bool "Energy Micro efm32"
870	depends on ARM_SINGLE_ARMV7M
871	select ARCH_REQUIRE_GPIOLIB
872	help
873	  Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
874	  processors.
875
876config ARCH_LPC18XX
877	bool "NXP LPC18xx/LPC43xx"
878	depends on ARM_SINGLE_ARMV7M
879	select ARCH_HAS_RESET_CONTROLLER
880	select ARM_AMBA
881	select CLKSRC_LPC32XX
882	select PINCTRL
883	help
884	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
885	  high performance microcontrollers.
886
887config ARCH_STM32
888	bool "STMicrolectronics STM32"
889	depends on ARM_SINGLE_ARMV7M
890	select ARCH_HAS_RESET_CONTROLLER
891	select ARMV7M_SYSTICK
892	select CLKSRC_STM32
893	select PINCTRL
894	select RESET_CONTROLLER
895	help
896	  Support for STMicroelectronics STM32 processors.
897
898config MACH_STM32F429
899	bool "STMicrolectronics STM32F429"
900	depends on ARCH_STM32
901	default y
902
903config ARCH_MPS2
904	bool "ARM MPS2 paltform"
905	depends on ARM_SINGLE_ARMV7M
906	select ARM_AMBA
907	select CLKSRC_MPS2
908	help
909	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
910	  with a range of available cores like Cortex-M3/M4/M7.
911
912	  Please, note that depends which Application Note is used memory map
913	  for the platform may vary, so adjustment of RAM base might be needed.
914
915# Definitions to make life easier
916config ARCH_ACORN
917	bool
918
919config PLAT_IOP
920	bool
921	select GENERIC_CLOCKEVENTS
922
923config PLAT_ORION
924	bool
925	select CLKSRC_MMIO
926	select COMMON_CLK
927	select GENERIC_IRQ_CHIP
928	select IRQ_DOMAIN
929
930config PLAT_ORION_LEGACY
931	bool
932	select PLAT_ORION
933
934config PLAT_PXA
935	bool
936
937config PLAT_VERSATILE
938	bool
939
940source "arch/arm/firmware/Kconfig"
941
942source arch/arm/mm/Kconfig
943
944config IWMMXT
945	bool "Enable iWMMXt support"
946	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
947	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
948	help
949	  Enable support for iWMMXt context switching at run time if
950	  running on a CPU that supports it.
951
952config MULTI_IRQ_HANDLER
953	bool
954	help
955	  Allow each machine to specify it's own IRQ handler at run time.
956
957if !MMU
958source "arch/arm/Kconfig-nommu"
959endif
960
961config PJ4B_ERRATA_4742
962	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
963	depends on CPU_PJ4B && MACH_ARMADA_370
964	default y
965	help
966	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
967	  Event (WFE) IDLE states, a specific timing sensitivity exists between
968	  the retiring WFI/WFE instructions and the newly issued subsequent
969	  instructions.  This sensitivity can result in a CPU hang scenario.
970	  Workaround:
971	  The software must insert either a Data Synchronization Barrier (DSB)
972	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
973	  instruction
974
975config ARM_ERRATA_326103
976	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
977	depends on CPU_V6
978	help
979	  Executing a SWP instruction to read-only memory does not set bit 11
980	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
981	  treat the access as a read, preventing a COW from occurring and
982	  causing the faulting task to livelock.
983
984config ARM_ERRATA_411920
985	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
986	depends on CPU_V6 || CPU_V6K
987	help
988	  Invalidation of the Instruction Cache operation can
989	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
990	  It does not affect the MPCore. This option enables the ARM Ltd.
991	  recommended workaround.
992
993config ARM_ERRATA_430973
994	bool "ARM errata: Stale prediction on replaced interworking branch"
995	depends on CPU_V7
996	help
997	  This option enables the workaround for the 430973 Cortex-A8
998	  r1p* erratum. If a code sequence containing an ARM/Thumb
999	  interworking branch is replaced with another code sequence at the
1000	  same virtual address, whether due to self-modifying code or virtual
1001	  to physical address re-mapping, Cortex-A8 does not recover from the
1002	  stale interworking branch prediction. This results in Cortex-A8
1003	  executing the new code sequence in the incorrect ARM or Thumb state.
1004	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1005	  and also flushes the branch target cache at every context switch.
1006	  Note that setting specific bits in the ACTLR register may not be
1007	  available in non-secure mode.
1008
1009config ARM_ERRATA_458693
1010	bool "ARM errata: Processor deadlock when a false hazard is created"
1011	depends on CPU_V7
1012	depends on !ARCH_MULTIPLATFORM
1013	help
1014	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1015	  erratum. For very specific sequences of memory operations, it is
1016	  possible for a hazard condition intended for a cache line to instead
1017	  be incorrectly associated with a different cache line. This false
1018	  hazard might then cause a processor deadlock. The workaround enables
1019	  the L1 caching of the NEON accesses and disables the PLD instruction
1020	  in the ACTLR register. Note that setting specific bits in the ACTLR
1021	  register may not be available in non-secure mode.
1022
1023config ARM_ERRATA_460075
1024	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1025	depends on CPU_V7
1026	depends on !ARCH_MULTIPLATFORM
1027	help
1028	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1029	  erratum. Any asynchronous access to the L2 cache may encounter a
1030	  situation in which recent store transactions to the L2 cache are lost
1031	  and overwritten with stale memory contents from external memory. The
1032	  workaround disables the write-allocate mode for the L2 cache via the
1033	  ACTLR register. Note that setting specific bits in the ACTLR register
1034	  may not be available in non-secure mode.
1035
1036config ARM_ERRATA_742230
1037	bool "ARM errata: DMB operation may be faulty"
1038	depends on CPU_V7 && SMP
1039	depends on !ARCH_MULTIPLATFORM
1040	help
1041	  This option enables the workaround for the 742230 Cortex-A9
1042	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1043	  between two write operations may not ensure the correct visibility
1044	  ordering of the two writes. This workaround sets a specific bit in
1045	  the diagnostic register of the Cortex-A9 which causes the DMB
1046	  instruction to behave as a DSB, ensuring the correct behaviour of
1047	  the two writes.
1048
1049config ARM_ERRATA_742231
1050	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1051	depends on CPU_V7 && SMP
1052	depends on !ARCH_MULTIPLATFORM
1053	help
1054	  This option enables the workaround for the 742231 Cortex-A9
1055	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1056	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1057	  accessing some data located in the same cache line, may get corrupted
1058	  data due to bad handling of the address hazard when the line gets
1059	  replaced from one of the CPUs at the same time as another CPU is
1060	  accessing it. This workaround sets specific bits in the diagnostic
1061	  register of the Cortex-A9 which reduces the linefill issuing
1062	  capabilities of the processor.
1063
1064config ARM_ERRATA_643719
1065	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1066	depends on CPU_V7 && SMP
1067	default y
1068	help
1069	  This option enables the workaround for the 643719 Cortex-A9 (prior to
1070	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1071	  register returns zero when it should return one. The workaround
1072	  corrects this value, ensuring cache maintenance operations which use
1073	  it behave as intended and avoiding data corruption.
1074
1075config ARM_ERRATA_720789
1076	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1077	depends on CPU_V7
1078	help
1079	  This option enables the workaround for the 720789 Cortex-A9 (prior to
1080	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1081	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1082	  As a consequence of this erratum, some TLB entries which should be
1083	  invalidated are not, resulting in an incoherency in the system page
1084	  tables. The workaround changes the TLB flushing routines to invalidate
1085	  entries regardless of the ASID.
1086
1087config ARM_ERRATA_743622
1088	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1089	depends on CPU_V7
1090	depends on !ARCH_MULTIPLATFORM
1091	help
1092	  This option enables the workaround for the 743622 Cortex-A9
1093	  (r2p*) erratum. Under very rare conditions, a faulty
1094	  optimisation in the Cortex-A9 Store Buffer may lead to data
1095	  corruption. This workaround sets a specific bit in the diagnostic
1096	  register of the Cortex-A9 which disables the Store Buffer
1097	  optimisation, preventing the defect from occurring. This has no
1098	  visible impact on the overall performance or power consumption of the
1099	  processor.
1100
1101config ARM_ERRATA_751472
1102	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1103	depends on CPU_V7
1104	depends on !ARCH_MULTIPLATFORM
1105	help
1106	  This option enables the workaround for the 751472 Cortex-A9 (prior
1107	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1108	  completion of a following broadcasted operation if the second
1109	  operation is received by a CPU before the ICIALLUIS has completed,
1110	  potentially leading to corrupted entries in the cache or TLB.
1111
1112config ARM_ERRATA_754322
1113	bool "ARM errata: possible faulty MMU translations following an ASID switch"
1114	depends on CPU_V7
1115	help
1116	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1117	  r3p*) erratum. A speculative memory access may cause a page table walk
1118	  which starts prior to an ASID switch but completes afterwards. This
1119	  can populate the micro-TLB with a stale entry which may be hit with
1120	  the new ASID. This workaround places two dsb instructions in the mm
1121	  switching code so that no page table walks can cross the ASID switch.
1122
1123config ARM_ERRATA_754327
1124	bool "ARM errata: no automatic Store Buffer drain"
1125	depends on CPU_V7 && SMP
1126	help
1127	  This option enables the workaround for the 754327 Cortex-A9 (prior to
1128	  r2p0) erratum. The Store Buffer does not have any automatic draining
1129	  mechanism and therefore a livelock may occur if an external agent
1130	  continuously polls a memory location waiting to observe an update.
1131	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
1132	  written polling loops from denying visibility of updates to memory.
1133
1134config ARM_ERRATA_364296
1135	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1136	depends on CPU_V6
1137	help
1138	  This options enables the workaround for the 364296 ARM1136
1139	  r0p2 erratum (possible cache data corruption with
1140	  hit-under-miss enabled). It sets the undocumented bit 31 in
1141	  the auxiliary control register and the FI bit in the control
1142	  register, thus disabling hit-under-miss without putting the
1143	  processor into full low interrupt latency mode. ARM11MPCore
1144	  is not affected.
1145
1146config ARM_ERRATA_764369
1147	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1148	depends on CPU_V7 && SMP
1149	help
1150	  This option enables the workaround for erratum 764369
1151	  affecting Cortex-A9 MPCore with two or more processors (all
1152	  current revisions). Under certain timing circumstances, a data
1153	  cache line maintenance operation by MVA targeting an Inner
1154	  Shareable memory region may fail to proceed up to either the
1155	  Point of Coherency or to the Point of Unification of the
1156	  system. This workaround adds a DSB instruction before the
1157	  relevant cache maintenance functions and sets a specific bit
1158	  in the diagnostic control register of the SCU.
1159
1160config ARM_ERRATA_775420
1161       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1162       depends on CPU_V7
1163       help
1164	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1165	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1166	 operation aborts with MMU exception, it might cause the processor
1167	 to deadlock. This workaround puts DSB before executing ISB if
1168	 an abort may occur on cache maintenance.
1169
1170config ARM_ERRATA_798181
1171	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1172	depends on CPU_V7 && SMP
1173	help
1174	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1175	  adequately shooting down all use of the old entries. This
1176	  option enables the Linux kernel workaround for this erratum
1177	  which sends an IPI to the CPUs that are running the same ASID
1178	  as the one being invalidated.
1179
1180config ARM_ERRATA_773022
1181	bool "ARM errata: incorrect instructions may be executed from loop buffer"
1182	depends on CPU_V7
1183	help
1184	  This option enables the workaround for the 773022 Cortex-A15
1185	  (up to r0p4) erratum. In certain rare sequences of code, the
1186	  loop buffer may deliver incorrect instructions. This
1187	  workaround disables the loop buffer to avoid the erratum.
1188
1189endmenu
1190
1191source "arch/arm/common/Kconfig"
1192
1193menu "Bus support"
1194
1195config ISA
1196	bool
1197	help
1198	  Find out whether you have ISA slots on your motherboard.  ISA is the
1199	  name of a bus system, i.e. the way the CPU talks to the other stuff
1200	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1201	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1202	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1203
1204# Select ISA DMA controller support
1205config ISA_DMA
1206	bool
1207	select ISA_DMA_API
1208
1209# Select ISA DMA interface
1210config ISA_DMA_API
1211	bool
1212
1213config PCI
1214	bool "PCI support" if MIGHT_HAVE_PCI
1215	help
1216	  Find out whether you have a PCI motherboard. PCI is the name of a
1217	  bus system, i.e. the way the CPU talks to the other stuff inside
1218	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1219	  VESA. If you have PCI, say Y, otherwise N.
1220
1221config PCI_DOMAINS
1222	bool
1223	depends on PCI
1224
1225config PCI_DOMAINS_GENERIC
1226	def_bool PCI_DOMAINS
1227
1228config PCI_NANOENGINE
1229	bool "BSE nanoEngine PCI support"
1230	depends on SA1100_NANOENGINE
1231	help
1232	  Enable PCI on the BSE nanoEngine board.
1233
1234config PCI_SYSCALL
1235	def_bool PCI
1236
1237config PCI_HOST_ITE8152
1238	bool
1239	depends on PCI && MACH_ARMCORE
1240	default y
1241	select DMABOUNCE
1242
1243source "drivers/pci/Kconfig"
1244
1245source "drivers/pcmcia/Kconfig"
1246
1247endmenu
1248
1249menu "Kernel Features"
1250
1251config HAVE_SMP
1252	bool
1253	help
1254	  This option should be selected by machines which have an SMP-
1255	  capable CPU.
1256
1257	  The only effect of this option is to make the SMP-related
1258	  options available to the user for configuration.
1259
1260config SMP
1261	bool "Symmetric Multi-Processing"
1262	depends on CPU_V6K || CPU_V7
1263	depends on GENERIC_CLOCKEVENTS
1264	depends on HAVE_SMP
1265	depends on MMU || ARM_MPU
1266	select IRQ_WORK
1267	help
1268	  This enables support for systems with more than one CPU. If you have
1269	  a system with only one CPU, say N. If you have a system with more
1270	  than one CPU, say Y.
1271
1272	  If you say N here, the kernel will run on uni- and multiprocessor
1273	  machines, but will use only one CPU of a multiprocessor machine. If
1274	  you say Y here, the kernel will run on many, but not all,
1275	  uniprocessor machines. On a uniprocessor machine, the kernel
1276	  will run faster if you say N here.
1277
1278	  See also <file:Documentation/x86/i386/IO-APIC.txt>,
1279	  <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1280	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1281
1282	  If you don't know what to do here, say N.
1283
1284config SMP_ON_UP
1285	bool "Allow booting SMP kernel on uniprocessor systems"
1286	depends on SMP && !XIP_KERNEL && MMU
1287	default y
1288	help
1289	  SMP kernels contain instructions which fail on non-SMP processors.
1290	  Enabling this option allows the kernel to modify itself to make
1291	  these instructions safe.  Disabling it allows about 1K of space
1292	  savings.
1293
1294	  If you don't know what to do here, say Y.
1295
1296config ARM_CPU_TOPOLOGY
1297	bool "Support cpu topology definition"
1298	depends on SMP && CPU_V7
1299	default y
1300	help
1301	  Support ARM cpu topology definition. The MPIDR register defines
1302	  affinity between processors which is then used to describe the cpu
1303	  topology of an ARM System.
1304
1305config SCHED_MC
1306	bool "Multi-core scheduler support"
1307	depends on ARM_CPU_TOPOLOGY
1308	help
1309	  Multi-core scheduler support improves the CPU scheduler's decision
1310	  making when dealing with multi-core CPU chips at a cost of slightly
1311	  increased overhead in some places. If unsure say N here.
1312
1313config SCHED_SMT
1314	bool "SMT scheduler support"
1315	depends on ARM_CPU_TOPOLOGY
1316	help
1317	  Improves the CPU scheduler's decision making when dealing with
1318	  MultiThreading at a cost of slightly increased overhead in some
1319	  places. If unsure say N here.
1320
1321config HAVE_ARM_SCU
1322	bool
1323	help
1324	  This option enables support for the ARM system coherency unit
1325
1326config HAVE_ARM_ARCH_TIMER
1327	bool "Architected timer support"
1328	depends on CPU_V7
1329	select ARM_ARCH_TIMER
1330	select GENERIC_CLOCKEVENTS
1331	help
1332	  This option enables support for the ARM architected timer
1333
1334config HAVE_ARM_TWD
1335	bool
1336	select CLKSRC_OF if OF
1337	help
1338	  This options enables support for the ARM timer and watchdog unit
1339
1340config MCPM
1341	bool "Multi-Cluster Power Management"
1342	depends on CPU_V7 && SMP
1343	help
1344	  This option provides the common power management infrastructure
1345	  for (multi-)cluster based systems, such as big.LITTLE based
1346	  systems.
1347
1348config MCPM_QUAD_CLUSTER
1349	bool
1350	depends on MCPM
1351	help
1352	  To avoid wasting resources unnecessarily, MCPM only supports up
1353	  to 2 clusters by default.
1354	  Platforms with 3 or 4 clusters that use MCPM must select this
1355	  option to allow the additional clusters to be managed.
1356
1357config BIG_LITTLE
1358	bool "big.LITTLE support (Experimental)"
1359	depends on CPU_V7 && SMP
1360	select MCPM
1361	help
1362	  This option enables support selections for the big.LITTLE
1363	  system architecture.
1364
1365config BL_SWITCHER
1366	bool "big.LITTLE switcher support"
1367	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1368	select CPU_PM
1369	help
1370	  The big.LITTLE "switcher" provides the core functionality to
1371	  transparently handle transition between a cluster of A15's
1372	  and a cluster of A7's in a big.LITTLE system.
1373
1374config BL_SWITCHER_DUMMY_IF
1375	tristate "Simple big.LITTLE switcher user interface"
1376	depends on BL_SWITCHER && DEBUG_KERNEL
1377	help
1378	  This is a simple and dummy char dev interface to control
1379	  the big.LITTLE switcher core code.  It is meant for
1380	  debugging purposes only.
1381
1382choice
1383	prompt "Memory split"
1384	depends on MMU
1385	default VMSPLIT_3G
1386	help
1387	  Select the desired split between kernel and user memory.
1388
1389	  If you are not absolutely sure what you are doing, leave this
1390	  option alone!
1391
1392	config VMSPLIT_3G
1393		bool "3G/1G user/kernel split"
1394	config VMSPLIT_3G_OPT
1395		bool "3G/1G user/kernel split (for full 1G low memory)"
1396	config VMSPLIT_2G
1397		bool "2G/2G user/kernel split"
1398	config VMSPLIT_1G
1399		bool "1G/3G user/kernel split"
1400endchoice
1401
1402config PAGE_OFFSET
1403	hex
1404	default PHYS_OFFSET if !MMU
1405	default 0x40000000 if VMSPLIT_1G
1406	default 0x80000000 if VMSPLIT_2G
1407	default 0xB0000000 if VMSPLIT_3G_OPT
1408	default 0xC0000000
1409
1410config NR_CPUS
1411	int "Maximum number of CPUs (2-32)"
1412	range 2 32
1413	depends on SMP
1414	default "4"
1415
1416config HOTPLUG_CPU
1417	bool "Support for hot-pluggable CPUs"
1418	depends on SMP
1419	help
1420	  Say Y here to experiment with turning CPUs off and on.  CPUs
1421	  can be controlled through /sys/devices/system/cpu.
1422
1423config ARM_PSCI
1424	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1425	depends on HAVE_ARM_SMCCC
1426	select ARM_PSCI_FW
1427	help
1428	  Say Y here if you want Linux to communicate with system firmware
1429	  implementing the PSCI specification for CPU-centric power
1430	  management operations described in ARM document number ARM DEN
1431	  0022A ("Power State Coordination Interface System Software on
1432	  ARM processors").
1433
1434# The GPIO number here must be sorted by descending number. In case of
1435# a multiplatform kernel, we just want the highest value required by the
1436# selected platforms.
1437config ARCH_NR_GPIO
1438	int
1439	default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1440		ARCH_ZYNQ
1441	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1442		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1443	default 416 if ARCH_SUNXI
1444	default 392 if ARCH_U8500
1445	default 352 if ARCH_VT8500
1446	default 288 if ARCH_ROCKCHIP
1447	default 264 if MACH_H4700
1448	default 0
1449	help
1450	  Maximum number of GPIOs in the system.
1451
1452	  If unsure, leave the default value.
1453
1454source kernel/Kconfig.preempt
1455
1456config HZ_FIXED
1457	int
1458	default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1459		ARCH_S5PV210 || ARCH_EXYNOS4
1460	default 128 if SOC_AT91RM9200
1461	default 0
1462
1463choice
1464	depends on HZ_FIXED = 0
1465	prompt "Timer frequency"
1466
1467config HZ_100
1468	bool "100 Hz"
1469
1470config HZ_200
1471	bool "200 Hz"
1472
1473config HZ_250
1474	bool "250 Hz"
1475
1476config HZ_300
1477	bool "300 Hz"
1478
1479config HZ_500
1480	bool "500 Hz"
1481
1482config HZ_1000
1483	bool "1000 Hz"
1484
1485endchoice
1486
1487config HZ
1488	int
1489	default HZ_FIXED if HZ_FIXED != 0
1490	default 100 if HZ_100
1491	default 200 if HZ_200
1492	default 250 if HZ_250
1493	default 300 if HZ_300
1494	default 500 if HZ_500
1495	default 1000
1496
1497config SCHED_HRTICK
1498	def_bool HIGH_RES_TIMERS
1499
1500config THUMB2_KERNEL
1501	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1502	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1503	default y if CPU_THUMBONLY
1504	select AEABI
1505	select ARM_ASM_UNIFIED
1506	select ARM_UNWIND
1507	help
1508	  By enabling this option, the kernel will be compiled in
1509	  Thumb-2 mode. A compiler/assembler that understand the unified
1510	  ARM-Thumb syntax is needed.
1511
1512	  If unsure, say N.
1513
1514config THUMB2_AVOID_R_ARM_THM_JUMP11
1515	bool "Work around buggy Thumb-2 short branch relocations in gas"
1516	depends on THUMB2_KERNEL && MODULES
1517	default y
1518	help
1519	  Various binutils versions can resolve Thumb-2 branches to
1520	  locally-defined, preemptible global symbols as short-range "b.n"
1521	  branch instructions.
1522
1523	  This is a problem, because there's no guarantee the final
1524	  destination of the symbol, or any candidate locations for a
1525	  trampoline, are within range of the branch.  For this reason, the
1526	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1527	  relocation in modules at all, and it makes little sense to add
1528	  support.
1529
1530	  The symptom is that the kernel fails with an "unsupported
1531	  relocation" error when loading some modules.
1532
1533	  Until fixed tools are available, passing
1534	  -fno-optimize-sibling-calls to gcc should prevent gcc generating
1535	  code which hits this problem, at the cost of a bit of extra runtime
1536	  stack usage in some cases.
1537
1538	  The problem is described in more detail at:
1539	      https://bugs.launchpad.net/binutils-linaro/+bug/725126
1540
1541	  Only Thumb-2 kernels are affected.
1542
1543	  Unless you are sure your tools don't have this problem, say Y.
1544
1545config ARM_ASM_UNIFIED
1546	bool
1547
1548config ARM_PATCH_IDIV
1549	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1550	depends on CPU_32v7 && !XIP_KERNEL
1551	default y
1552	help
1553	  The ARM compiler inserts calls to __aeabi_idiv() and
1554	  __aeabi_uidiv() when it needs to perform division on signed
1555	  and unsigned integers. Some v7 CPUs have support for the sdiv
1556	  and udiv instructions that can be used to implement those
1557	  functions.
1558
1559	  Enabling this option allows the kernel to modify itself to
1560	  replace the first two instructions of these library functions
1561	  with the sdiv or udiv plus "bx lr" instructions when the CPU
1562	  it is running on supports them. Typically this will be faster
1563	  and less power intensive than running the original library
1564	  code to do integer division.
1565
1566config AEABI
1567	bool "Use the ARM EABI to compile the kernel"
1568	help
1569	  This option allows for the kernel to be compiled using the latest
1570	  ARM ABI (aka EABI).  This is only useful if you are using a user
1571	  space environment that is also compiled with EABI.
1572
1573	  Since there are major incompatibilities between the legacy ABI and
1574	  EABI, especially with regard to structure member alignment, this
1575	  option also changes the kernel syscall calling convention to
1576	  disambiguate both ABIs and allow for backward compatibility support
1577	  (selected with CONFIG_OABI_COMPAT).
1578
1579	  To use this you need GCC version 4.0.0 or later.
1580
1581config OABI_COMPAT
1582	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1583	depends on AEABI && !THUMB2_KERNEL
1584	help
1585	  This option preserves the old syscall interface along with the
1586	  new (ARM EABI) one. It also provides a compatibility layer to
1587	  intercept syscalls that have structure arguments which layout
1588	  in memory differs between the legacy ABI and the new ARM EABI
1589	  (only for non "thumb" binaries). This option adds a tiny
1590	  overhead to all syscalls and produces a slightly larger kernel.
1591
1592	  The seccomp filter system will not be available when this is
1593	  selected, since there is no way yet to sensibly distinguish
1594	  between calling conventions during filtering.
1595
1596	  If you know you'll be using only pure EABI user space then you
1597	  can say N here. If this option is not selected and you attempt
1598	  to execute a legacy ABI binary then the result will be
1599	  UNPREDICTABLE (in fact it can be predicted that it won't work
1600	  at all). If in doubt say N.
1601
1602config ARCH_HAS_HOLES_MEMORYMODEL
1603	bool
1604
1605config ARCH_SPARSEMEM_ENABLE
1606	bool
1607
1608config ARCH_SPARSEMEM_DEFAULT
1609	def_bool ARCH_SPARSEMEM_ENABLE
1610
1611config ARCH_SELECT_MEMORY_MODEL
1612	def_bool ARCH_SPARSEMEM_ENABLE
1613
1614config HAVE_ARCH_PFN_VALID
1615	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1616
1617config HAVE_GENERIC_RCU_GUP
1618	def_bool y
1619	depends on ARM_LPAE
1620
1621config HIGHMEM
1622	bool "High Memory Support"
1623	depends on MMU
1624	help
1625	  The address space of ARM processors is only 4 Gigabytes large
1626	  and it has to accommodate user address space, kernel address
1627	  space as well as some memory mapped IO. That means that, if you
1628	  have a large amount of physical memory and/or IO, not all of the
1629	  memory can be "permanently mapped" by the kernel. The physical
1630	  memory that is not permanently mapped is called "high memory".
1631
1632	  Depending on the selected kernel/user memory split, minimum
1633	  vmalloc space and actual amount of RAM, you may not need this
1634	  option which should result in a slightly faster kernel.
1635
1636	  If unsure, say n.
1637
1638config HIGHPTE
1639	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1640	depends on HIGHMEM
1641	default y
1642	help
1643	  The VM uses one page of physical memory for each page table.
1644	  For systems with a lot of processes, this can use a lot of
1645	  precious low memory, eventually leading to low memory being
1646	  consumed by page tables.  Setting this option will allow
1647	  user-space 2nd level page tables to reside in high memory.
1648
1649config CPU_SW_DOMAIN_PAN
1650	bool "Enable use of CPU domains to implement privileged no-access"
1651	depends on MMU && !ARM_LPAE
1652	default y
1653	help
1654	  Increase kernel security by ensuring that normal kernel accesses
1655	  are unable to access userspace addresses.  This can help prevent
1656	  use-after-free bugs becoming an exploitable privilege escalation
1657	  by ensuring that magic values (such as LIST_POISON) will always
1658	  fault when dereferenced.
1659
1660	  CPUs with low-vector mappings use a best-efforts implementation.
1661	  Their lower 1MB needs to remain accessible for the vectors, but
1662	  the remainder of userspace will become appropriately inaccessible.
1663
1664config HW_PERF_EVENTS
1665	def_bool y
1666	depends on ARM_PMU
1667
1668config SYS_SUPPORTS_HUGETLBFS
1669       def_bool y
1670       depends on ARM_LPAE
1671
1672config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1673       def_bool y
1674       depends on ARM_LPAE
1675
1676config ARCH_WANT_GENERAL_HUGETLB
1677	def_bool y
1678
1679config ARM_MODULE_PLTS
1680	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1681	depends on MODULES
1682	help
1683	  Allocate PLTs when loading modules so that jumps and calls whose
1684	  targets are too far away for their relative offsets to be encoded
1685	  in the instructions themselves can be bounced via veneers in the
1686	  module's PLT. This allows modules to be allocated in the generic
1687	  vmalloc area after the dedicated module memory area has been
1688	  exhausted. The modules will use slightly more memory, but after
1689	  rounding up to page size, the actual memory footprint is usually
1690	  the same.
1691
1692	  Say y if you are getting out of memory errors while loading modules
1693
1694source "mm/Kconfig"
1695
1696config FORCE_MAX_ZONEORDER
1697	int "Maximum zone order"
1698	default "12" if SOC_AM33XX
1699	default "9" if SA1111 || ARCH_EFM32
1700	default "11"
1701	help
1702	  The kernel memory allocator divides physically contiguous memory
1703	  blocks into "zones", where each zone is a power of two number of
1704	  pages.  This option selects the largest power of two that the kernel
1705	  keeps in the memory allocator.  If you need to allocate very large
1706	  blocks of physically contiguous memory, then you may need to
1707	  increase this value.
1708
1709	  This config option is actually maximum order plus one. For example,
1710	  a value of 11 means that the largest free memory block is 2^10 pages.
1711
1712config ALIGNMENT_TRAP
1713	bool
1714	depends on CPU_CP15_MMU
1715	default y if !ARCH_EBSA110
1716	select HAVE_PROC_CPU if PROC_FS
1717	help
1718	  ARM processors cannot fetch/store information which is not
1719	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1720	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1721	  fetch/store instructions will be emulated in software if you say
1722	  here, which has a severe performance impact. This is necessary for
1723	  correct operation of some network protocols. With an IP-only
1724	  configuration it is safe to say N, otherwise say Y.
1725
1726config UACCESS_WITH_MEMCPY
1727	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1728	depends on MMU
1729	default y if CPU_FEROCEON
1730	help
1731	  Implement faster copy_to_user and clear_user methods for CPU
1732	  cores where a 8-word STM instruction give significantly higher
1733	  memory write throughput than a sequence of individual 32bit stores.
1734
1735	  A possible side effect is a slight increase in scheduling latency
1736	  between threads sharing the same address space if they invoke
1737	  such copy operations with large buffers.
1738
1739	  However, if the CPU data cache is using a write-allocate mode,
1740	  this option is unlikely to provide any performance gain.
1741
1742config SECCOMP
1743	bool
1744	prompt "Enable seccomp to safely compute untrusted bytecode"
1745	---help---
1746	  This kernel feature is useful for number crunching applications
1747	  that may need to compute untrusted bytecode during their
1748	  execution. By using pipes or other transports made available to
1749	  the process as file descriptors supporting the read/write
1750	  syscalls, it's possible to isolate those applications in
1751	  their own address space using seccomp. Once seccomp is
1752	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1753	  and the task is only allowed to execute a few safe syscalls
1754	  defined by each seccomp mode.
1755
1756config SWIOTLB
1757	def_bool y
1758
1759config IOMMU_HELPER
1760	def_bool SWIOTLB
1761
1762config PARAVIRT
1763	bool "Enable paravirtualization code"
1764	help
1765	  This changes the kernel so it can modify itself when it is run
1766	  under a hypervisor, potentially improving performance significantly
1767	  over full virtualization.
1768
1769config PARAVIRT_TIME_ACCOUNTING
1770	bool "Paravirtual steal time accounting"
1771	select PARAVIRT
1772	default n
1773	help
1774	  Select this option to enable fine granularity task steal time
1775	  accounting. Time spent executing other tasks in parallel with
1776	  the current vCPU is discounted from the vCPU power. To account for
1777	  that, there can be a small performance impact.
1778
1779	  If in doubt, say N here.
1780
1781config XEN_DOM0
1782	def_bool y
1783	depends on XEN
1784
1785config XEN
1786	bool "Xen guest support on ARM"
1787	depends on ARM && AEABI && OF
1788	depends on CPU_V7 && !CPU_V6
1789	depends on !GENERIC_ATOMIC64
1790	depends on MMU
1791	select ARCH_DMA_ADDR_T_64BIT
1792	select ARM_PSCI
1793	select SWIOTLB_XEN
1794	select PARAVIRT
1795	help
1796	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1797
1798endmenu
1799
1800menu "Boot options"
1801
1802config USE_OF
1803	bool "Flattened Device Tree support"
1804	select IRQ_DOMAIN
1805	select OF
1806	help
1807	  Include support for flattened device tree machine descriptions.
1808
1809config ATAGS
1810	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1811	default y
1812	help
1813	  This is the traditional way of passing data to the kernel at boot
1814	  time. If you are solely relying on the flattened device tree (or
1815	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1816	  to remove ATAGS support from your kernel binary.  If unsure,
1817	  leave this to y.
1818
1819config DEPRECATED_PARAM_STRUCT
1820	bool "Provide old way to pass kernel parameters"
1821	depends on ATAGS
1822	help
1823	  This was deprecated in 2001 and announced to live on for 5 years.
1824	  Some old boot loaders still use this way.
1825
1826# Compressed boot loader in ROM.  Yes, we really want to ask about
1827# TEXT and BSS so we preserve their values in the config files.
1828config ZBOOT_ROM_TEXT
1829	hex "Compressed ROM boot loader base address"
1830	default "0"
1831	help
1832	  The physical address at which the ROM-able zImage is to be
1833	  placed in the target.  Platforms which normally make use of
1834	  ROM-able zImage formats normally set this to a suitable
1835	  value in their defconfig file.
1836
1837	  If ZBOOT_ROM is not enabled, this has no effect.
1838
1839config ZBOOT_ROM_BSS
1840	hex "Compressed ROM boot loader BSS address"
1841	default "0"
1842	help
1843	  The base address of an area of read/write memory in the target
1844	  for the ROM-able zImage which must be available while the
1845	  decompressor is running. It must be large enough to hold the
1846	  entire decompressed kernel plus an additional 128 KiB.
1847	  Platforms which normally make use of ROM-able zImage formats
1848	  normally set this to a suitable value in their defconfig file.
1849
1850	  If ZBOOT_ROM is not enabled, this has no effect.
1851
1852config ZBOOT_ROM
1853	bool "Compressed boot loader in ROM/flash"
1854	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1855	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1856	help
1857	  Say Y here if you intend to execute your compressed kernel image
1858	  (zImage) directly from ROM or flash.  If unsure, say N.
1859
1860config ARM_APPENDED_DTB
1861	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1862	depends on OF
1863	help
1864	  With this option, the boot code will look for a device tree binary
1865	  (DTB) appended to zImage
1866	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1867
1868	  This is meant as a backward compatibility convenience for those
1869	  systems with a bootloader that can't be upgraded to accommodate
1870	  the documented boot protocol using a device tree.
1871
1872	  Beware that there is very little in terms of protection against
1873	  this option being confused by leftover garbage in memory that might
1874	  look like a DTB header after a reboot if no actual DTB is appended
1875	  to zImage.  Do not leave this option active in a production kernel
1876	  if you don't intend to always append a DTB.  Proper passing of the
1877	  location into r2 of a bootloader provided DTB is always preferable
1878	  to this option.
1879
1880config ARM_ATAG_DTB_COMPAT
1881	bool "Supplement the appended DTB with traditional ATAG information"
1882	depends on ARM_APPENDED_DTB
1883	help
1884	  Some old bootloaders can't be updated to a DTB capable one, yet
1885	  they provide ATAGs with memory configuration, the ramdisk address,
1886	  the kernel cmdline string, etc.  Such information is dynamically
1887	  provided by the bootloader and can't always be stored in a static
1888	  DTB.  To allow a device tree enabled kernel to be used with such
1889	  bootloaders, this option allows zImage to extract the information
1890	  from the ATAG list and store it at run time into the appended DTB.
1891
1892choice
1893	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1894	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1895
1896config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1897	bool "Use bootloader kernel arguments if available"
1898	help
1899	  Uses the command-line options passed by the boot loader instead of
1900	  the device tree bootargs property. If the boot loader doesn't provide
1901	  any, the device tree bootargs property will be used.
1902
1903config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1904	bool "Extend with bootloader kernel arguments"
1905	help
1906	  The command-line arguments provided by the boot loader will be
1907	  appended to the the device tree bootargs property.
1908
1909endchoice
1910
1911config CMDLINE
1912	string "Default kernel command string"
1913	default ""
1914	help
1915	  On some architectures (EBSA110 and CATS), there is currently no way
1916	  for the boot loader to pass arguments to the kernel. For these
1917	  architectures, you should supply some command-line options at build
1918	  time by entering them here. As a minimum, you should specify the
1919	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1920
1921choice
1922	prompt "Kernel command line type" if CMDLINE != ""
1923	default CMDLINE_FROM_BOOTLOADER
1924	depends on ATAGS
1925
1926config CMDLINE_FROM_BOOTLOADER
1927	bool "Use bootloader kernel arguments if available"
1928	help
1929	  Uses the command-line options passed by the boot loader. If
1930	  the boot loader doesn't provide any, the default kernel command
1931	  string provided in CMDLINE will be used.
1932
1933config CMDLINE_EXTEND
1934	bool "Extend bootloader kernel arguments"
1935	help
1936	  The command-line arguments provided by the boot loader will be
1937	  appended to the default kernel command string.
1938
1939config CMDLINE_FORCE
1940	bool "Always use the default kernel command string"
1941	help
1942	  Always use the default kernel command string, even if the boot
1943	  loader passes other arguments to the kernel.
1944	  This is useful if you cannot or don't want to change the
1945	  command-line options your boot loader passes to the kernel.
1946endchoice
1947
1948config XIP_KERNEL
1949	bool "Kernel Execute-In-Place from ROM"
1950	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1951	help
1952	  Execute-In-Place allows the kernel to run from non-volatile storage
1953	  directly addressable by the CPU, such as NOR flash. This saves RAM
1954	  space since the text section of the kernel is not loaded from flash
1955	  to RAM.  Read-write sections, such as the data section and stack,
1956	  are still copied to RAM.  The XIP kernel is not compressed since
1957	  it has to run directly from flash, so it will take more space to
1958	  store it.  The flash address used to link the kernel object files,
1959	  and for storing it, is configuration dependent. Therefore, if you
1960	  say Y here, you must know the proper physical address where to
1961	  store the kernel image depending on your own flash memory usage.
1962
1963	  Also note that the make target becomes "make xipImage" rather than
1964	  "make zImage" or "make Image".  The final kernel binary to put in
1965	  ROM memory will be arch/arm/boot/xipImage.
1966
1967	  If unsure, say N.
1968
1969config XIP_PHYS_ADDR
1970	hex "XIP Kernel Physical Location"
1971	depends on XIP_KERNEL
1972	default "0x00080000"
1973	help
1974	  This is the physical address in your flash memory the kernel will
1975	  be linked for and stored to.  This address is dependent on your
1976	  own flash usage.
1977
1978config KEXEC
1979	bool "Kexec system call (EXPERIMENTAL)"
1980	depends on (!SMP || PM_SLEEP_SMP)
1981	depends on !CPU_V7M
1982	select KEXEC_CORE
1983	help
1984	  kexec is a system call that implements the ability to shutdown your
1985	  current kernel, and to start another kernel.  It is like a reboot
1986	  but it is independent of the system firmware.   And like a reboot
1987	  you can start any kernel with it, not just Linux.
1988
1989	  It is an ongoing process to be certain the hardware in a machine
1990	  is properly shutdown, so do not be surprised if this code does not
1991	  initially work for you.
1992
1993config ATAGS_PROC
1994	bool "Export atags in procfs"
1995	depends on ATAGS && KEXEC
1996	default y
1997	help
1998	  Should the atags used to boot the kernel be exported in an "atags"
1999	  file in procfs. Useful with kexec.
2000
2001config CRASH_DUMP
2002	bool "Build kdump crash kernel (EXPERIMENTAL)"
2003	help
2004	  Generate crash dump after being started by kexec. This should
2005	  be normally only set in special crash dump kernels which are
2006	  loaded in the main kernel with kexec-tools into a specially
2007	  reserved region and then later executed after a crash by
2008	  kdump/kexec. The crash dump kernel must be compiled to a
2009	  memory address not used by the main kernel
2010
2011	  For more details see Documentation/kdump/kdump.txt
2012
2013config AUTO_ZRELADDR
2014	bool "Auto calculation of the decompressed kernel image address"
2015	help
2016	  ZRELADDR is the physical address where the decompressed kernel
2017	  image will be placed. If AUTO_ZRELADDR is selected, the address
2018	  will be determined at run-time by masking the current IP with
2019	  0xf8000000. This assumes the zImage being placed in the first 128MB
2020	  from start of memory.
2021
2022config EFI_STUB
2023	bool
2024
2025config EFI
2026	bool "UEFI runtime support"
2027	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2028	select UCS2_STRING
2029	select EFI_PARAMS_FROM_FDT
2030	select EFI_STUB
2031	select EFI_ARMSTUB
2032	select EFI_RUNTIME_WRAPPERS
2033	---help---
2034	  This option provides support for runtime services provided
2035	  by UEFI firmware (such as non-volatile variables, realtime
2036	  clock, and platform reset). A UEFI stub is also provided to
2037	  allow the kernel to be booted as an EFI application. This
2038	  is only useful for kernels that may run on systems that have
2039	  UEFI firmware.
2040
2041endmenu
2042
2043menu "CPU Power Management"
2044
2045source "drivers/cpufreq/Kconfig"
2046
2047source "drivers/cpuidle/Kconfig"
2048
2049endmenu
2050
2051menu "Floating point emulation"
2052
2053comment "At least one emulation must be selected"
2054
2055config FPE_NWFPE
2056	bool "NWFPE math emulation"
2057	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2058	---help---
2059	  Say Y to include the NWFPE floating point emulator in the kernel.
2060	  This is necessary to run most binaries. Linux does not currently
2061	  support floating point hardware so you need to say Y here even if
2062	  your machine has an FPA or floating point co-processor podule.
2063
2064	  You may say N here if you are going to load the Acorn FPEmulator
2065	  early in the bootup.
2066
2067config FPE_NWFPE_XP
2068	bool "Support extended precision"
2069	depends on FPE_NWFPE
2070	help
2071	  Say Y to include 80-bit support in the kernel floating-point
2072	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2073	  Note that gcc does not generate 80-bit operations by default,
2074	  so in most cases this option only enlarges the size of the
2075	  floating point emulator without any good reason.
2076
2077	  You almost surely want to say N here.
2078
2079config FPE_FASTFPE
2080	bool "FastFPE math emulation (EXPERIMENTAL)"
2081	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2082	---help---
2083	  Say Y here to include the FAST floating point emulator in the kernel.
2084	  This is an experimental much faster emulator which now also has full
2085	  precision for the mantissa.  It does not support any exceptions.
2086	  It is very simple, and approximately 3-6 times faster than NWFPE.
2087
2088	  It should be sufficient for most programs.  It may be not suitable
2089	  for scientific calculations, but you have to check this for yourself.
2090	  If you do not feel you need a faster FP emulation you should better
2091	  choose NWFPE.
2092
2093config VFP
2094	bool "VFP-format floating point maths"
2095	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2096	help
2097	  Say Y to include VFP support code in the kernel. This is needed
2098	  if your hardware includes a VFP unit.
2099
2100	  Please see <file:Documentation/arm/VFP/release-notes.txt> for
2101	  release notes and additional status information.
2102
2103	  Say N if your target does not have VFP hardware.
2104
2105config VFPv3
2106	bool
2107	depends on VFP
2108	default y if CPU_V7
2109
2110config NEON
2111	bool "Advanced SIMD (NEON) Extension support"
2112	depends on VFPv3 && CPU_V7
2113	help
2114	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2115	  Extension.
2116
2117config KERNEL_MODE_NEON
2118	bool "Support for NEON in kernel mode"
2119	depends on NEON && AEABI
2120	help
2121	  Say Y to include support for NEON in kernel mode.
2122
2123endmenu
2124
2125menu "Userspace binary formats"
2126
2127source "fs/Kconfig.binfmt"
2128
2129endmenu
2130
2131menu "Power management options"
2132
2133source "kernel/power/Kconfig"
2134
2135config ARCH_SUSPEND_POSSIBLE
2136	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2137		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2138	def_bool y
2139
2140config ARM_CPU_SUSPEND
2141	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2142	depends on ARCH_SUSPEND_POSSIBLE
2143
2144config ARCH_HIBERNATION_POSSIBLE
2145	bool
2146	depends on MMU
2147	default y if ARCH_SUSPEND_POSSIBLE
2148
2149endmenu
2150
2151source "net/Kconfig"
2152
2153source "drivers/Kconfig"
2154
2155source "drivers/firmware/Kconfig"
2156
2157source "fs/Kconfig"
2158
2159source "arch/arm/Kconfig.debug"
2160
2161source "security/Kconfig"
2162
2163source "crypto/Kconfig"
2164if CRYPTO
2165source "arch/arm/crypto/Kconfig"
2166endif
2167
2168source "lib/Kconfig"
2169
2170source "arch/arm/kvm/Kconfig"
2171