1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_DEVMEM_IS_ALLOWED 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_HAVE_CUSTOM_GPIO_H 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_MIGHT_HAVE_PC_PARPORT 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_USE_BUILTIN_BSWAP 13 select ARCH_USE_CMPXCHG_LOCKREF 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_EXTABLE_SORT if MMU 16 select CLONE_BACKWARDS 17 select CPU_PM if (SUSPEND || CPU_IDLE) 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 19 select EDAC_SUPPORT 20 select EDAC_ATOMIC_SCRUB 21 select GENERIC_ALLOCATOR 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_EARLY_IOREMAP 25 select GENERIC_IDLE_POLL_SETUP 26 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW_LEVEL 29 select GENERIC_PCI_IOMAP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select HANDLE_DOMAIN_IRQ 35 select HARDIRQS_SW_RESEND 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 40 select HAVE_ARCH_MMAP_RND_BITS if MMU 41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 42 select HAVE_ARCH_TRACEHOOK 43 select HAVE_ARM_SMCCC if CPU_V7 44 select HAVE_CBPF_JIT 45 select HAVE_CC_STACKPROTECTOR 46 select HAVE_CONTEXT_TRACKING 47 select HAVE_C_RECORDMCOUNT 48 select HAVE_DEBUG_KMEMLEAK 49 select HAVE_DMA_API_DEBUG 50 select HAVE_DMA_CONTIGUOUS if MMU 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 53 select HAVE_EXIT_THREAD 54 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 55 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 56 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 57 select HAVE_GENERIC_DMA_COHERENT 58 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 59 select HAVE_IDE if PCI || ISA || PCMCIA 60 select HAVE_IRQ_TIME_ACCOUNTING 61 select HAVE_KERNEL_GZIP 62 select HAVE_KERNEL_LZ4 63 select HAVE_KERNEL_LZMA 64 select HAVE_KERNEL_LZO 65 select HAVE_KERNEL_XZ 66 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 67 select HAVE_KRETPROBES if (HAVE_KPROBES) 68 select HAVE_MEMBLOCK 69 select HAVE_MOD_ARCH_SPECIFIC 70 select HAVE_NMI 71 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 72 select HAVE_OPTPROBES if !THUMB2_KERNEL 73 select HAVE_PERF_EVENTS 74 select HAVE_PERF_REGS 75 select HAVE_PERF_USER_STACK_DUMP 76 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 77 select HAVE_REGS_AND_STACK_ACCESS_API 78 select HAVE_SYSCALL_TRACEPOINTS 79 select HAVE_UID16 80 select HAVE_VIRT_CPU_ACCOUNTING_GEN 81 select IRQ_FORCED_THREADING 82 select MODULES_USE_ELF_REL 83 select NO_BOOTMEM 84 select OF_EARLY_FLATTREE if OF 85 select OF_RESERVED_MEM if OF 86 select OLD_SIGACTION 87 select OLD_SIGSUSPEND3 88 select PERF_USE_VMALLOC 89 select RTC_LIB 90 select SYS_SUPPORTS_APM_EMULATION 91 # Above selects are sorted alphabetically; please add new ones 92 # according to that. Thanks. 93 help 94 The ARM series is a line of low-power-consumption RISC chip designs 95 licensed by ARM Ltd and targeted at embedded applications and 96 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 97 manufactured, but legacy ARM-based PC hardware remains popular in 98 Europe. There is an ARM Linux project with a web page at 99 <http://www.arm.linux.org.uk/>. 100 101config ARM_HAS_SG_CHAIN 102 select ARCH_HAS_SG_CHAIN 103 bool 104 105config NEED_SG_DMA_LENGTH 106 bool 107 108config ARM_DMA_USE_IOMMU 109 bool 110 select ARM_HAS_SG_CHAIN 111 select NEED_SG_DMA_LENGTH 112 113if ARM_DMA_USE_IOMMU 114 115config ARM_DMA_IOMMU_ALIGNMENT 116 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 117 range 4 9 118 default 8 119 help 120 DMA mapping framework by default aligns all buffers to the smallest 121 PAGE_SIZE order which is greater than or equal to the requested buffer 122 size. This works well for buffers up to a few hundreds kilobytes, but 123 for larger buffers it just a waste of address space. Drivers which has 124 relatively small addressing window (like 64Mib) might run out of 125 virtual space with just a few allocations. 126 127 With this parameter you can specify the maximum PAGE_SIZE order for 128 DMA IOMMU buffers. Larger buffers will be aligned only to this 129 specified order. The order is expressed as a power of two multiplied 130 by the PAGE_SIZE. 131 132endif 133 134config MIGHT_HAVE_PCI 135 bool 136 137config SYS_SUPPORTS_APM_EMULATION 138 bool 139 140config HAVE_TCM 141 bool 142 select GENERIC_ALLOCATOR 143 144config HAVE_PROC_CPU 145 bool 146 147config NO_IOPORT_MAP 148 bool 149 150config EISA 151 bool 152 ---help--- 153 The Extended Industry Standard Architecture (EISA) bus was 154 developed as an open alternative to the IBM MicroChannel bus. 155 156 The EISA bus provided some of the features of the IBM MicroChannel 157 bus while maintaining backward compatibility with cards made for 158 the older ISA bus. The EISA bus saw limited use between 1988 and 159 1995 when it was made obsolete by the PCI bus. 160 161 Say Y here if you are building a kernel for an EISA-based machine. 162 163 Otherwise, say N. 164 165config SBUS 166 bool 167 168config STACKTRACE_SUPPORT 169 bool 170 default y 171 172config LOCKDEP_SUPPORT 173 bool 174 default y 175 176config TRACE_IRQFLAGS_SUPPORT 177 bool 178 default !CPU_V7M 179 180config RWSEM_XCHGADD_ALGORITHM 181 bool 182 default y 183 184config ARCH_HAS_ILOG2_U32 185 bool 186 187config ARCH_HAS_ILOG2_U64 188 bool 189 190config ARCH_HAS_BANDGAP 191 bool 192 193config FIX_EARLYCON_MEM 194 def_bool y if MMU 195 196config GENERIC_HWEIGHT 197 bool 198 default y 199 200config GENERIC_CALIBRATE_DELAY 201 bool 202 default y 203 204config ARCH_MAY_HAVE_PC_FDC 205 bool 206 207config ZONE_DMA 208 bool 209 210config NEED_DMA_MAP_STATE 211 def_bool y 212 213config ARCH_SUPPORTS_UPROBES 214 def_bool y 215 216config ARCH_HAS_DMA_SET_COHERENT_MASK 217 bool 218 219config GENERIC_ISA_DMA 220 bool 221 222config FIQ 223 bool 224 225config NEED_RET_TO_USER 226 bool 227 228config ARCH_MTD_XIP 229 bool 230 231config VECTORS_BASE 232 hex 233 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 234 default DRAM_BASE if REMAP_VECTORS_TO_RAM 235 default 0x00000000 236 help 237 The base address of exception vectors. This must be two pages 238 in size. 239 240config ARM_PATCH_PHYS_VIRT 241 bool "Patch physical to virtual translations at runtime" if EMBEDDED 242 default y 243 depends on !XIP_KERNEL && MMU 244 help 245 Patch phys-to-virt and virt-to-phys translation functions at 246 boot and module load time according to the position of the 247 kernel in system memory. 248 249 This can only be used with non-XIP MMU kernels where the base 250 of physical memory is at a 16MB boundary. 251 252 Only disable this option if you know that you do not require 253 this feature (eg, building a kernel for a single machine) and 254 you need to shrink the kernel to the minimal size. 255 256config NEED_MACH_IO_H 257 bool 258 help 259 Select this when mach/io.h is required to provide special 260 definitions for this platform. The need for mach/io.h should 261 be avoided when possible. 262 263config NEED_MACH_MEMORY_H 264 bool 265 help 266 Select this when mach/memory.h is required to provide special 267 definitions for this platform. The need for mach/memory.h should 268 be avoided when possible. 269 270config PHYS_OFFSET 271 hex "Physical address of main memory" if MMU 272 depends on !ARM_PATCH_PHYS_VIRT 273 default DRAM_BASE if !MMU 274 default 0x00000000 if ARCH_EBSA110 || \ 275 ARCH_FOOTBRIDGE || \ 276 ARCH_INTEGRATOR || \ 277 ARCH_IOP13XX || \ 278 ARCH_KS8695 || \ 279 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x20000000 if ARCH_S5PV210 282 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 283 default 0xc0000000 if ARCH_SA1100 284 help 285 Please provide the physical address corresponding to the 286 location of main memory in your system. 287 288config GENERIC_BUG 289 def_bool y 290 depends on BUG 291 292config PGTABLE_LEVELS 293 int 294 default 3 if ARM_LPAE 295 default 2 296 297source "init/Kconfig" 298 299source "kernel/Kconfig.freezer" 300 301menu "System Type" 302 303config MMU 304 bool "MMU-based Paged Memory Management Support" 305 default y 306 help 307 Select if you want MMU-based virtualised addressing space 308 support by paged memory management. If unsure, say 'Y'. 309 310config ARCH_MMAP_RND_BITS_MIN 311 default 8 312 313config ARCH_MMAP_RND_BITS_MAX 314 default 14 if PAGE_OFFSET=0x40000000 315 default 15 if PAGE_OFFSET=0x80000000 316 default 16 317 318# 319# The "ARM system type" choice list is ordered alphabetically by option 320# text. Please add new entries in the option alphabetic order. 321# 322choice 323 prompt "ARM system type" 324 default ARM_SINGLE_ARMV7M if !MMU 325 default ARCH_MULTIPLATFORM if MMU 326 327config ARCH_MULTIPLATFORM 328 bool "Allow multiple platforms to be selected" 329 depends on MMU 330 select ARM_HAS_SG_CHAIN 331 select ARM_PATCH_PHYS_VIRT 332 select AUTO_ZRELADDR 333 select CLKSRC_OF 334 select COMMON_CLK 335 select GENERIC_CLOCKEVENTS 336 select MIGHT_HAVE_PCI 337 select MULTI_IRQ_HANDLER 338 select SPARSE_IRQ 339 select USE_OF 340 341config ARM_SINGLE_ARMV7M 342 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 343 depends on !MMU 344 select ARM_NVIC 345 select AUTO_ZRELADDR 346 select CLKSRC_OF 347 select COMMON_CLK 348 select CPU_V7M 349 select GENERIC_CLOCKEVENTS 350 select NO_IOPORT_MAP 351 select SPARSE_IRQ 352 select USE_OF 353 354config ARCH_GEMINI 355 bool "Cortina Systems Gemini" 356 select CLKSRC_MMIO 357 select CPU_FA526 358 select GENERIC_CLOCKEVENTS 359 select GPIOLIB 360 help 361 Support for the Cortina Systems Gemini family SoCs 362 363config ARCH_EBSA110 364 bool "EBSA-110" 365 select ARCH_USES_GETTIMEOFFSET 366 select CPU_SA110 367 select ISA 368 select NEED_MACH_IO_H 369 select NEED_MACH_MEMORY_H 370 select NO_IOPORT_MAP 371 help 372 This is an evaluation board for the StrongARM processor available 373 from Digital. It has limited hardware on-board, including an 374 Ethernet interface, two PCMCIA sockets, two serial ports and a 375 parallel port. 376 377config ARCH_EP93XX 378 bool "EP93xx-based" 379 select ARCH_HAS_HOLES_MEMORYMODEL 380 select ARM_AMBA 381 select ARM_PATCH_PHYS_VIRT 382 select ARM_VIC 383 select AUTO_ZRELADDR 384 select CLKDEV_LOOKUP 385 select CLKSRC_MMIO 386 select CPU_ARM920T 387 select GENERIC_CLOCKEVENTS 388 select GPIOLIB 389 help 390 This enables support for the Cirrus EP93xx series of CPUs. 391 392config ARCH_FOOTBRIDGE 393 bool "FootBridge" 394 select CPU_SA110 395 select FOOTBRIDGE 396 select GENERIC_CLOCKEVENTS 397 select HAVE_IDE 398 select NEED_MACH_IO_H if !MMU 399 select NEED_MACH_MEMORY_H 400 help 401 Support for systems based on the DC21285 companion chip 402 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 403 404config ARCH_NETX 405 bool "Hilscher NetX based" 406 select ARM_VIC 407 select CLKSRC_MMIO 408 select CPU_ARM926T 409 select GENERIC_CLOCKEVENTS 410 help 411 This enables support for systems based on the Hilscher NetX Soc 412 413config ARCH_IOP13XX 414 bool "IOP13xx-based" 415 depends on MMU 416 select CPU_XSC3 417 select NEED_MACH_MEMORY_H 418 select NEED_RET_TO_USER 419 select PCI 420 select PLAT_IOP 421 select VMSPLIT_1G 422 select SPARSE_IRQ 423 help 424 Support for Intel's IOP13XX (XScale) family of processors. 425 426config ARCH_IOP32X 427 bool "IOP32x-based" 428 depends on MMU 429 select CPU_XSCALE 430 select GPIO_IOP 431 select GPIOLIB 432 select NEED_RET_TO_USER 433 select PCI 434 select PLAT_IOP 435 help 436 Support for Intel's 80219 and IOP32X (XScale) family of 437 processors. 438 439config ARCH_IOP33X 440 bool "IOP33x-based" 441 depends on MMU 442 select CPU_XSCALE 443 select GPIO_IOP 444 select GPIOLIB 445 select NEED_RET_TO_USER 446 select PCI 447 select PLAT_IOP 448 help 449 Support for Intel's IOP33X (XScale) family of processors. 450 451config ARCH_IXP4XX 452 bool "IXP4xx-based" 453 depends on MMU 454 select ARCH_HAS_DMA_SET_COHERENT_MASK 455 select ARCH_SUPPORTS_BIG_ENDIAN 456 select CLKSRC_MMIO 457 select CPU_XSCALE 458 select DMABOUNCE if PCI 459 select GENERIC_CLOCKEVENTS 460 select GPIOLIB 461 select MIGHT_HAVE_PCI 462 select NEED_MACH_IO_H 463 select USB_EHCI_BIG_ENDIAN_DESC 464 select USB_EHCI_BIG_ENDIAN_MMIO 465 help 466 Support for Intel's IXP4XX (XScale) family of processors. 467 468config ARCH_DOVE 469 bool "Marvell Dove" 470 select CPU_PJ4 471 select GENERIC_CLOCKEVENTS 472 select GPIOLIB 473 select MIGHT_HAVE_PCI 474 select MULTI_IRQ_HANDLER 475 select MVEBU_MBUS 476 select PINCTRL 477 select PINCTRL_DOVE 478 select PLAT_ORION_LEGACY 479 select SPARSE_IRQ 480 select PM_GENERIC_DOMAINS if PM 481 help 482 Support for the Marvell Dove SoC 88AP510 483 484config ARCH_KS8695 485 bool "Micrel/Kendin KS8695" 486 select CLKSRC_MMIO 487 select CPU_ARM922T 488 select GENERIC_CLOCKEVENTS 489 select GPIOLIB 490 select NEED_MACH_MEMORY_H 491 help 492 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 493 System-on-Chip devices. 494 495config ARCH_W90X900 496 bool "Nuvoton W90X900 CPU" 497 select CLKDEV_LOOKUP 498 select CLKSRC_MMIO 499 select CPU_ARM926T 500 select GENERIC_CLOCKEVENTS 501 select GPIOLIB 502 help 503 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 504 At present, the w90x900 has been renamed nuc900, regarding 505 the ARM series product line, you can login the following 506 link address to know more. 507 508 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 509 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 510 511config ARCH_LPC32XX 512 bool "NXP LPC32XX" 513 select ARM_AMBA 514 select CLKDEV_LOOKUP 515 select CLKSRC_LPC32XX 516 select COMMON_CLK 517 select CPU_ARM926T 518 select GENERIC_CLOCKEVENTS 519 select GPIOLIB 520 select MULTI_IRQ_HANDLER 521 select SPARSE_IRQ 522 select USE_OF 523 help 524 Support for the NXP LPC32XX family of processors 525 526config ARCH_PXA 527 bool "PXA2xx/PXA3xx-based" 528 depends on MMU 529 select ARCH_MTD_XIP 530 select ARM_CPU_SUSPEND if PM 531 select AUTO_ZRELADDR 532 select COMMON_CLK 533 select CLKDEV_LOOKUP 534 select CLKSRC_PXA 535 select CLKSRC_MMIO 536 select CLKSRC_OF 537 select CPU_XSCALE if !CPU_XSC3 538 select GENERIC_CLOCKEVENTS 539 select GPIO_PXA 540 select GPIOLIB 541 select HAVE_IDE 542 select IRQ_DOMAIN 543 select MULTI_IRQ_HANDLER 544 select PLAT_PXA 545 select SPARSE_IRQ 546 help 547 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 548 549config ARCH_RPC 550 bool "RiscPC" 551 depends on MMU 552 select ARCH_ACORN 553 select ARCH_MAY_HAVE_PC_FDC 554 select ARCH_SPARSEMEM_ENABLE 555 select ARCH_USES_GETTIMEOFFSET 556 select CPU_SA110 557 select FIQ 558 select HAVE_IDE 559 select HAVE_PATA_PLATFORM 560 select ISA_DMA_API 561 select NEED_MACH_IO_H 562 select NEED_MACH_MEMORY_H 563 select NO_IOPORT_MAP 564 help 565 On the Acorn Risc-PC, Linux can support the internal IDE disk and 566 CD-ROM interface, serial and parallel port, and the floppy drive. 567 568config ARCH_SA1100 569 bool "SA1100-based" 570 select ARCH_MTD_XIP 571 select ARCH_SPARSEMEM_ENABLE 572 select CLKDEV_LOOKUP 573 select CLKSRC_MMIO 574 select CLKSRC_PXA 575 select CLKSRC_OF if OF 576 select CPU_FREQ 577 select CPU_SA1100 578 select GENERIC_CLOCKEVENTS 579 select GPIOLIB 580 select HAVE_IDE 581 select IRQ_DOMAIN 582 select ISA 583 select MULTI_IRQ_HANDLER 584 select NEED_MACH_MEMORY_H 585 select SPARSE_IRQ 586 help 587 Support for StrongARM 11x0 based boards. 588 589config ARCH_S3C24XX 590 bool "Samsung S3C24XX SoCs" 591 select ATAGS 592 select CLKDEV_LOOKUP 593 select CLKSRC_SAMSUNG_PWM 594 select GENERIC_CLOCKEVENTS 595 select GPIO_SAMSUNG 596 select GPIOLIB 597 select HAVE_S3C2410_I2C if I2C 598 select HAVE_S3C2410_WATCHDOG if WATCHDOG 599 select HAVE_S3C_RTC if RTC_CLASS 600 select MULTI_IRQ_HANDLER 601 select NEED_MACH_IO_H 602 select SAMSUNG_ATAGS 603 help 604 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 605 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 606 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 607 Samsung SMDK2410 development board (and derivatives). 608 609config ARCH_DAVINCI 610 bool "TI DaVinci" 611 select ARCH_HAS_HOLES_MEMORYMODEL 612 select CLKDEV_LOOKUP 613 select CPU_ARM926T 614 select GENERIC_ALLOCATOR 615 select GENERIC_CLOCKEVENTS 616 select GENERIC_IRQ_CHIP 617 select GPIOLIB 618 select HAVE_IDE 619 select USE_OF 620 select ZONE_DMA 621 help 622 Support for TI's DaVinci platform. 623 624config ARCH_OMAP1 625 bool "TI OMAP1" 626 depends on MMU 627 select ARCH_HAS_HOLES_MEMORYMODEL 628 select ARCH_OMAP 629 select CLKDEV_LOOKUP 630 select CLKSRC_MMIO 631 select GENERIC_CLOCKEVENTS 632 select GENERIC_IRQ_CHIP 633 select GPIOLIB 634 select HAVE_IDE 635 select IRQ_DOMAIN 636 select MULTI_IRQ_HANDLER 637 select NEED_MACH_IO_H if PCCARD 638 select NEED_MACH_MEMORY_H 639 select SPARSE_IRQ 640 help 641 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 642 643endchoice 644 645menu "Multiple platform selection" 646 depends on ARCH_MULTIPLATFORM 647 648comment "CPU Core family selection" 649 650config ARCH_MULTI_V4 651 bool "ARMv4 based platforms (FA526)" 652 depends on !ARCH_MULTI_V6_V7 653 select ARCH_MULTI_V4_V5 654 select CPU_FA526 655 656config ARCH_MULTI_V4T 657 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 658 depends on !ARCH_MULTI_V6_V7 659 select ARCH_MULTI_V4_V5 660 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 661 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 662 CPU_ARM925T || CPU_ARM940T) 663 664config ARCH_MULTI_V5 665 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 666 depends on !ARCH_MULTI_V6_V7 667 select ARCH_MULTI_V4_V5 668 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 669 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 670 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 671 672config ARCH_MULTI_V4_V5 673 bool 674 675config ARCH_MULTI_V6 676 bool "ARMv6 based platforms (ARM11)" 677 select ARCH_MULTI_V6_V7 678 select CPU_V6K 679 680config ARCH_MULTI_V7 681 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 682 default y 683 select ARCH_MULTI_V6_V7 684 select CPU_V7 685 select HAVE_SMP 686 687config ARCH_MULTI_V6_V7 688 bool 689 select MIGHT_HAVE_CACHE_L2X0 690 691config ARCH_MULTI_CPU_AUTO 692 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 693 select ARCH_MULTI_V5 694 695endmenu 696 697config ARCH_VIRT 698 bool "Dummy Virtual Machine" 699 depends on ARCH_MULTI_V7 700 select ARM_AMBA 701 select ARM_GIC 702 select ARM_GIC_V2M if PCI_MSI 703 select ARM_GIC_V3 704 select ARM_PSCI 705 select HAVE_ARM_ARCH_TIMER 706 707# 708# This is sorted alphabetically by mach-* pathname. However, plat-* 709# Kconfigs may be included either alphabetically (according to the 710# plat- suffix) or along side the corresponding mach-* source. 711# 712source "arch/arm/mach-mvebu/Kconfig" 713 714source "arch/arm/mach-alpine/Kconfig" 715 716source "arch/arm/mach-artpec/Kconfig" 717 718source "arch/arm/mach-asm9260/Kconfig" 719 720source "arch/arm/mach-at91/Kconfig" 721 722source "arch/arm/mach-axxia/Kconfig" 723 724source "arch/arm/mach-bcm/Kconfig" 725 726source "arch/arm/mach-berlin/Kconfig" 727 728source "arch/arm/mach-clps711x/Kconfig" 729 730source "arch/arm/mach-cns3xxx/Kconfig" 731 732source "arch/arm/mach-davinci/Kconfig" 733 734source "arch/arm/mach-digicolor/Kconfig" 735 736source "arch/arm/mach-dove/Kconfig" 737 738source "arch/arm/mach-ep93xx/Kconfig" 739 740source "arch/arm/mach-footbridge/Kconfig" 741 742source "arch/arm/mach-gemini/Kconfig" 743 744source "arch/arm/mach-highbank/Kconfig" 745 746source "arch/arm/mach-hisi/Kconfig" 747 748source "arch/arm/mach-integrator/Kconfig" 749 750source "arch/arm/mach-iop32x/Kconfig" 751 752source "arch/arm/mach-iop33x/Kconfig" 753 754source "arch/arm/mach-iop13xx/Kconfig" 755 756source "arch/arm/mach-ixp4xx/Kconfig" 757 758source "arch/arm/mach-keystone/Kconfig" 759 760source "arch/arm/mach-ks8695/Kconfig" 761 762source "arch/arm/mach-meson/Kconfig" 763 764source "arch/arm/mach-moxart/Kconfig" 765 766source "arch/arm/mach-aspeed/Kconfig" 767 768source "arch/arm/mach-mv78xx0/Kconfig" 769 770source "arch/arm/mach-imx/Kconfig" 771 772source "arch/arm/mach-mediatek/Kconfig" 773 774source "arch/arm/mach-mxs/Kconfig" 775 776source "arch/arm/mach-netx/Kconfig" 777 778source "arch/arm/mach-nomadik/Kconfig" 779 780source "arch/arm/mach-nspire/Kconfig" 781 782source "arch/arm/plat-omap/Kconfig" 783 784source "arch/arm/mach-omap1/Kconfig" 785 786source "arch/arm/mach-omap2/Kconfig" 787 788source "arch/arm/mach-orion5x/Kconfig" 789 790source "arch/arm/mach-picoxcell/Kconfig" 791 792source "arch/arm/mach-pxa/Kconfig" 793source "arch/arm/plat-pxa/Kconfig" 794 795source "arch/arm/mach-mmp/Kconfig" 796 797source "arch/arm/mach-oxnas/Kconfig" 798 799source "arch/arm/mach-qcom/Kconfig" 800 801source "arch/arm/mach-realview/Kconfig" 802 803source "arch/arm/mach-rockchip/Kconfig" 804 805source "arch/arm/mach-sa1100/Kconfig" 806 807source "arch/arm/mach-socfpga/Kconfig" 808 809source "arch/arm/mach-spear/Kconfig" 810 811source "arch/arm/mach-sti/Kconfig" 812 813source "arch/arm/mach-s3c24xx/Kconfig" 814 815source "arch/arm/mach-s3c64xx/Kconfig" 816 817source "arch/arm/mach-s5pv210/Kconfig" 818 819source "arch/arm/mach-exynos/Kconfig" 820source "arch/arm/plat-samsung/Kconfig" 821 822source "arch/arm/mach-shmobile/Kconfig" 823 824source "arch/arm/mach-sunxi/Kconfig" 825 826source "arch/arm/mach-prima2/Kconfig" 827 828source "arch/arm/mach-tango/Kconfig" 829 830source "arch/arm/mach-tegra/Kconfig" 831 832source "arch/arm/mach-u300/Kconfig" 833 834source "arch/arm/mach-uniphier/Kconfig" 835 836source "arch/arm/mach-ux500/Kconfig" 837 838source "arch/arm/mach-versatile/Kconfig" 839 840source "arch/arm/mach-vexpress/Kconfig" 841source "arch/arm/plat-versatile/Kconfig" 842 843source "arch/arm/mach-vt8500/Kconfig" 844 845source "arch/arm/mach-w90x900/Kconfig" 846 847source "arch/arm/mach-zx/Kconfig" 848 849source "arch/arm/mach-zynq/Kconfig" 850 851# ARMv7-M architecture 852config ARCH_EFM32 853 bool "Energy Micro efm32" 854 depends on ARM_SINGLE_ARMV7M 855 select GPIOLIB 856 help 857 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 858 processors. 859 860config ARCH_LPC18XX 861 bool "NXP LPC18xx/LPC43xx" 862 depends on ARM_SINGLE_ARMV7M 863 select ARCH_HAS_RESET_CONTROLLER 864 select ARM_AMBA 865 select CLKSRC_LPC32XX 866 select PINCTRL 867 help 868 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 869 high performance microcontrollers. 870 871config ARCH_STM32 872 bool "STMicrolectronics STM32" 873 depends on ARM_SINGLE_ARMV7M 874 select ARCH_HAS_RESET_CONTROLLER 875 select ARMV7M_SYSTICK 876 select CLKSRC_STM32 877 select PINCTRL 878 select RESET_CONTROLLER 879 help 880 Support for STMicroelectronics STM32 processors. 881 882config MACH_STM32F429 883 bool "STMicrolectronics STM32F429" 884 depends on ARCH_STM32 885 default y 886 887config ARCH_MPS2 888 bool "ARM MPS2 platform" 889 depends on ARM_SINGLE_ARMV7M 890 select ARM_AMBA 891 select CLKSRC_MPS2 892 help 893 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 894 with a range of available cores like Cortex-M3/M4/M7. 895 896 Please, note that depends which Application Note is used memory map 897 for the platform may vary, so adjustment of RAM base might be needed. 898 899# Definitions to make life easier 900config ARCH_ACORN 901 bool 902 903config PLAT_IOP 904 bool 905 select GENERIC_CLOCKEVENTS 906 907config PLAT_ORION 908 bool 909 select CLKSRC_MMIO 910 select COMMON_CLK 911 select GENERIC_IRQ_CHIP 912 select IRQ_DOMAIN 913 914config PLAT_ORION_LEGACY 915 bool 916 select PLAT_ORION 917 918config PLAT_PXA 919 bool 920 921config PLAT_VERSATILE 922 bool 923 924source "arch/arm/firmware/Kconfig" 925 926source arch/arm/mm/Kconfig 927 928config IWMMXT 929 bool "Enable iWMMXt support" 930 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 931 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 932 help 933 Enable support for iWMMXt context switching at run time if 934 running on a CPU that supports it. 935 936config MULTI_IRQ_HANDLER 937 bool 938 help 939 Allow each machine to specify it's own IRQ handler at run time. 940 941if !MMU 942source "arch/arm/Kconfig-nommu" 943endif 944 945config PJ4B_ERRATA_4742 946 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 947 depends on CPU_PJ4B && MACH_ARMADA_370 948 default y 949 help 950 When coming out of either a Wait for Interrupt (WFI) or a Wait for 951 Event (WFE) IDLE states, a specific timing sensitivity exists between 952 the retiring WFI/WFE instructions and the newly issued subsequent 953 instructions. This sensitivity can result in a CPU hang scenario. 954 Workaround: 955 The software must insert either a Data Synchronization Barrier (DSB) 956 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 957 instruction 958 959config ARM_ERRATA_326103 960 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 961 depends on CPU_V6 962 help 963 Executing a SWP instruction to read-only memory does not set bit 11 964 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 965 treat the access as a read, preventing a COW from occurring and 966 causing the faulting task to livelock. 967 968config ARM_ERRATA_411920 969 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 970 depends on CPU_V6 || CPU_V6K 971 help 972 Invalidation of the Instruction Cache operation can 973 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 974 It does not affect the MPCore. This option enables the ARM Ltd. 975 recommended workaround. 976 977config ARM_ERRATA_430973 978 bool "ARM errata: Stale prediction on replaced interworking branch" 979 depends on CPU_V7 980 help 981 This option enables the workaround for the 430973 Cortex-A8 982 r1p* erratum. If a code sequence containing an ARM/Thumb 983 interworking branch is replaced with another code sequence at the 984 same virtual address, whether due to self-modifying code or virtual 985 to physical address re-mapping, Cortex-A8 does not recover from the 986 stale interworking branch prediction. This results in Cortex-A8 987 executing the new code sequence in the incorrect ARM or Thumb state. 988 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 989 and also flushes the branch target cache at every context switch. 990 Note that setting specific bits in the ACTLR register may not be 991 available in non-secure mode. 992 993config ARM_ERRATA_458693 994 bool "ARM errata: Processor deadlock when a false hazard is created" 995 depends on CPU_V7 996 depends on !ARCH_MULTIPLATFORM 997 help 998 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 999 erratum. For very specific sequences of memory operations, it is 1000 possible for a hazard condition intended for a cache line to instead 1001 be incorrectly associated with a different cache line. This false 1002 hazard might then cause a processor deadlock. The workaround enables 1003 the L1 caching of the NEON accesses and disables the PLD instruction 1004 in the ACTLR register. Note that setting specific bits in the ACTLR 1005 register may not be available in non-secure mode. 1006 1007config ARM_ERRATA_460075 1008 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1009 depends on CPU_V7 1010 depends on !ARCH_MULTIPLATFORM 1011 help 1012 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1013 erratum. Any asynchronous access to the L2 cache may encounter a 1014 situation in which recent store transactions to the L2 cache are lost 1015 and overwritten with stale memory contents from external memory. The 1016 workaround disables the write-allocate mode for the L2 cache via the 1017 ACTLR register. Note that setting specific bits in the ACTLR register 1018 may not be available in non-secure mode. 1019 1020config ARM_ERRATA_742230 1021 bool "ARM errata: DMB operation may be faulty" 1022 depends on CPU_V7 && SMP 1023 depends on !ARCH_MULTIPLATFORM 1024 help 1025 This option enables the workaround for the 742230 Cortex-A9 1026 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1027 between two write operations may not ensure the correct visibility 1028 ordering of the two writes. This workaround sets a specific bit in 1029 the diagnostic register of the Cortex-A9 which causes the DMB 1030 instruction to behave as a DSB, ensuring the correct behaviour of 1031 the two writes. 1032 1033config ARM_ERRATA_742231 1034 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1035 depends on CPU_V7 && SMP 1036 depends on !ARCH_MULTIPLATFORM 1037 help 1038 This option enables the workaround for the 742231 Cortex-A9 1039 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1040 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1041 accessing some data located in the same cache line, may get corrupted 1042 data due to bad handling of the address hazard when the line gets 1043 replaced from one of the CPUs at the same time as another CPU is 1044 accessing it. This workaround sets specific bits in the diagnostic 1045 register of the Cortex-A9 which reduces the linefill issuing 1046 capabilities of the processor. 1047 1048config ARM_ERRATA_643719 1049 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1050 depends on CPU_V7 && SMP 1051 default y 1052 help 1053 This option enables the workaround for the 643719 Cortex-A9 (prior to 1054 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1055 register returns zero when it should return one. The workaround 1056 corrects this value, ensuring cache maintenance operations which use 1057 it behave as intended and avoiding data corruption. 1058 1059config ARM_ERRATA_720789 1060 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1061 depends on CPU_V7 1062 help 1063 This option enables the workaround for the 720789 Cortex-A9 (prior to 1064 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1065 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1066 As a consequence of this erratum, some TLB entries which should be 1067 invalidated are not, resulting in an incoherency in the system page 1068 tables. The workaround changes the TLB flushing routines to invalidate 1069 entries regardless of the ASID. 1070 1071config ARM_ERRATA_743622 1072 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1073 depends on CPU_V7 1074 depends on !ARCH_MULTIPLATFORM 1075 help 1076 This option enables the workaround for the 743622 Cortex-A9 1077 (r2p*) erratum. Under very rare conditions, a faulty 1078 optimisation in the Cortex-A9 Store Buffer may lead to data 1079 corruption. This workaround sets a specific bit in the diagnostic 1080 register of the Cortex-A9 which disables the Store Buffer 1081 optimisation, preventing the defect from occurring. This has no 1082 visible impact on the overall performance or power consumption of the 1083 processor. 1084 1085config ARM_ERRATA_751472 1086 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1087 depends on CPU_V7 1088 depends on !ARCH_MULTIPLATFORM 1089 help 1090 This option enables the workaround for the 751472 Cortex-A9 (prior 1091 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1092 completion of a following broadcasted operation if the second 1093 operation is received by a CPU before the ICIALLUIS has completed, 1094 potentially leading to corrupted entries in the cache or TLB. 1095 1096config ARM_ERRATA_754322 1097 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1098 depends on CPU_V7 1099 help 1100 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1101 r3p*) erratum. A speculative memory access may cause a page table walk 1102 which starts prior to an ASID switch but completes afterwards. This 1103 can populate the micro-TLB with a stale entry which may be hit with 1104 the new ASID. This workaround places two dsb instructions in the mm 1105 switching code so that no page table walks can cross the ASID switch. 1106 1107config ARM_ERRATA_754327 1108 bool "ARM errata: no automatic Store Buffer drain" 1109 depends on CPU_V7 && SMP 1110 help 1111 This option enables the workaround for the 754327 Cortex-A9 (prior to 1112 r2p0) erratum. The Store Buffer does not have any automatic draining 1113 mechanism and therefore a livelock may occur if an external agent 1114 continuously polls a memory location waiting to observe an update. 1115 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1116 written polling loops from denying visibility of updates to memory. 1117 1118config ARM_ERRATA_364296 1119 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1120 depends on CPU_V6 1121 help 1122 This options enables the workaround for the 364296 ARM1136 1123 r0p2 erratum (possible cache data corruption with 1124 hit-under-miss enabled). It sets the undocumented bit 31 in 1125 the auxiliary control register and the FI bit in the control 1126 register, thus disabling hit-under-miss without putting the 1127 processor into full low interrupt latency mode. ARM11MPCore 1128 is not affected. 1129 1130config ARM_ERRATA_764369 1131 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1132 depends on CPU_V7 && SMP 1133 help 1134 This option enables the workaround for erratum 764369 1135 affecting Cortex-A9 MPCore with two or more processors (all 1136 current revisions). Under certain timing circumstances, a data 1137 cache line maintenance operation by MVA targeting an Inner 1138 Shareable memory region may fail to proceed up to either the 1139 Point of Coherency or to the Point of Unification of the 1140 system. This workaround adds a DSB instruction before the 1141 relevant cache maintenance functions and sets a specific bit 1142 in the diagnostic control register of the SCU. 1143 1144config ARM_ERRATA_775420 1145 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1146 depends on CPU_V7 1147 help 1148 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1149 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1150 operation aborts with MMU exception, it might cause the processor 1151 to deadlock. This workaround puts DSB before executing ISB if 1152 an abort may occur on cache maintenance. 1153 1154config ARM_ERRATA_798181 1155 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1156 depends on CPU_V7 && SMP 1157 help 1158 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1159 adequately shooting down all use of the old entries. This 1160 option enables the Linux kernel workaround for this erratum 1161 which sends an IPI to the CPUs that are running the same ASID 1162 as the one being invalidated. 1163 1164config ARM_ERRATA_773022 1165 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1166 depends on CPU_V7 1167 help 1168 This option enables the workaround for the 773022 Cortex-A15 1169 (up to r0p4) erratum. In certain rare sequences of code, the 1170 loop buffer may deliver incorrect instructions. This 1171 workaround disables the loop buffer to avoid the erratum. 1172 1173config ARM_ERRATA_818325_852422 1174 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1175 depends on CPU_V7 1176 help 1177 This option enables the workaround for: 1178 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1179 instruction might deadlock. Fixed in r0p1. 1180 - Cortex-A12 852422: Execution of a sequence of instructions might 1181 lead to either a data corruption or a CPU deadlock. Not fixed in 1182 any Cortex-A12 cores yet. 1183 This workaround for all both errata involves setting bit[12] of the 1184 Feature Register. This bit disables an optimisation applied to a 1185 sequence of 2 instructions that use opposing condition codes. 1186 1187config ARM_ERRATA_821420 1188 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1189 depends on CPU_V7 1190 help 1191 This option enables the workaround for the 821420 Cortex-A12 1192 (all revs) erratum. In very rare timing conditions, a sequence 1193 of VMOV to Core registers instructions, for which the second 1194 one is in the shadow of a branch or abort, can lead to a 1195 deadlock when the VMOV instructions are issued out-of-order. 1196 1197config ARM_ERRATA_825619 1198 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1199 depends on CPU_V7 1200 help 1201 This option enables the workaround for the 825619 Cortex-A12 1202 (all revs) erratum. Within rare timing constraints, executing a 1203 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1204 and Device/Strongly-Ordered loads and stores might cause deadlock 1205 1206config ARM_ERRATA_852421 1207 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1208 depends on CPU_V7 1209 help 1210 This option enables the workaround for the 852421 Cortex-A17 1211 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1212 execution of a DMB ST instruction might fail to properly order 1213 stores from GroupA and stores from GroupB. 1214 1215config ARM_ERRATA_852423 1216 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1217 depends on CPU_V7 1218 help 1219 This option enables the workaround for: 1220 - Cortex-A17 852423: Execution of a sequence of instructions might 1221 lead to either a data corruption or a CPU deadlock. Not fixed in 1222 any Cortex-A17 cores yet. 1223 This is identical to Cortex-A12 erratum 852422. It is a separate 1224 config option from the A12 erratum due to the way errata are checked 1225 for and handled. 1226 1227endmenu 1228 1229source "arch/arm/common/Kconfig" 1230 1231menu "Bus support" 1232 1233config ISA 1234 bool 1235 help 1236 Find out whether you have ISA slots on your motherboard. ISA is the 1237 name of a bus system, i.e. the way the CPU talks to the other stuff 1238 inside your box. Other bus systems are PCI, EISA, MicroChannel 1239 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1240 newer boards don't support it. If you have ISA, say Y, otherwise N. 1241 1242# Select ISA DMA controller support 1243config ISA_DMA 1244 bool 1245 select ISA_DMA_API 1246 1247# Select ISA DMA interface 1248config ISA_DMA_API 1249 bool 1250 1251config PCI 1252 bool "PCI support" if MIGHT_HAVE_PCI 1253 help 1254 Find out whether you have a PCI motherboard. PCI is the name of a 1255 bus system, i.e. the way the CPU talks to the other stuff inside 1256 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1257 VESA. If you have PCI, say Y, otherwise N. 1258 1259config PCI_DOMAINS 1260 bool 1261 depends on PCI 1262 1263config PCI_DOMAINS_GENERIC 1264 def_bool PCI_DOMAINS 1265 1266config PCI_NANOENGINE 1267 bool "BSE nanoEngine PCI support" 1268 depends on SA1100_NANOENGINE 1269 help 1270 Enable PCI on the BSE nanoEngine board. 1271 1272config PCI_SYSCALL 1273 def_bool PCI 1274 1275config PCI_HOST_ITE8152 1276 bool 1277 depends on PCI && MACH_ARMCORE 1278 default y 1279 select DMABOUNCE 1280 1281source "drivers/pci/Kconfig" 1282 1283source "drivers/pcmcia/Kconfig" 1284 1285endmenu 1286 1287menu "Kernel Features" 1288 1289config HAVE_SMP 1290 bool 1291 help 1292 This option should be selected by machines which have an SMP- 1293 capable CPU. 1294 1295 The only effect of this option is to make the SMP-related 1296 options available to the user for configuration. 1297 1298config SMP 1299 bool "Symmetric Multi-Processing" 1300 depends on CPU_V6K || CPU_V7 1301 depends on GENERIC_CLOCKEVENTS 1302 depends on HAVE_SMP 1303 depends on MMU || ARM_MPU 1304 select IRQ_WORK 1305 help 1306 This enables support for systems with more than one CPU. If you have 1307 a system with only one CPU, say N. If you have a system with more 1308 than one CPU, say Y. 1309 1310 If you say N here, the kernel will run on uni- and multiprocessor 1311 machines, but will use only one CPU of a multiprocessor machine. If 1312 you say Y here, the kernel will run on many, but not all, 1313 uniprocessor machines. On a uniprocessor machine, the kernel 1314 will run faster if you say N here. 1315 1316 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1317 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1318 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1319 1320 If you don't know what to do here, say N. 1321 1322config SMP_ON_UP 1323 bool "Allow booting SMP kernel on uniprocessor systems" 1324 depends on SMP && !XIP_KERNEL && MMU 1325 default y 1326 help 1327 SMP kernels contain instructions which fail on non-SMP processors. 1328 Enabling this option allows the kernel to modify itself to make 1329 these instructions safe. Disabling it allows about 1K of space 1330 savings. 1331 1332 If you don't know what to do here, say Y. 1333 1334config ARM_CPU_TOPOLOGY 1335 bool "Support cpu topology definition" 1336 depends on SMP && CPU_V7 1337 default y 1338 help 1339 Support ARM cpu topology definition. The MPIDR register defines 1340 affinity between processors which is then used to describe the cpu 1341 topology of an ARM System. 1342 1343config SCHED_MC 1344 bool "Multi-core scheduler support" 1345 depends on ARM_CPU_TOPOLOGY 1346 help 1347 Multi-core scheduler support improves the CPU scheduler's decision 1348 making when dealing with multi-core CPU chips at a cost of slightly 1349 increased overhead in some places. If unsure say N here. 1350 1351config SCHED_SMT 1352 bool "SMT scheduler support" 1353 depends on ARM_CPU_TOPOLOGY 1354 help 1355 Improves the CPU scheduler's decision making when dealing with 1356 MultiThreading at a cost of slightly increased overhead in some 1357 places. If unsure say N here. 1358 1359config HAVE_ARM_SCU 1360 bool 1361 help 1362 This option enables support for the ARM system coherency unit 1363 1364config HAVE_ARM_ARCH_TIMER 1365 bool "Architected timer support" 1366 depends on CPU_V7 1367 select ARM_ARCH_TIMER 1368 select GENERIC_CLOCKEVENTS 1369 help 1370 This option enables support for the ARM architected timer 1371 1372config HAVE_ARM_TWD 1373 bool 1374 select CLKSRC_OF if OF 1375 help 1376 This options enables support for the ARM timer and watchdog unit 1377 1378config MCPM 1379 bool "Multi-Cluster Power Management" 1380 depends on CPU_V7 && SMP 1381 help 1382 This option provides the common power management infrastructure 1383 for (multi-)cluster based systems, such as big.LITTLE based 1384 systems. 1385 1386config MCPM_QUAD_CLUSTER 1387 bool 1388 depends on MCPM 1389 help 1390 To avoid wasting resources unnecessarily, MCPM only supports up 1391 to 2 clusters by default. 1392 Platforms with 3 or 4 clusters that use MCPM must select this 1393 option to allow the additional clusters to be managed. 1394 1395config BIG_LITTLE 1396 bool "big.LITTLE support (Experimental)" 1397 depends on CPU_V7 && SMP 1398 select MCPM 1399 help 1400 This option enables support selections for the big.LITTLE 1401 system architecture. 1402 1403config BL_SWITCHER 1404 bool "big.LITTLE switcher support" 1405 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1406 select CPU_PM 1407 help 1408 The big.LITTLE "switcher" provides the core functionality to 1409 transparently handle transition between a cluster of A15's 1410 and a cluster of A7's in a big.LITTLE system. 1411 1412config BL_SWITCHER_DUMMY_IF 1413 tristate "Simple big.LITTLE switcher user interface" 1414 depends on BL_SWITCHER && DEBUG_KERNEL 1415 help 1416 This is a simple and dummy char dev interface to control 1417 the big.LITTLE switcher core code. It is meant for 1418 debugging purposes only. 1419 1420choice 1421 prompt "Memory split" 1422 depends on MMU 1423 default VMSPLIT_3G 1424 help 1425 Select the desired split between kernel and user memory. 1426 1427 If you are not absolutely sure what you are doing, leave this 1428 option alone! 1429 1430 config VMSPLIT_3G 1431 bool "3G/1G user/kernel split" 1432 config VMSPLIT_3G_OPT 1433 bool "3G/1G user/kernel split (for full 1G low memory)" 1434 config VMSPLIT_2G 1435 bool "2G/2G user/kernel split" 1436 config VMSPLIT_1G 1437 bool "1G/3G user/kernel split" 1438endchoice 1439 1440config PAGE_OFFSET 1441 hex 1442 default PHYS_OFFSET if !MMU 1443 default 0x40000000 if VMSPLIT_1G 1444 default 0x80000000 if VMSPLIT_2G 1445 default 0xB0000000 if VMSPLIT_3G_OPT 1446 default 0xC0000000 1447 1448config NR_CPUS 1449 int "Maximum number of CPUs (2-32)" 1450 range 2 32 1451 depends on SMP 1452 default "4" 1453 1454config HOTPLUG_CPU 1455 bool "Support for hot-pluggable CPUs" 1456 depends on SMP 1457 help 1458 Say Y here to experiment with turning CPUs off and on. CPUs 1459 can be controlled through /sys/devices/system/cpu. 1460 1461config ARM_PSCI 1462 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1463 depends on HAVE_ARM_SMCCC 1464 select ARM_PSCI_FW 1465 help 1466 Say Y here if you want Linux to communicate with system firmware 1467 implementing the PSCI specification for CPU-centric power 1468 management operations described in ARM document number ARM DEN 1469 0022A ("Power State Coordination Interface System Software on 1470 ARM processors"). 1471 1472# The GPIO number here must be sorted by descending number. In case of 1473# a multiplatform kernel, we just want the highest value required by the 1474# selected platforms. 1475config ARCH_NR_GPIO 1476 int 1477 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1478 ARCH_ZYNQ 1479 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1480 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1481 default 416 if ARCH_SUNXI 1482 default 392 if ARCH_U8500 1483 default 352 if ARCH_VT8500 1484 default 288 if ARCH_ROCKCHIP 1485 default 264 if MACH_H4700 1486 default 0 1487 help 1488 Maximum number of GPIOs in the system. 1489 1490 If unsure, leave the default value. 1491 1492source kernel/Kconfig.preempt 1493 1494config HZ_FIXED 1495 int 1496 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1497 ARCH_S5PV210 || ARCH_EXYNOS4 1498 default 128 if SOC_AT91RM9200 1499 default 0 1500 1501choice 1502 depends on HZ_FIXED = 0 1503 prompt "Timer frequency" 1504 1505config HZ_100 1506 bool "100 Hz" 1507 1508config HZ_200 1509 bool "200 Hz" 1510 1511config HZ_250 1512 bool "250 Hz" 1513 1514config HZ_300 1515 bool "300 Hz" 1516 1517config HZ_500 1518 bool "500 Hz" 1519 1520config HZ_1000 1521 bool "1000 Hz" 1522 1523endchoice 1524 1525config HZ 1526 int 1527 default HZ_FIXED if HZ_FIXED != 0 1528 default 100 if HZ_100 1529 default 200 if HZ_200 1530 default 250 if HZ_250 1531 default 300 if HZ_300 1532 default 500 if HZ_500 1533 default 1000 1534 1535config SCHED_HRTICK 1536 def_bool HIGH_RES_TIMERS 1537 1538config THUMB2_KERNEL 1539 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1540 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1541 default y if CPU_THUMBONLY 1542 select AEABI 1543 select ARM_ASM_UNIFIED 1544 select ARM_UNWIND 1545 help 1546 By enabling this option, the kernel will be compiled in 1547 Thumb-2 mode. A compiler/assembler that understand the unified 1548 ARM-Thumb syntax is needed. 1549 1550 If unsure, say N. 1551 1552config THUMB2_AVOID_R_ARM_THM_JUMP11 1553 bool "Work around buggy Thumb-2 short branch relocations in gas" 1554 depends on THUMB2_KERNEL && MODULES 1555 default y 1556 help 1557 Various binutils versions can resolve Thumb-2 branches to 1558 locally-defined, preemptible global symbols as short-range "b.n" 1559 branch instructions. 1560 1561 This is a problem, because there's no guarantee the final 1562 destination of the symbol, or any candidate locations for a 1563 trampoline, are within range of the branch. For this reason, the 1564 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1565 relocation in modules at all, and it makes little sense to add 1566 support. 1567 1568 The symptom is that the kernel fails with an "unsupported 1569 relocation" error when loading some modules. 1570 1571 Until fixed tools are available, passing 1572 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1573 code which hits this problem, at the cost of a bit of extra runtime 1574 stack usage in some cases. 1575 1576 The problem is described in more detail at: 1577 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1578 1579 Only Thumb-2 kernels are affected. 1580 1581 Unless you are sure your tools don't have this problem, say Y. 1582 1583config ARM_ASM_UNIFIED 1584 bool 1585 1586config ARM_PATCH_IDIV 1587 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1588 depends on CPU_32v7 && !XIP_KERNEL 1589 default y 1590 help 1591 The ARM compiler inserts calls to __aeabi_idiv() and 1592 __aeabi_uidiv() when it needs to perform division on signed 1593 and unsigned integers. Some v7 CPUs have support for the sdiv 1594 and udiv instructions that can be used to implement those 1595 functions. 1596 1597 Enabling this option allows the kernel to modify itself to 1598 replace the first two instructions of these library functions 1599 with the sdiv or udiv plus "bx lr" instructions when the CPU 1600 it is running on supports them. Typically this will be faster 1601 and less power intensive than running the original library 1602 code to do integer division. 1603 1604config AEABI 1605 bool "Use the ARM EABI to compile the kernel" 1606 help 1607 This option allows for the kernel to be compiled using the latest 1608 ARM ABI (aka EABI). This is only useful if you are using a user 1609 space environment that is also compiled with EABI. 1610 1611 Since there are major incompatibilities between the legacy ABI and 1612 EABI, especially with regard to structure member alignment, this 1613 option also changes the kernel syscall calling convention to 1614 disambiguate both ABIs and allow for backward compatibility support 1615 (selected with CONFIG_OABI_COMPAT). 1616 1617 To use this you need GCC version 4.0.0 or later. 1618 1619config OABI_COMPAT 1620 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1621 depends on AEABI && !THUMB2_KERNEL 1622 help 1623 This option preserves the old syscall interface along with the 1624 new (ARM EABI) one. It also provides a compatibility layer to 1625 intercept syscalls that have structure arguments which layout 1626 in memory differs between the legacy ABI and the new ARM EABI 1627 (only for non "thumb" binaries). This option adds a tiny 1628 overhead to all syscalls and produces a slightly larger kernel. 1629 1630 The seccomp filter system will not be available when this is 1631 selected, since there is no way yet to sensibly distinguish 1632 between calling conventions during filtering. 1633 1634 If you know you'll be using only pure EABI user space then you 1635 can say N here. If this option is not selected and you attempt 1636 to execute a legacy ABI binary then the result will be 1637 UNPREDICTABLE (in fact it can be predicted that it won't work 1638 at all). If in doubt say N. 1639 1640config ARCH_HAS_HOLES_MEMORYMODEL 1641 bool 1642 1643config ARCH_SPARSEMEM_ENABLE 1644 bool 1645 1646config ARCH_SPARSEMEM_DEFAULT 1647 def_bool ARCH_SPARSEMEM_ENABLE 1648 1649config ARCH_SELECT_MEMORY_MODEL 1650 def_bool ARCH_SPARSEMEM_ENABLE 1651 1652config HAVE_ARCH_PFN_VALID 1653 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1654 1655config HAVE_GENERIC_RCU_GUP 1656 def_bool y 1657 depends on ARM_LPAE 1658 1659config HIGHMEM 1660 bool "High Memory Support" 1661 depends on MMU 1662 help 1663 The address space of ARM processors is only 4 Gigabytes large 1664 and it has to accommodate user address space, kernel address 1665 space as well as some memory mapped IO. That means that, if you 1666 have a large amount of physical memory and/or IO, not all of the 1667 memory can be "permanently mapped" by the kernel. The physical 1668 memory that is not permanently mapped is called "high memory". 1669 1670 Depending on the selected kernel/user memory split, minimum 1671 vmalloc space and actual amount of RAM, you may not need this 1672 option which should result in a slightly faster kernel. 1673 1674 If unsure, say n. 1675 1676config HIGHPTE 1677 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1678 depends on HIGHMEM 1679 default y 1680 help 1681 The VM uses one page of physical memory for each page table. 1682 For systems with a lot of processes, this can use a lot of 1683 precious low memory, eventually leading to low memory being 1684 consumed by page tables. Setting this option will allow 1685 user-space 2nd level page tables to reside in high memory. 1686 1687config CPU_SW_DOMAIN_PAN 1688 bool "Enable use of CPU domains to implement privileged no-access" 1689 depends on MMU && !ARM_LPAE 1690 default y 1691 help 1692 Increase kernel security by ensuring that normal kernel accesses 1693 are unable to access userspace addresses. This can help prevent 1694 use-after-free bugs becoming an exploitable privilege escalation 1695 by ensuring that magic values (such as LIST_POISON) will always 1696 fault when dereferenced. 1697 1698 CPUs with low-vector mappings use a best-efforts implementation. 1699 Their lower 1MB needs to remain accessible for the vectors, but 1700 the remainder of userspace will become appropriately inaccessible. 1701 1702config HW_PERF_EVENTS 1703 def_bool y 1704 depends on ARM_PMU 1705 1706config SYS_SUPPORTS_HUGETLBFS 1707 def_bool y 1708 depends on ARM_LPAE 1709 1710config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1711 def_bool y 1712 depends on ARM_LPAE 1713 1714config ARCH_WANT_GENERAL_HUGETLB 1715 def_bool y 1716 1717config ARM_MODULE_PLTS 1718 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1719 depends on MODULES 1720 help 1721 Allocate PLTs when loading modules so that jumps and calls whose 1722 targets are too far away for their relative offsets to be encoded 1723 in the instructions themselves can be bounced via veneers in the 1724 module's PLT. This allows modules to be allocated in the generic 1725 vmalloc area after the dedicated module memory area has been 1726 exhausted. The modules will use slightly more memory, but after 1727 rounding up to page size, the actual memory footprint is usually 1728 the same. 1729 1730 Say y if you are getting out of memory errors while loading modules 1731 1732source "mm/Kconfig" 1733 1734config FORCE_MAX_ZONEORDER 1735 int "Maximum zone order" 1736 default "12" if SOC_AM33XX 1737 default "9" if SA1111 || ARCH_EFM32 1738 default "11" 1739 help 1740 The kernel memory allocator divides physically contiguous memory 1741 blocks into "zones", where each zone is a power of two number of 1742 pages. This option selects the largest power of two that the kernel 1743 keeps in the memory allocator. If you need to allocate very large 1744 blocks of physically contiguous memory, then you may need to 1745 increase this value. 1746 1747 This config option is actually maximum order plus one. For example, 1748 a value of 11 means that the largest free memory block is 2^10 pages. 1749 1750config ALIGNMENT_TRAP 1751 bool 1752 depends on CPU_CP15_MMU 1753 default y if !ARCH_EBSA110 1754 select HAVE_PROC_CPU if PROC_FS 1755 help 1756 ARM processors cannot fetch/store information which is not 1757 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1758 address divisible by 4. On 32-bit ARM processors, these non-aligned 1759 fetch/store instructions will be emulated in software if you say 1760 here, which has a severe performance impact. This is necessary for 1761 correct operation of some network protocols. With an IP-only 1762 configuration it is safe to say N, otherwise say Y. 1763 1764config UACCESS_WITH_MEMCPY 1765 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1766 depends on MMU 1767 default y if CPU_FEROCEON 1768 help 1769 Implement faster copy_to_user and clear_user methods for CPU 1770 cores where a 8-word STM instruction give significantly higher 1771 memory write throughput than a sequence of individual 32bit stores. 1772 1773 A possible side effect is a slight increase in scheduling latency 1774 between threads sharing the same address space if they invoke 1775 such copy operations with large buffers. 1776 1777 However, if the CPU data cache is using a write-allocate mode, 1778 this option is unlikely to provide any performance gain. 1779 1780config SECCOMP 1781 bool 1782 prompt "Enable seccomp to safely compute untrusted bytecode" 1783 ---help--- 1784 This kernel feature is useful for number crunching applications 1785 that may need to compute untrusted bytecode during their 1786 execution. By using pipes or other transports made available to 1787 the process as file descriptors supporting the read/write 1788 syscalls, it's possible to isolate those applications in 1789 their own address space using seccomp. Once seccomp is 1790 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1791 and the task is only allowed to execute a few safe syscalls 1792 defined by each seccomp mode. 1793 1794config SWIOTLB 1795 def_bool y 1796 1797config IOMMU_HELPER 1798 def_bool SWIOTLB 1799 1800config PARAVIRT 1801 bool "Enable paravirtualization code" 1802 help 1803 This changes the kernel so it can modify itself when it is run 1804 under a hypervisor, potentially improving performance significantly 1805 over full virtualization. 1806 1807config PARAVIRT_TIME_ACCOUNTING 1808 bool "Paravirtual steal time accounting" 1809 select PARAVIRT 1810 default n 1811 help 1812 Select this option to enable fine granularity task steal time 1813 accounting. Time spent executing other tasks in parallel with 1814 the current vCPU is discounted from the vCPU power. To account for 1815 that, there can be a small performance impact. 1816 1817 If in doubt, say N here. 1818 1819config XEN_DOM0 1820 def_bool y 1821 depends on XEN 1822 1823config XEN 1824 bool "Xen guest support on ARM" 1825 depends on ARM && AEABI && OF 1826 depends on CPU_V7 && !CPU_V6 1827 depends on !GENERIC_ATOMIC64 1828 depends on MMU 1829 select ARCH_DMA_ADDR_T_64BIT 1830 select ARM_PSCI 1831 select SWIOTLB_XEN 1832 select PARAVIRT 1833 help 1834 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1835 1836endmenu 1837 1838menu "Boot options" 1839 1840config USE_OF 1841 bool "Flattened Device Tree support" 1842 select IRQ_DOMAIN 1843 select OF 1844 help 1845 Include support for flattened device tree machine descriptions. 1846 1847config ATAGS 1848 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1849 default y 1850 help 1851 This is the traditional way of passing data to the kernel at boot 1852 time. If you are solely relying on the flattened device tree (or 1853 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1854 to remove ATAGS support from your kernel binary. If unsure, 1855 leave this to y. 1856 1857config DEPRECATED_PARAM_STRUCT 1858 bool "Provide old way to pass kernel parameters" 1859 depends on ATAGS 1860 help 1861 This was deprecated in 2001 and announced to live on for 5 years. 1862 Some old boot loaders still use this way. 1863 1864# Compressed boot loader in ROM. Yes, we really want to ask about 1865# TEXT and BSS so we preserve their values in the config files. 1866config ZBOOT_ROM_TEXT 1867 hex "Compressed ROM boot loader base address" 1868 default "0" 1869 help 1870 The physical address at which the ROM-able zImage is to be 1871 placed in the target. Platforms which normally make use of 1872 ROM-able zImage formats normally set this to a suitable 1873 value in their defconfig file. 1874 1875 If ZBOOT_ROM is not enabled, this has no effect. 1876 1877config ZBOOT_ROM_BSS 1878 hex "Compressed ROM boot loader BSS address" 1879 default "0" 1880 help 1881 The base address of an area of read/write memory in the target 1882 for the ROM-able zImage which must be available while the 1883 decompressor is running. It must be large enough to hold the 1884 entire decompressed kernel plus an additional 128 KiB. 1885 Platforms which normally make use of ROM-able zImage formats 1886 normally set this to a suitable value in their defconfig file. 1887 1888 If ZBOOT_ROM is not enabled, this has no effect. 1889 1890config ZBOOT_ROM 1891 bool "Compressed boot loader in ROM/flash" 1892 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1893 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1894 help 1895 Say Y here if you intend to execute your compressed kernel image 1896 (zImage) directly from ROM or flash. If unsure, say N. 1897 1898config ARM_APPENDED_DTB 1899 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1900 depends on OF 1901 help 1902 With this option, the boot code will look for a device tree binary 1903 (DTB) appended to zImage 1904 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1905 1906 This is meant as a backward compatibility convenience for those 1907 systems with a bootloader that can't be upgraded to accommodate 1908 the documented boot protocol using a device tree. 1909 1910 Beware that there is very little in terms of protection against 1911 this option being confused by leftover garbage in memory that might 1912 look like a DTB header after a reboot if no actual DTB is appended 1913 to zImage. Do not leave this option active in a production kernel 1914 if you don't intend to always append a DTB. Proper passing of the 1915 location into r2 of a bootloader provided DTB is always preferable 1916 to this option. 1917 1918config ARM_ATAG_DTB_COMPAT 1919 bool "Supplement the appended DTB with traditional ATAG information" 1920 depends on ARM_APPENDED_DTB 1921 help 1922 Some old bootloaders can't be updated to a DTB capable one, yet 1923 they provide ATAGs with memory configuration, the ramdisk address, 1924 the kernel cmdline string, etc. Such information is dynamically 1925 provided by the bootloader and can't always be stored in a static 1926 DTB. To allow a device tree enabled kernel to be used with such 1927 bootloaders, this option allows zImage to extract the information 1928 from the ATAG list and store it at run time into the appended DTB. 1929 1930choice 1931 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1932 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1933 1934config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1935 bool "Use bootloader kernel arguments if available" 1936 help 1937 Uses the command-line options passed by the boot loader instead of 1938 the device tree bootargs property. If the boot loader doesn't provide 1939 any, the device tree bootargs property will be used. 1940 1941config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1942 bool "Extend with bootloader kernel arguments" 1943 help 1944 The command-line arguments provided by the boot loader will be 1945 appended to the the device tree bootargs property. 1946 1947endchoice 1948 1949config CMDLINE 1950 string "Default kernel command string" 1951 default "" 1952 help 1953 On some architectures (EBSA110 and CATS), there is currently no way 1954 for the boot loader to pass arguments to the kernel. For these 1955 architectures, you should supply some command-line options at build 1956 time by entering them here. As a minimum, you should specify the 1957 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1958 1959choice 1960 prompt "Kernel command line type" if CMDLINE != "" 1961 default CMDLINE_FROM_BOOTLOADER 1962 depends on ATAGS 1963 1964config CMDLINE_FROM_BOOTLOADER 1965 bool "Use bootloader kernel arguments if available" 1966 help 1967 Uses the command-line options passed by the boot loader. If 1968 the boot loader doesn't provide any, the default kernel command 1969 string provided in CMDLINE will be used. 1970 1971config CMDLINE_EXTEND 1972 bool "Extend bootloader kernel arguments" 1973 help 1974 The command-line arguments provided by the boot loader will be 1975 appended to the default kernel command string. 1976 1977config CMDLINE_FORCE 1978 bool "Always use the default kernel command string" 1979 help 1980 Always use the default kernel command string, even if the boot 1981 loader passes other arguments to the kernel. 1982 This is useful if you cannot or don't want to change the 1983 command-line options your boot loader passes to the kernel. 1984endchoice 1985 1986config XIP_KERNEL 1987 bool "Kernel Execute-In-Place from ROM" 1988 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1989 help 1990 Execute-In-Place allows the kernel to run from non-volatile storage 1991 directly addressable by the CPU, such as NOR flash. This saves RAM 1992 space since the text section of the kernel is not loaded from flash 1993 to RAM. Read-write sections, such as the data section and stack, 1994 are still copied to RAM. The XIP kernel is not compressed since 1995 it has to run directly from flash, so it will take more space to 1996 store it. The flash address used to link the kernel object files, 1997 and for storing it, is configuration dependent. Therefore, if you 1998 say Y here, you must know the proper physical address where to 1999 store the kernel image depending on your own flash memory usage. 2000 2001 Also note that the make target becomes "make xipImage" rather than 2002 "make zImage" or "make Image". The final kernel binary to put in 2003 ROM memory will be arch/arm/boot/xipImage. 2004 2005 If unsure, say N. 2006 2007config XIP_PHYS_ADDR 2008 hex "XIP Kernel Physical Location" 2009 depends on XIP_KERNEL 2010 default "0x00080000" 2011 help 2012 This is the physical address in your flash memory the kernel will 2013 be linked for and stored to. This address is dependent on your 2014 own flash usage. 2015 2016config KEXEC 2017 bool "Kexec system call (EXPERIMENTAL)" 2018 depends on (!SMP || PM_SLEEP_SMP) 2019 depends on !CPU_V7M 2020 select KEXEC_CORE 2021 help 2022 kexec is a system call that implements the ability to shutdown your 2023 current kernel, and to start another kernel. It is like a reboot 2024 but it is independent of the system firmware. And like a reboot 2025 you can start any kernel with it, not just Linux. 2026 2027 It is an ongoing process to be certain the hardware in a machine 2028 is properly shutdown, so do not be surprised if this code does not 2029 initially work for you. 2030 2031config ATAGS_PROC 2032 bool "Export atags in procfs" 2033 depends on ATAGS && KEXEC 2034 default y 2035 help 2036 Should the atags used to boot the kernel be exported in an "atags" 2037 file in procfs. Useful with kexec. 2038 2039config CRASH_DUMP 2040 bool "Build kdump crash kernel (EXPERIMENTAL)" 2041 help 2042 Generate crash dump after being started by kexec. This should 2043 be normally only set in special crash dump kernels which are 2044 loaded in the main kernel with kexec-tools into a specially 2045 reserved region and then later executed after a crash by 2046 kdump/kexec. The crash dump kernel must be compiled to a 2047 memory address not used by the main kernel 2048 2049 For more details see Documentation/kdump/kdump.txt 2050 2051config AUTO_ZRELADDR 2052 bool "Auto calculation of the decompressed kernel image address" 2053 help 2054 ZRELADDR is the physical address where the decompressed kernel 2055 image will be placed. If AUTO_ZRELADDR is selected, the address 2056 will be determined at run-time by masking the current IP with 2057 0xf8000000. This assumes the zImage being placed in the first 128MB 2058 from start of memory. 2059 2060config EFI_STUB 2061 bool 2062 2063config EFI 2064 bool "UEFI runtime support" 2065 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2066 select UCS2_STRING 2067 select EFI_PARAMS_FROM_FDT 2068 select EFI_STUB 2069 select EFI_ARMSTUB 2070 select EFI_RUNTIME_WRAPPERS 2071 ---help--- 2072 This option provides support for runtime services provided 2073 by UEFI firmware (such as non-volatile variables, realtime 2074 clock, and platform reset). A UEFI stub is also provided to 2075 allow the kernel to be booted as an EFI application. This 2076 is only useful for kernels that may run on systems that have 2077 UEFI firmware. 2078 2079endmenu 2080 2081menu "CPU Power Management" 2082 2083source "drivers/cpufreq/Kconfig" 2084 2085source "drivers/cpuidle/Kconfig" 2086 2087endmenu 2088 2089menu "Floating point emulation" 2090 2091comment "At least one emulation must be selected" 2092 2093config FPE_NWFPE 2094 bool "NWFPE math emulation" 2095 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2096 ---help--- 2097 Say Y to include the NWFPE floating point emulator in the kernel. 2098 This is necessary to run most binaries. Linux does not currently 2099 support floating point hardware so you need to say Y here even if 2100 your machine has an FPA or floating point co-processor podule. 2101 2102 You may say N here if you are going to load the Acorn FPEmulator 2103 early in the bootup. 2104 2105config FPE_NWFPE_XP 2106 bool "Support extended precision" 2107 depends on FPE_NWFPE 2108 help 2109 Say Y to include 80-bit support in the kernel floating-point 2110 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2111 Note that gcc does not generate 80-bit operations by default, 2112 so in most cases this option only enlarges the size of the 2113 floating point emulator without any good reason. 2114 2115 You almost surely want to say N here. 2116 2117config FPE_FASTFPE 2118 bool "FastFPE math emulation (EXPERIMENTAL)" 2119 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2120 ---help--- 2121 Say Y here to include the FAST floating point emulator in the kernel. 2122 This is an experimental much faster emulator which now also has full 2123 precision for the mantissa. It does not support any exceptions. 2124 It is very simple, and approximately 3-6 times faster than NWFPE. 2125 2126 It should be sufficient for most programs. It may be not suitable 2127 for scientific calculations, but you have to check this for yourself. 2128 If you do not feel you need a faster FP emulation you should better 2129 choose NWFPE. 2130 2131config VFP 2132 bool "VFP-format floating point maths" 2133 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2134 help 2135 Say Y to include VFP support code in the kernel. This is needed 2136 if your hardware includes a VFP unit. 2137 2138 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2139 release notes and additional status information. 2140 2141 Say N if your target does not have VFP hardware. 2142 2143config VFPv3 2144 bool 2145 depends on VFP 2146 default y if CPU_V7 2147 2148config NEON 2149 bool "Advanced SIMD (NEON) Extension support" 2150 depends on VFPv3 && CPU_V7 2151 help 2152 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2153 Extension. 2154 2155config KERNEL_MODE_NEON 2156 bool "Support for NEON in kernel mode" 2157 depends on NEON && AEABI 2158 help 2159 Say Y to include support for NEON in kernel mode. 2160 2161endmenu 2162 2163menu "Userspace binary formats" 2164 2165source "fs/Kconfig.binfmt" 2166 2167endmenu 2168 2169menu "Power management options" 2170 2171source "kernel/power/Kconfig" 2172 2173config ARCH_SUSPEND_POSSIBLE 2174 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2175 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2176 def_bool y 2177 2178config ARM_CPU_SUSPEND 2179 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2180 depends on ARCH_SUSPEND_POSSIBLE 2181 2182config ARCH_HIBERNATION_POSSIBLE 2183 bool 2184 depends on MMU 2185 default y if ARCH_SUSPEND_POSSIBLE 2186 2187endmenu 2188 2189source "net/Kconfig" 2190 2191source "drivers/Kconfig" 2192 2193source "drivers/firmware/Kconfig" 2194 2195source "fs/Kconfig" 2196 2197source "arch/arm/Kconfig.debug" 2198 2199source "security/Kconfig" 2200 2201source "crypto/Kconfig" 2202if CRYPTO 2203source "arch/arm/crypto/Kconfig" 2204endif 2205 2206source "lib/Kconfig" 2207 2208source "arch/arm/kvm/Kconfig" 2209