1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 15 select ARCH_HAS_PHYS_TO_DMA 16 select ARCH_HAS_SETUP_DMA_OPS 17 select ARCH_HAS_SET_MEMORY 18 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 19 select ARCH_HAS_STRICT_MODULE_RWX if MMU 20 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 22 select ARCH_HAVE_CUSTOM_GPIO_H 23 select ARCH_HAS_GCOV_PROFILE_ALL 24 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 25 select ARCH_MIGHT_HAVE_PC_PARPORT 26 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 27 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 28 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 29 select ARCH_SUPPORTS_ATOMIC_RMW 30 select ARCH_USE_BUILTIN_BSWAP 31 select ARCH_USE_CMPXCHG_LOCKREF 32 select ARCH_WANT_IPC_PARSE_VERSION 33 select BUILDTIME_EXTABLE_SORT if MMU 34 select CLONE_BACKWARDS 35 select CPU_PM if SUSPEND || CPU_IDLE 36 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 37 select DMA_DECLARE_COHERENT 38 select DMA_REMAP if MMU 39 select EDAC_SUPPORT 40 select EDAC_ATOMIC_SCRUB 41 select GENERIC_ALLOCATOR 42 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 43 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 44 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 45 select GENERIC_CPU_AUTOPROBE 46 select GENERIC_EARLY_IOREMAP 47 select GENERIC_IDLE_POLL_SETUP 48 select GENERIC_IRQ_PROBE 49 select GENERIC_IRQ_SHOW 50 select GENERIC_IRQ_SHOW_LEVEL 51 select GENERIC_PCI_IOMAP 52 select GENERIC_SCHED_CLOCK 53 select GENERIC_SMP_IDLE_THREAD 54 select GENERIC_STRNCPY_FROM_USER 55 select GENERIC_STRNLEN_USER 56 select HANDLE_DOMAIN_IRQ 57 select HARDIRQS_SW_RESEND 58 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 59 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 60 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 61 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 62 select HAVE_ARCH_MMAP_RND_BITS if MMU 63 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 64 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 65 select HAVE_ARCH_TRACEHOOK 66 select HAVE_ARM_SMCCC if CPU_V7 67 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 68 select HAVE_CONTEXT_TRACKING 69 select HAVE_C_RECORDMCOUNT 70 select HAVE_DEBUG_KMEMLEAK 71 select HAVE_DMA_CONTIGUOUS if MMU 72 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 74 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 75 select HAVE_EXIT_THREAD 76 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 77 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 78 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 79 select HAVE_GCC_PLUGINS 80 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 81 select HAVE_IDE if PCI || ISA || PCMCIA 82 select HAVE_IRQ_TIME_ACCOUNTING 83 select HAVE_KERNEL_GZIP 84 select HAVE_KERNEL_LZ4 85 select HAVE_KERNEL_LZMA 86 select HAVE_KERNEL_LZO 87 select HAVE_KERNEL_XZ 88 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 89 select HAVE_KRETPROBES if HAVE_KPROBES 90 select HAVE_MOD_ARCH_SPECIFIC 91 select HAVE_NMI 92 select HAVE_OPROFILE if HAVE_PERF_EVENTS 93 select HAVE_OPTPROBES if !THUMB2_KERNEL 94 select HAVE_PERF_EVENTS 95 select HAVE_PERF_REGS 96 select HAVE_PERF_USER_STACK_DUMP 97 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 98 select HAVE_REGS_AND_STACK_ACCESS_API 99 select HAVE_RSEQ 100 select HAVE_STACKPROTECTOR 101 select HAVE_SYSCALL_TRACEPOINTS 102 select HAVE_UID16 103 select HAVE_VIRT_CPU_ACCOUNTING_GEN 104 select IRQ_FORCED_THREADING 105 select MODULES_USE_ELF_REL 106 select NEED_DMA_MAP_STATE 107 select OF_EARLY_FLATTREE if OF 108 select OLD_SIGACTION 109 select OLD_SIGSUSPEND3 110 select PCI_SYSCALL if PCI 111 select PERF_USE_VMALLOC 112 select REFCOUNT_FULL 113 select RTC_LIB 114 select SYS_SUPPORTS_APM_EMULATION 115 # Above selects are sorted alphabetically; please add new ones 116 # according to that. Thanks. 117 help 118 The ARM series is a line of low-power-consumption RISC chip designs 119 licensed by ARM Ltd and targeted at embedded applications and 120 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 121 manufactured, but legacy ARM-based PC hardware remains popular in 122 Europe. There is an ARM Linux project with a web page at 123 <http://www.arm.linux.org.uk/>. 124 125config ARM_HAS_SG_CHAIN 126 bool 127 128config ARM_DMA_USE_IOMMU 129 bool 130 select ARM_HAS_SG_CHAIN 131 select NEED_SG_DMA_LENGTH 132 133if ARM_DMA_USE_IOMMU 134 135config ARM_DMA_IOMMU_ALIGNMENT 136 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 137 range 4 9 138 default 8 139 help 140 DMA mapping framework by default aligns all buffers to the smallest 141 PAGE_SIZE order which is greater than or equal to the requested buffer 142 size. This works well for buffers up to a few hundreds kilobytes, but 143 for larger buffers it just a waste of address space. Drivers which has 144 relatively small addressing window (like 64Mib) might run out of 145 virtual space with just a few allocations. 146 147 With this parameter you can specify the maximum PAGE_SIZE order for 148 DMA IOMMU buffers. Larger buffers will be aligned only to this 149 specified order. The order is expressed as a power of two multiplied 150 by the PAGE_SIZE. 151 152endif 153 154config SYS_SUPPORTS_APM_EMULATION 155 bool 156 157config HAVE_TCM 158 bool 159 select GENERIC_ALLOCATOR 160 161config HAVE_PROC_CPU 162 bool 163 164config NO_IOPORT_MAP 165 bool 166 167config SBUS 168 bool 169 170config STACKTRACE_SUPPORT 171 bool 172 default y 173 174config LOCKDEP_SUPPORT 175 bool 176 default y 177 178config TRACE_IRQFLAGS_SUPPORT 179 bool 180 default !CPU_V7M 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config ARCH_SUPPORTS_UPROBES 209 def_bool y 210 211config ARCH_HAS_DMA_SET_COHERENT_MASK 212 bool 213 214config GENERIC_ISA_DMA 215 bool 216 217config FIQ 218 bool 219 220config NEED_RET_TO_USER 221 bool 222 223config ARCH_MTD_XIP 224 bool 225 226config ARM_PATCH_PHYS_VIRT 227 bool "Patch physical to virtual translations at runtime" if EMBEDDED 228 default y 229 depends on !XIP_KERNEL && MMU 230 help 231 Patch phys-to-virt and virt-to-phys translation functions at 232 boot and module load time according to the position of the 233 kernel in system memory. 234 235 This can only be used with non-XIP MMU kernels where the base 236 of physical memory is at a 16MB boundary. 237 238 Only disable this option if you know that you do not require 239 this feature (eg, building a kernel for a single machine) and 240 you need to shrink the kernel to the minimal size. 241 242config NEED_MACH_IO_H 243 bool 244 help 245 Select this when mach/io.h is required to provide special 246 definitions for this platform. The need for mach/io.h should 247 be avoided when possible. 248 249config NEED_MACH_MEMORY_H 250 bool 251 help 252 Select this when mach/memory.h is required to provide special 253 definitions for this platform. The need for mach/memory.h should 254 be avoided when possible. 255 256config PHYS_OFFSET 257 hex "Physical address of main memory" if MMU 258 depends on !ARM_PATCH_PHYS_VIRT 259 default DRAM_BASE if !MMU 260 default 0x00000000 if ARCH_EBSA110 || \ 261 ARCH_FOOTBRIDGE || \ 262 ARCH_INTEGRATOR || \ 263 ARCH_IOP13XX || \ 264 ARCH_KS8695 || \ 265 ARCH_REALVIEW 266 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 267 default 0x20000000 if ARCH_S5PV210 268 default 0xc0000000 if ARCH_SA1100 269 help 270 Please provide the physical address corresponding to the 271 location of main memory in your system. 272 273config GENERIC_BUG 274 def_bool y 275 depends on BUG 276 277config PGTABLE_LEVELS 278 int 279 default 3 if ARM_LPAE 280 default 2 281 282menu "System Type" 283 284config MMU 285 bool "MMU-based Paged Memory Management Support" 286 default y 287 help 288 Select if you want MMU-based virtualised addressing space 289 support by paged memory management. If unsure, say 'Y'. 290 291config ARCH_MMAP_RND_BITS_MIN 292 default 8 293 294config ARCH_MMAP_RND_BITS_MAX 295 default 14 if PAGE_OFFSET=0x40000000 296 default 15 if PAGE_OFFSET=0x80000000 297 default 16 298 299# 300# The "ARM system type" choice list is ordered alphabetically by option 301# text. Please add new entries in the option alphabetic order. 302# 303choice 304 prompt "ARM system type" 305 default ARM_SINGLE_ARMV7M if !MMU 306 default ARCH_MULTIPLATFORM if MMU 307 308config ARCH_MULTIPLATFORM 309 bool "Allow multiple platforms to be selected" 310 depends on MMU 311 select ARM_HAS_SG_CHAIN 312 select ARM_PATCH_PHYS_VIRT 313 select AUTO_ZRELADDR 314 select TIMER_OF 315 select COMMON_CLK 316 select GENERIC_CLOCKEVENTS 317 select GENERIC_IRQ_MULTI_HANDLER 318 select HAVE_PCI 319 select PCI_DOMAINS_GENERIC if PCI 320 select SPARSE_IRQ 321 select USE_OF 322 323config ARM_SINGLE_ARMV7M 324 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 325 depends on !MMU 326 select ARM_NVIC 327 select AUTO_ZRELADDR 328 select TIMER_OF 329 select COMMON_CLK 330 select CPU_V7M 331 select GENERIC_CLOCKEVENTS 332 select NO_IOPORT_MAP 333 select SPARSE_IRQ 334 select USE_OF 335 336config ARCH_EBSA110 337 bool "EBSA-110" 338 select ARCH_USES_GETTIMEOFFSET 339 select CPU_SA110 340 select ISA 341 select NEED_MACH_IO_H 342 select NEED_MACH_MEMORY_H 343 select NO_IOPORT_MAP 344 help 345 This is an evaluation board for the StrongARM processor available 346 from Digital. It has limited hardware on-board, including an 347 Ethernet interface, two PCMCIA sockets, two serial ports and a 348 parallel port. 349 350config ARCH_EP93XX 351 bool "EP93xx-based" 352 select ARCH_SPARSEMEM_ENABLE 353 select ARM_AMBA 354 imply ARM_PATCH_PHYS_VIRT 355 select ARM_VIC 356 select AUTO_ZRELADDR 357 select CLKDEV_LOOKUP 358 select CLKSRC_MMIO 359 select CPU_ARM920T 360 select GENERIC_CLOCKEVENTS 361 select GPIOLIB 362 help 363 This enables support for the Cirrus EP93xx series of CPUs. 364 365config ARCH_FOOTBRIDGE 366 bool "FootBridge" 367 select CPU_SA110 368 select FOOTBRIDGE 369 select GENERIC_CLOCKEVENTS 370 select HAVE_IDE 371 select NEED_MACH_IO_H if !MMU 372 select NEED_MACH_MEMORY_H 373 help 374 Support for systems based on the DC21285 companion chip 375 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 376 377config ARCH_NETX 378 bool "Hilscher NetX based" 379 select ARM_VIC 380 select CLKSRC_MMIO 381 select CPU_ARM926T 382 select GENERIC_CLOCKEVENTS 383 help 384 This enables support for systems based on the Hilscher NetX Soc 385 386config ARCH_IOP13XX 387 bool "IOP13xx-based" 388 depends on MMU 389 select CPU_XSC3 390 select NEED_MACH_MEMORY_H 391 select NEED_RET_TO_USER 392 select FORCE_PCI 393 select PLAT_IOP 394 select VMSPLIT_1G 395 select SPARSE_IRQ 396 help 397 Support for Intel's IOP13XX (XScale) family of processors. 398 399config ARCH_IOP32X 400 bool "IOP32x-based" 401 depends on MMU 402 select CPU_XSCALE 403 select GPIO_IOP 404 select GPIOLIB 405 select NEED_RET_TO_USER 406 select FORCE_PCI 407 select PLAT_IOP 408 help 409 Support for Intel's 80219 and IOP32X (XScale) family of 410 processors. 411 412config ARCH_IOP33X 413 bool "IOP33x-based" 414 depends on MMU 415 select CPU_XSCALE 416 select GPIO_IOP 417 select GPIOLIB 418 select NEED_RET_TO_USER 419 select FORCE_PCI 420 select PLAT_IOP 421 help 422 Support for Intel's IOP33X (XScale) family of processors. 423 424config ARCH_IXP4XX 425 bool "IXP4xx-based" 426 depends on MMU 427 select ARCH_HAS_DMA_SET_COHERENT_MASK 428 select ARCH_SUPPORTS_BIG_ENDIAN 429 select CLKSRC_MMIO 430 select CPU_XSCALE 431 select DMABOUNCE if PCI 432 select GENERIC_CLOCKEVENTS 433 select GPIOLIB 434 select HAVE_PCI 435 select NEED_MACH_IO_H 436 select USB_EHCI_BIG_ENDIAN_DESC 437 select USB_EHCI_BIG_ENDIAN_MMIO 438 help 439 Support for Intel's IXP4XX (XScale) family of processors. 440 441config ARCH_DOVE 442 bool "Marvell Dove" 443 select CPU_PJ4 444 select GENERIC_CLOCKEVENTS 445 select GENERIC_IRQ_MULTI_HANDLER 446 select GPIOLIB 447 select HAVE_PCI 448 select MVEBU_MBUS 449 select PINCTRL 450 select PINCTRL_DOVE 451 select PLAT_ORION_LEGACY 452 select SPARSE_IRQ 453 select PM_GENERIC_DOMAINS if PM 454 help 455 Support for the Marvell Dove SoC 88AP510 456 457config ARCH_KS8695 458 bool "Micrel/Kendin KS8695" 459 select CLKSRC_MMIO 460 select CPU_ARM922T 461 select GENERIC_CLOCKEVENTS 462 select GPIOLIB 463 select NEED_MACH_MEMORY_H 464 help 465 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 466 System-on-Chip devices. 467 468config ARCH_W90X900 469 bool "Nuvoton W90X900 CPU" 470 select CLKDEV_LOOKUP 471 select CLKSRC_MMIO 472 select CPU_ARM926T 473 select GENERIC_CLOCKEVENTS 474 select GPIOLIB 475 help 476 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 477 At present, the w90x900 has been renamed nuc900, regarding 478 the ARM series product line, you can login the following 479 link address to know more. 480 481 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 482 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 483 484config ARCH_LPC32XX 485 bool "NXP LPC32XX" 486 select ARM_AMBA 487 select CLKDEV_LOOKUP 488 select CLKSRC_LPC32XX 489 select COMMON_CLK 490 select CPU_ARM926T 491 select GENERIC_CLOCKEVENTS 492 select GENERIC_IRQ_MULTI_HANDLER 493 select GPIOLIB 494 select SPARSE_IRQ 495 select USE_OF 496 help 497 Support for the NXP LPC32XX family of processors 498 499config ARCH_PXA 500 bool "PXA2xx/PXA3xx-based" 501 depends on MMU 502 select ARCH_MTD_XIP 503 select ARM_CPU_SUSPEND if PM 504 select AUTO_ZRELADDR 505 select COMMON_CLK 506 select CLKDEV_LOOKUP 507 select CLKSRC_PXA 508 select CLKSRC_MMIO 509 select TIMER_OF 510 select CPU_XSCALE if !CPU_XSC3 511 select GENERIC_CLOCKEVENTS 512 select GENERIC_IRQ_MULTI_HANDLER 513 select GPIO_PXA 514 select GPIOLIB 515 select HAVE_IDE 516 select IRQ_DOMAIN 517 select PLAT_PXA 518 select SPARSE_IRQ 519 help 520 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 521 522config ARCH_RPC 523 bool "RiscPC" 524 depends on MMU 525 select ARCH_ACORN 526 select ARCH_MAY_HAVE_PC_FDC 527 select ARCH_SPARSEMEM_ENABLE 528 select ARCH_USES_GETTIMEOFFSET 529 select CPU_SA110 530 select FIQ 531 select HAVE_IDE 532 select HAVE_PATA_PLATFORM 533 select ISA_DMA_API 534 select NEED_MACH_IO_H 535 select NEED_MACH_MEMORY_H 536 select NO_IOPORT_MAP 537 help 538 On the Acorn Risc-PC, Linux can support the internal IDE disk and 539 CD-ROM interface, serial and parallel port, and the floppy drive. 540 541config ARCH_SA1100 542 bool "SA1100-based" 543 select ARCH_MTD_XIP 544 select ARCH_SPARSEMEM_ENABLE 545 select CLKDEV_LOOKUP 546 select CLKSRC_MMIO 547 select CLKSRC_PXA 548 select TIMER_OF if OF 549 select CPU_FREQ 550 select CPU_SA1100 551 select GENERIC_CLOCKEVENTS 552 select GENERIC_IRQ_MULTI_HANDLER 553 select GPIOLIB 554 select HAVE_IDE 555 select IRQ_DOMAIN 556 select ISA 557 select NEED_MACH_MEMORY_H 558 select SPARSE_IRQ 559 help 560 Support for StrongARM 11x0 based boards. 561 562config ARCH_S3C24XX 563 bool "Samsung S3C24XX SoCs" 564 select ATAGS 565 select CLKDEV_LOOKUP 566 select CLKSRC_SAMSUNG_PWM 567 select GENERIC_CLOCKEVENTS 568 select GPIO_SAMSUNG 569 select GPIOLIB 570 select GENERIC_IRQ_MULTI_HANDLER 571 select HAVE_S3C2410_I2C if I2C 572 select HAVE_S3C2410_WATCHDOG if WATCHDOG 573 select HAVE_S3C_RTC if RTC_CLASS 574 select NEED_MACH_IO_H 575 select SAMSUNG_ATAGS 576 select USE_OF 577 help 578 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 579 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 580 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 581 Samsung SMDK2410 development board (and derivatives). 582 583config ARCH_DAVINCI 584 bool "TI DaVinci" 585 select ARCH_HAS_HOLES_MEMORYMODEL 586 select COMMON_CLK 587 select CPU_ARM926T 588 select GENERIC_ALLOCATOR 589 select GENERIC_CLOCKEVENTS 590 select GENERIC_IRQ_CHIP 591 select GENERIC_IRQ_MULTI_HANDLER 592 select GPIOLIB 593 select HAVE_IDE 594 select PM_GENERIC_DOMAINS if PM 595 select PM_GENERIC_DOMAINS_OF if PM && OF 596 select REGMAP_MMIO 597 select RESET_CONTROLLER 598 select SPARSE_IRQ 599 select USE_OF 600 select ZONE_DMA 601 help 602 Support for TI's DaVinci platform. 603 604config ARCH_OMAP1 605 bool "TI OMAP1" 606 depends on MMU 607 select ARCH_HAS_HOLES_MEMORYMODEL 608 select ARCH_OMAP 609 select CLKDEV_LOOKUP 610 select CLKSRC_MMIO 611 select GENERIC_CLOCKEVENTS 612 select GENERIC_IRQ_CHIP 613 select GENERIC_IRQ_MULTI_HANDLER 614 select GPIOLIB 615 select HAVE_IDE 616 select IRQ_DOMAIN 617 select NEED_MACH_IO_H if PCCARD 618 select NEED_MACH_MEMORY_H 619 select SPARSE_IRQ 620 help 621 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 622 623endchoice 624 625menu "Multiple platform selection" 626 depends on ARCH_MULTIPLATFORM 627 628comment "CPU Core family selection" 629 630config ARCH_MULTI_V4 631 bool "ARMv4 based platforms (FA526)" 632 depends on !ARCH_MULTI_V6_V7 633 select ARCH_MULTI_V4_V5 634 select CPU_FA526 635 636config ARCH_MULTI_V4T 637 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 638 depends on !ARCH_MULTI_V6_V7 639 select ARCH_MULTI_V4_V5 640 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 641 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 642 CPU_ARM925T || CPU_ARM940T) 643 644config ARCH_MULTI_V5 645 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 646 depends on !ARCH_MULTI_V6_V7 647 select ARCH_MULTI_V4_V5 648 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 649 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 650 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 651 652config ARCH_MULTI_V4_V5 653 bool 654 655config ARCH_MULTI_V6 656 bool "ARMv6 based platforms (ARM11)" 657 select ARCH_MULTI_V6_V7 658 select CPU_V6K 659 660config ARCH_MULTI_V7 661 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 662 default y 663 select ARCH_MULTI_V6_V7 664 select CPU_V7 665 select HAVE_SMP 666 667config ARCH_MULTI_V6_V7 668 bool 669 select MIGHT_HAVE_CACHE_L2X0 670 671config ARCH_MULTI_CPU_AUTO 672 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 673 select ARCH_MULTI_V5 674 675endmenu 676 677config ARCH_VIRT 678 bool "Dummy Virtual Machine" 679 depends on ARCH_MULTI_V7 680 select ARM_AMBA 681 select ARM_GIC 682 select ARM_GIC_V2M if PCI 683 select ARM_GIC_V3 684 select ARM_GIC_V3_ITS if PCI 685 select ARM_PSCI 686 select HAVE_ARM_ARCH_TIMER 687 select ARCH_SUPPORTS_BIG_ENDIAN 688 689# 690# This is sorted alphabetically by mach-* pathname. However, plat-* 691# Kconfigs may be included either alphabetically (according to the 692# plat- suffix) or along side the corresponding mach-* source. 693# 694source "arch/arm/mach-actions/Kconfig" 695 696source "arch/arm/mach-alpine/Kconfig" 697 698source "arch/arm/mach-artpec/Kconfig" 699 700source "arch/arm/mach-asm9260/Kconfig" 701 702source "arch/arm/mach-aspeed/Kconfig" 703 704source "arch/arm/mach-at91/Kconfig" 705 706source "arch/arm/mach-axxia/Kconfig" 707 708source "arch/arm/mach-bcm/Kconfig" 709 710source "arch/arm/mach-berlin/Kconfig" 711 712source "arch/arm/mach-clps711x/Kconfig" 713 714source "arch/arm/mach-cns3xxx/Kconfig" 715 716source "arch/arm/mach-davinci/Kconfig" 717 718source "arch/arm/mach-digicolor/Kconfig" 719 720source "arch/arm/mach-dove/Kconfig" 721 722source "arch/arm/mach-ep93xx/Kconfig" 723 724source "arch/arm/mach-exynos/Kconfig" 725source "arch/arm/plat-samsung/Kconfig" 726 727source "arch/arm/mach-footbridge/Kconfig" 728 729source "arch/arm/mach-gemini/Kconfig" 730 731source "arch/arm/mach-highbank/Kconfig" 732 733source "arch/arm/mach-hisi/Kconfig" 734 735source "arch/arm/mach-imx/Kconfig" 736 737source "arch/arm/mach-integrator/Kconfig" 738 739source "arch/arm/mach-iop13xx/Kconfig" 740 741source "arch/arm/mach-iop32x/Kconfig" 742 743source "arch/arm/mach-iop33x/Kconfig" 744 745source "arch/arm/mach-ixp4xx/Kconfig" 746 747source "arch/arm/mach-keystone/Kconfig" 748 749source "arch/arm/mach-ks8695/Kconfig" 750 751source "arch/arm/mach-mediatek/Kconfig" 752 753source "arch/arm/mach-meson/Kconfig" 754 755source "arch/arm/mach-milbeaut/Kconfig" 756 757source "arch/arm/mach-mmp/Kconfig" 758 759source "arch/arm/mach-moxart/Kconfig" 760 761source "arch/arm/mach-mv78xx0/Kconfig" 762 763source "arch/arm/mach-mvebu/Kconfig" 764 765source "arch/arm/mach-mxs/Kconfig" 766 767source "arch/arm/mach-netx/Kconfig" 768 769source "arch/arm/mach-nomadik/Kconfig" 770 771source "arch/arm/mach-npcm/Kconfig" 772 773source "arch/arm/mach-nspire/Kconfig" 774 775source "arch/arm/plat-omap/Kconfig" 776 777source "arch/arm/mach-omap1/Kconfig" 778 779source "arch/arm/mach-omap2/Kconfig" 780 781source "arch/arm/mach-orion5x/Kconfig" 782 783source "arch/arm/mach-oxnas/Kconfig" 784 785source "arch/arm/mach-picoxcell/Kconfig" 786 787source "arch/arm/mach-prima2/Kconfig" 788 789source "arch/arm/mach-pxa/Kconfig" 790source "arch/arm/plat-pxa/Kconfig" 791 792source "arch/arm/mach-qcom/Kconfig" 793 794source "arch/arm/mach-rda/Kconfig" 795 796source "arch/arm/mach-realview/Kconfig" 797 798source "arch/arm/mach-rockchip/Kconfig" 799 800source "arch/arm/mach-s3c24xx/Kconfig" 801 802source "arch/arm/mach-s3c64xx/Kconfig" 803 804source "arch/arm/mach-s5pv210/Kconfig" 805 806source "arch/arm/mach-sa1100/Kconfig" 807 808source "arch/arm/mach-shmobile/Kconfig" 809 810source "arch/arm/mach-socfpga/Kconfig" 811 812source "arch/arm/mach-spear/Kconfig" 813 814source "arch/arm/mach-sti/Kconfig" 815 816source "arch/arm/mach-stm32/Kconfig" 817 818source "arch/arm/mach-sunxi/Kconfig" 819 820source "arch/arm/mach-tango/Kconfig" 821 822source "arch/arm/mach-tegra/Kconfig" 823 824source "arch/arm/mach-u300/Kconfig" 825 826source "arch/arm/mach-uniphier/Kconfig" 827 828source "arch/arm/mach-ux500/Kconfig" 829 830source "arch/arm/mach-versatile/Kconfig" 831 832source "arch/arm/mach-vexpress/Kconfig" 833source "arch/arm/plat-versatile/Kconfig" 834 835source "arch/arm/mach-vt8500/Kconfig" 836 837source "arch/arm/mach-w90x900/Kconfig" 838 839source "arch/arm/mach-zx/Kconfig" 840 841source "arch/arm/mach-zynq/Kconfig" 842 843# ARMv7-M architecture 844config ARCH_EFM32 845 bool "Energy Micro efm32" 846 depends on ARM_SINGLE_ARMV7M 847 select GPIOLIB 848 help 849 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 850 processors. 851 852config ARCH_LPC18XX 853 bool "NXP LPC18xx/LPC43xx" 854 depends on ARM_SINGLE_ARMV7M 855 select ARCH_HAS_RESET_CONTROLLER 856 select ARM_AMBA 857 select CLKSRC_LPC32XX 858 select PINCTRL 859 help 860 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 861 high performance microcontrollers. 862 863config ARCH_MPS2 864 bool "ARM MPS2 platform" 865 depends on ARM_SINGLE_ARMV7M 866 select ARM_AMBA 867 select CLKSRC_MPS2 868 help 869 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 870 with a range of available cores like Cortex-M3/M4/M7. 871 872 Please, note that depends which Application Note is used memory map 873 for the platform may vary, so adjustment of RAM base might be needed. 874 875# Definitions to make life easier 876config ARCH_ACORN 877 bool 878 879config PLAT_IOP 880 bool 881 select GENERIC_CLOCKEVENTS 882 883config PLAT_ORION 884 bool 885 select CLKSRC_MMIO 886 select COMMON_CLK 887 select GENERIC_IRQ_CHIP 888 select IRQ_DOMAIN 889 890config PLAT_ORION_LEGACY 891 bool 892 select PLAT_ORION 893 894config PLAT_PXA 895 bool 896 897config PLAT_VERSATILE 898 bool 899 900source "arch/arm/firmware/Kconfig" 901 902source "arch/arm/mm/Kconfig" 903 904config IWMMXT 905 bool "Enable iWMMXt support" 906 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 907 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 908 help 909 Enable support for iWMMXt context switching at run time if 910 running on a CPU that supports it. 911 912if !MMU 913source "arch/arm/Kconfig-nommu" 914endif 915 916config PJ4B_ERRATA_4742 917 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 918 depends on CPU_PJ4B && MACH_ARMADA_370 919 default y 920 help 921 When coming out of either a Wait for Interrupt (WFI) or a Wait for 922 Event (WFE) IDLE states, a specific timing sensitivity exists between 923 the retiring WFI/WFE instructions and the newly issued subsequent 924 instructions. This sensitivity can result in a CPU hang scenario. 925 Workaround: 926 The software must insert either a Data Synchronization Barrier (DSB) 927 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 928 instruction 929 930config ARM_ERRATA_326103 931 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 932 depends on CPU_V6 933 help 934 Executing a SWP instruction to read-only memory does not set bit 11 935 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 936 treat the access as a read, preventing a COW from occurring and 937 causing the faulting task to livelock. 938 939config ARM_ERRATA_411920 940 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 941 depends on CPU_V6 || CPU_V6K 942 help 943 Invalidation of the Instruction Cache operation can 944 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 945 It does not affect the MPCore. This option enables the ARM Ltd. 946 recommended workaround. 947 948config ARM_ERRATA_430973 949 bool "ARM errata: Stale prediction on replaced interworking branch" 950 depends on CPU_V7 951 help 952 This option enables the workaround for the 430973 Cortex-A8 953 r1p* erratum. If a code sequence containing an ARM/Thumb 954 interworking branch is replaced with another code sequence at the 955 same virtual address, whether due to self-modifying code or virtual 956 to physical address re-mapping, Cortex-A8 does not recover from the 957 stale interworking branch prediction. This results in Cortex-A8 958 executing the new code sequence in the incorrect ARM or Thumb state. 959 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 960 and also flushes the branch target cache at every context switch. 961 Note that setting specific bits in the ACTLR register may not be 962 available in non-secure mode. 963 964config ARM_ERRATA_458693 965 bool "ARM errata: Processor deadlock when a false hazard is created" 966 depends on CPU_V7 967 depends on !ARCH_MULTIPLATFORM 968 help 969 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 970 erratum. For very specific sequences of memory operations, it is 971 possible for a hazard condition intended for a cache line to instead 972 be incorrectly associated with a different cache line. This false 973 hazard might then cause a processor deadlock. The workaround enables 974 the L1 caching of the NEON accesses and disables the PLD instruction 975 in the ACTLR register. Note that setting specific bits in the ACTLR 976 register may not be available in non-secure mode. 977 978config ARM_ERRATA_460075 979 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 980 depends on CPU_V7 981 depends on !ARCH_MULTIPLATFORM 982 help 983 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 984 erratum. Any asynchronous access to the L2 cache may encounter a 985 situation in which recent store transactions to the L2 cache are lost 986 and overwritten with stale memory contents from external memory. The 987 workaround disables the write-allocate mode for the L2 cache via the 988 ACTLR register. Note that setting specific bits in the ACTLR register 989 may not be available in non-secure mode. 990 991config ARM_ERRATA_742230 992 bool "ARM errata: DMB operation may be faulty" 993 depends on CPU_V7 && SMP 994 depends on !ARCH_MULTIPLATFORM 995 help 996 This option enables the workaround for the 742230 Cortex-A9 997 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 998 between two write operations may not ensure the correct visibility 999 ordering of the two writes. This workaround sets a specific bit in 1000 the diagnostic register of the Cortex-A9 which causes the DMB 1001 instruction to behave as a DSB, ensuring the correct behaviour of 1002 the two writes. 1003 1004config ARM_ERRATA_742231 1005 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1006 depends on CPU_V7 && SMP 1007 depends on !ARCH_MULTIPLATFORM 1008 help 1009 This option enables the workaround for the 742231 Cortex-A9 1010 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1011 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1012 accessing some data located in the same cache line, may get corrupted 1013 data due to bad handling of the address hazard when the line gets 1014 replaced from one of the CPUs at the same time as another CPU is 1015 accessing it. This workaround sets specific bits in the diagnostic 1016 register of the Cortex-A9 which reduces the linefill issuing 1017 capabilities of the processor. 1018 1019config ARM_ERRATA_643719 1020 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1021 depends on CPU_V7 && SMP 1022 default y 1023 help 1024 This option enables the workaround for the 643719 Cortex-A9 (prior to 1025 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1026 register returns zero when it should return one. The workaround 1027 corrects this value, ensuring cache maintenance operations which use 1028 it behave as intended and avoiding data corruption. 1029 1030config ARM_ERRATA_720789 1031 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1032 depends on CPU_V7 1033 help 1034 This option enables the workaround for the 720789 Cortex-A9 (prior to 1035 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1036 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1037 As a consequence of this erratum, some TLB entries which should be 1038 invalidated are not, resulting in an incoherency in the system page 1039 tables. The workaround changes the TLB flushing routines to invalidate 1040 entries regardless of the ASID. 1041 1042config ARM_ERRATA_743622 1043 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1044 depends on CPU_V7 1045 depends on !ARCH_MULTIPLATFORM 1046 help 1047 This option enables the workaround for the 743622 Cortex-A9 1048 (r2p*) erratum. Under very rare conditions, a faulty 1049 optimisation in the Cortex-A9 Store Buffer may lead to data 1050 corruption. This workaround sets a specific bit in the diagnostic 1051 register of the Cortex-A9 which disables the Store Buffer 1052 optimisation, preventing the defect from occurring. This has no 1053 visible impact on the overall performance or power consumption of the 1054 processor. 1055 1056config ARM_ERRATA_751472 1057 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1058 depends on CPU_V7 1059 depends on !ARCH_MULTIPLATFORM 1060 help 1061 This option enables the workaround for the 751472 Cortex-A9 (prior 1062 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1063 completion of a following broadcasted operation if the second 1064 operation is received by a CPU before the ICIALLUIS has completed, 1065 potentially leading to corrupted entries in the cache or TLB. 1066 1067config ARM_ERRATA_754322 1068 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1069 depends on CPU_V7 1070 help 1071 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1072 r3p*) erratum. A speculative memory access may cause a page table walk 1073 which starts prior to an ASID switch but completes afterwards. This 1074 can populate the micro-TLB with a stale entry which may be hit with 1075 the new ASID. This workaround places two dsb instructions in the mm 1076 switching code so that no page table walks can cross the ASID switch. 1077 1078config ARM_ERRATA_754327 1079 bool "ARM errata: no automatic Store Buffer drain" 1080 depends on CPU_V7 && SMP 1081 help 1082 This option enables the workaround for the 754327 Cortex-A9 (prior to 1083 r2p0) erratum. The Store Buffer does not have any automatic draining 1084 mechanism and therefore a livelock may occur if an external agent 1085 continuously polls a memory location waiting to observe an update. 1086 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1087 written polling loops from denying visibility of updates to memory. 1088 1089config ARM_ERRATA_364296 1090 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1091 depends on CPU_V6 1092 help 1093 This options enables the workaround for the 364296 ARM1136 1094 r0p2 erratum (possible cache data corruption with 1095 hit-under-miss enabled). It sets the undocumented bit 31 in 1096 the auxiliary control register and the FI bit in the control 1097 register, thus disabling hit-under-miss without putting the 1098 processor into full low interrupt latency mode. ARM11MPCore 1099 is not affected. 1100 1101config ARM_ERRATA_764369 1102 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1103 depends on CPU_V7 && SMP 1104 help 1105 This option enables the workaround for erratum 764369 1106 affecting Cortex-A9 MPCore with two or more processors (all 1107 current revisions). Under certain timing circumstances, a data 1108 cache line maintenance operation by MVA targeting an Inner 1109 Shareable memory region may fail to proceed up to either the 1110 Point of Coherency or to the Point of Unification of the 1111 system. This workaround adds a DSB instruction before the 1112 relevant cache maintenance functions and sets a specific bit 1113 in the diagnostic control register of the SCU. 1114 1115config ARM_ERRATA_775420 1116 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1117 depends on CPU_V7 1118 help 1119 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1120 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1121 operation aborts with MMU exception, it might cause the processor 1122 to deadlock. This workaround puts DSB before executing ISB if 1123 an abort may occur on cache maintenance. 1124 1125config ARM_ERRATA_798181 1126 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1127 depends on CPU_V7 && SMP 1128 help 1129 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1130 adequately shooting down all use of the old entries. This 1131 option enables the Linux kernel workaround for this erratum 1132 which sends an IPI to the CPUs that are running the same ASID 1133 as the one being invalidated. 1134 1135config ARM_ERRATA_773022 1136 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1137 depends on CPU_V7 1138 help 1139 This option enables the workaround for the 773022 Cortex-A15 1140 (up to r0p4) erratum. In certain rare sequences of code, the 1141 loop buffer may deliver incorrect instructions. This 1142 workaround disables the loop buffer to avoid the erratum. 1143 1144config ARM_ERRATA_818325_852422 1145 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1146 depends on CPU_V7 1147 help 1148 This option enables the workaround for: 1149 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1150 instruction might deadlock. Fixed in r0p1. 1151 - Cortex-A12 852422: Execution of a sequence of instructions might 1152 lead to either a data corruption or a CPU deadlock. Not fixed in 1153 any Cortex-A12 cores yet. 1154 This workaround for all both errata involves setting bit[12] of the 1155 Feature Register. This bit disables an optimisation applied to a 1156 sequence of 2 instructions that use opposing condition codes. 1157 1158config ARM_ERRATA_821420 1159 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1160 depends on CPU_V7 1161 help 1162 This option enables the workaround for the 821420 Cortex-A12 1163 (all revs) erratum. In very rare timing conditions, a sequence 1164 of VMOV to Core registers instructions, for which the second 1165 one is in the shadow of a branch or abort, can lead to a 1166 deadlock when the VMOV instructions are issued out-of-order. 1167 1168config ARM_ERRATA_825619 1169 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1170 depends on CPU_V7 1171 help 1172 This option enables the workaround for the 825619 Cortex-A12 1173 (all revs) erratum. Within rare timing constraints, executing a 1174 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1175 and Device/Strongly-Ordered loads and stores might cause deadlock 1176 1177config ARM_ERRATA_852421 1178 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1179 depends on CPU_V7 1180 help 1181 This option enables the workaround for the 852421 Cortex-A17 1182 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1183 execution of a DMB ST instruction might fail to properly order 1184 stores from GroupA and stores from GroupB. 1185 1186config ARM_ERRATA_852423 1187 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1188 depends on CPU_V7 1189 help 1190 This option enables the workaround for: 1191 - Cortex-A17 852423: Execution of a sequence of instructions might 1192 lead to either a data corruption or a CPU deadlock. Not fixed in 1193 any Cortex-A17 cores yet. 1194 This is identical to Cortex-A12 erratum 852422. It is a separate 1195 config option from the A12 erratum due to the way errata are checked 1196 for and handled. 1197 1198endmenu 1199 1200source "arch/arm/common/Kconfig" 1201 1202menu "Bus support" 1203 1204config ISA 1205 bool 1206 help 1207 Find out whether you have ISA slots on your motherboard. ISA is the 1208 name of a bus system, i.e. the way the CPU talks to the other stuff 1209 inside your box. Other bus systems are PCI, EISA, MicroChannel 1210 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1211 newer boards don't support it. If you have ISA, say Y, otherwise N. 1212 1213# Select ISA DMA controller support 1214config ISA_DMA 1215 bool 1216 select ISA_DMA_API 1217 1218# Select ISA DMA interface 1219config ISA_DMA_API 1220 bool 1221 1222config PCI_NANOENGINE 1223 bool "BSE nanoEngine PCI support" 1224 depends on SA1100_NANOENGINE 1225 help 1226 Enable PCI on the BSE nanoEngine board. 1227 1228config PCI_HOST_ITE8152 1229 bool 1230 depends on PCI && MACH_ARMCORE 1231 default y 1232 select DMABOUNCE 1233 1234endmenu 1235 1236menu "Kernel Features" 1237 1238config HAVE_SMP 1239 bool 1240 help 1241 This option should be selected by machines which have an SMP- 1242 capable CPU. 1243 1244 The only effect of this option is to make the SMP-related 1245 options available to the user for configuration. 1246 1247config SMP 1248 bool "Symmetric Multi-Processing" 1249 depends on CPU_V6K || CPU_V7 1250 depends on GENERIC_CLOCKEVENTS 1251 depends on HAVE_SMP 1252 depends on MMU || ARM_MPU 1253 select IRQ_WORK 1254 help 1255 This enables support for systems with more than one CPU. If you have 1256 a system with only one CPU, say N. If you have a system with more 1257 than one CPU, say Y. 1258 1259 If you say N here, the kernel will run on uni- and multiprocessor 1260 machines, but will use only one CPU of a multiprocessor machine. If 1261 you say Y here, the kernel will run on many, but not all, 1262 uniprocessor machines. On a uniprocessor machine, the kernel 1263 will run faster if you say N here. 1264 1265 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1266 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1267 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1268 1269 If you don't know what to do here, say N. 1270 1271config SMP_ON_UP 1272 bool "Allow booting SMP kernel on uniprocessor systems" 1273 depends on SMP && !XIP_KERNEL && MMU 1274 default y 1275 help 1276 SMP kernels contain instructions which fail on non-SMP processors. 1277 Enabling this option allows the kernel to modify itself to make 1278 these instructions safe. Disabling it allows about 1K of space 1279 savings. 1280 1281 If you don't know what to do here, say Y. 1282 1283config ARM_CPU_TOPOLOGY 1284 bool "Support cpu topology definition" 1285 depends on SMP && CPU_V7 1286 default y 1287 help 1288 Support ARM cpu topology definition. The MPIDR register defines 1289 affinity between processors which is then used to describe the cpu 1290 topology of an ARM System. 1291 1292config SCHED_MC 1293 bool "Multi-core scheduler support" 1294 depends on ARM_CPU_TOPOLOGY 1295 help 1296 Multi-core scheduler support improves the CPU scheduler's decision 1297 making when dealing with multi-core CPU chips at a cost of slightly 1298 increased overhead in some places. If unsure say N here. 1299 1300config SCHED_SMT 1301 bool "SMT scheduler support" 1302 depends on ARM_CPU_TOPOLOGY 1303 help 1304 Improves the CPU scheduler's decision making when dealing with 1305 MultiThreading at a cost of slightly increased overhead in some 1306 places. If unsure say N here. 1307 1308config HAVE_ARM_SCU 1309 bool 1310 help 1311 This option enables support for the ARM snoop control unit 1312 1313config HAVE_ARM_ARCH_TIMER 1314 bool "Architected timer support" 1315 depends on CPU_V7 1316 select ARM_ARCH_TIMER 1317 select GENERIC_CLOCKEVENTS 1318 help 1319 This option enables support for the ARM architected timer 1320 1321config HAVE_ARM_TWD 1322 bool 1323 help 1324 This options enables support for the ARM timer and watchdog unit 1325 1326config MCPM 1327 bool "Multi-Cluster Power Management" 1328 depends on CPU_V7 && SMP 1329 help 1330 This option provides the common power management infrastructure 1331 for (multi-)cluster based systems, such as big.LITTLE based 1332 systems. 1333 1334config MCPM_QUAD_CLUSTER 1335 bool 1336 depends on MCPM 1337 help 1338 To avoid wasting resources unnecessarily, MCPM only supports up 1339 to 2 clusters by default. 1340 Platforms with 3 or 4 clusters that use MCPM must select this 1341 option to allow the additional clusters to be managed. 1342 1343config BIG_LITTLE 1344 bool "big.LITTLE support (Experimental)" 1345 depends on CPU_V7 && SMP 1346 select MCPM 1347 help 1348 This option enables support selections for the big.LITTLE 1349 system architecture. 1350 1351config BL_SWITCHER 1352 bool "big.LITTLE switcher support" 1353 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1354 select CPU_PM 1355 help 1356 The big.LITTLE "switcher" provides the core functionality to 1357 transparently handle transition between a cluster of A15's 1358 and a cluster of A7's in a big.LITTLE system. 1359 1360config BL_SWITCHER_DUMMY_IF 1361 tristate "Simple big.LITTLE switcher user interface" 1362 depends on BL_SWITCHER && DEBUG_KERNEL 1363 help 1364 This is a simple and dummy char dev interface to control 1365 the big.LITTLE switcher core code. It is meant for 1366 debugging purposes only. 1367 1368choice 1369 prompt "Memory split" 1370 depends on MMU 1371 default VMSPLIT_3G 1372 help 1373 Select the desired split between kernel and user memory. 1374 1375 If you are not absolutely sure what you are doing, leave this 1376 option alone! 1377 1378 config VMSPLIT_3G 1379 bool "3G/1G user/kernel split" 1380 config VMSPLIT_3G_OPT 1381 depends on !ARM_LPAE 1382 bool "3G/1G user/kernel split (for full 1G low memory)" 1383 config VMSPLIT_2G 1384 bool "2G/2G user/kernel split" 1385 config VMSPLIT_1G 1386 bool "1G/3G user/kernel split" 1387endchoice 1388 1389config PAGE_OFFSET 1390 hex 1391 default PHYS_OFFSET if !MMU 1392 default 0x40000000 if VMSPLIT_1G 1393 default 0x80000000 if VMSPLIT_2G 1394 default 0xB0000000 if VMSPLIT_3G_OPT 1395 default 0xC0000000 1396 1397config NR_CPUS 1398 int "Maximum number of CPUs (2-32)" 1399 range 2 32 1400 depends on SMP 1401 default "4" 1402 1403config HOTPLUG_CPU 1404 bool "Support for hot-pluggable CPUs" 1405 depends on SMP 1406 select GENERIC_IRQ_MIGRATION 1407 help 1408 Say Y here to experiment with turning CPUs off and on. CPUs 1409 can be controlled through /sys/devices/system/cpu. 1410 1411config ARM_PSCI 1412 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1413 depends on HAVE_ARM_SMCCC 1414 select ARM_PSCI_FW 1415 help 1416 Say Y here if you want Linux to communicate with system firmware 1417 implementing the PSCI specification for CPU-centric power 1418 management operations described in ARM document number ARM DEN 1419 0022A ("Power State Coordination Interface System Software on 1420 ARM processors"). 1421 1422# The GPIO number here must be sorted by descending number. In case of 1423# a multiplatform kernel, we just want the highest value required by the 1424# selected platforms. 1425config ARCH_NR_GPIO 1426 int 1427 default 2048 if ARCH_SOCFPGA 1428 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1429 ARCH_ZYNQ 1430 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1431 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1432 default 416 if ARCH_SUNXI 1433 default 392 if ARCH_U8500 1434 default 352 if ARCH_VT8500 1435 default 288 if ARCH_ROCKCHIP 1436 default 264 if MACH_H4700 1437 default 0 1438 help 1439 Maximum number of GPIOs in the system. 1440 1441 If unsure, leave the default value. 1442 1443config HZ_FIXED 1444 int 1445 default 200 if ARCH_EBSA110 1446 default 128 if SOC_AT91RM9200 1447 default 0 1448 1449choice 1450 depends on HZ_FIXED = 0 1451 prompt "Timer frequency" 1452 1453config HZ_100 1454 bool "100 Hz" 1455 1456config HZ_200 1457 bool "200 Hz" 1458 1459config HZ_250 1460 bool "250 Hz" 1461 1462config HZ_300 1463 bool "300 Hz" 1464 1465config HZ_500 1466 bool "500 Hz" 1467 1468config HZ_1000 1469 bool "1000 Hz" 1470 1471endchoice 1472 1473config HZ 1474 int 1475 default HZ_FIXED if HZ_FIXED != 0 1476 default 100 if HZ_100 1477 default 200 if HZ_200 1478 default 250 if HZ_250 1479 default 300 if HZ_300 1480 default 500 if HZ_500 1481 default 1000 1482 1483config SCHED_HRTICK 1484 def_bool HIGH_RES_TIMERS 1485 1486config THUMB2_KERNEL 1487 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1488 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1489 default y if CPU_THUMBONLY 1490 select ARM_UNWIND 1491 help 1492 By enabling this option, the kernel will be compiled in 1493 Thumb-2 mode. 1494 1495 If unsure, say N. 1496 1497config THUMB2_AVOID_R_ARM_THM_JUMP11 1498 bool "Work around buggy Thumb-2 short branch relocations in gas" 1499 depends on THUMB2_KERNEL && MODULES 1500 default y 1501 help 1502 Various binutils versions can resolve Thumb-2 branches to 1503 locally-defined, preemptible global symbols as short-range "b.n" 1504 branch instructions. 1505 1506 This is a problem, because there's no guarantee the final 1507 destination of the symbol, or any candidate locations for a 1508 trampoline, are within range of the branch. For this reason, the 1509 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1510 relocation in modules at all, and it makes little sense to add 1511 support. 1512 1513 The symptom is that the kernel fails with an "unsupported 1514 relocation" error when loading some modules. 1515 1516 Until fixed tools are available, passing 1517 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1518 code which hits this problem, at the cost of a bit of extra runtime 1519 stack usage in some cases. 1520 1521 The problem is described in more detail at: 1522 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1523 1524 Only Thumb-2 kernels are affected. 1525 1526 Unless you are sure your tools don't have this problem, say Y. 1527 1528config ARM_PATCH_IDIV 1529 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1530 depends on CPU_32v7 && !XIP_KERNEL 1531 default y 1532 help 1533 The ARM compiler inserts calls to __aeabi_idiv() and 1534 __aeabi_uidiv() when it needs to perform division on signed 1535 and unsigned integers. Some v7 CPUs have support for the sdiv 1536 and udiv instructions that can be used to implement those 1537 functions. 1538 1539 Enabling this option allows the kernel to modify itself to 1540 replace the first two instructions of these library functions 1541 with the sdiv or udiv plus "bx lr" instructions when the CPU 1542 it is running on supports them. Typically this will be faster 1543 and less power intensive than running the original library 1544 code to do integer division. 1545 1546config AEABI 1547 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1548 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1549 help 1550 This option allows for the kernel to be compiled using the latest 1551 ARM ABI (aka EABI). This is only useful if you are using a user 1552 space environment that is also compiled with EABI. 1553 1554 Since there are major incompatibilities between the legacy ABI and 1555 EABI, especially with regard to structure member alignment, this 1556 option also changes the kernel syscall calling convention to 1557 disambiguate both ABIs and allow for backward compatibility support 1558 (selected with CONFIG_OABI_COMPAT). 1559 1560 To use this you need GCC version 4.0.0 or later. 1561 1562config OABI_COMPAT 1563 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1564 depends on AEABI && !THUMB2_KERNEL 1565 help 1566 This option preserves the old syscall interface along with the 1567 new (ARM EABI) one. It also provides a compatibility layer to 1568 intercept syscalls that have structure arguments which layout 1569 in memory differs between the legacy ABI and the new ARM EABI 1570 (only for non "thumb" binaries). This option adds a tiny 1571 overhead to all syscalls and produces a slightly larger kernel. 1572 1573 The seccomp filter system will not be available when this is 1574 selected, since there is no way yet to sensibly distinguish 1575 between calling conventions during filtering. 1576 1577 If you know you'll be using only pure EABI user space then you 1578 can say N here. If this option is not selected and you attempt 1579 to execute a legacy ABI binary then the result will be 1580 UNPREDICTABLE (in fact it can be predicted that it won't work 1581 at all). If in doubt say N. 1582 1583config ARCH_HAS_HOLES_MEMORYMODEL 1584 bool 1585 1586config ARCH_SPARSEMEM_ENABLE 1587 bool 1588 1589config ARCH_SPARSEMEM_DEFAULT 1590 def_bool ARCH_SPARSEMEM_ENABLE 1591 1592config ARCH_SELECT_MEMORY_MODEL 1593 def_bool ARCH_SPARSEMEM_ENABLE 1594 1595config HAVE_ARCH_PFN_VALID 1596 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1597 1598config HAVE_GENERIC_GUP 1599 def_bool y 1600 depends on ARM_LPAE 1601 1602config HIGHMEM 1603 bool "High Memory Support" 1604 depends on MMU 1605 help 1606 The address space of ARM processors is only 4 Gigabytes large 1607 and it has to accommodate user address space, kernel address 1608 space as well as some memory mapped IO. That means that, if you 1609 have a large amount of physical memory and/or IO, not all of the 1610 memory can be "permanently mapped" by the kernel. The physical 1611 memory that is not permanently mapped is called "high memory". 1612 1613 Depending on the selected kernel/user memory split, minimum 1614 vmalloc space and actual amount of RAM, you may not need this 1615 option which should result in a slightly faster kernel. 1616 1617 If unsure, say n. 1618 1619config HIGHPTE 1620 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1621 depends on HIGHMEM 1622 default y 1623 help 1624 The VM uses one page of physical memory for each page table. 1625 For systems with a lot of processes, this can use a lot of 1626 precious low memory, eventually leading to low memory being 1627 consumed by page tables. Setting this option will allow 1628 user-space 2nd level page tables to reside in high memory. 1629 1630config CPU_SW_DOMAIN_PAN 1631 bool "Enable use of CPU domains to implement privileged no-access" 1632 depends on MMU && !ARM_LPAE 1633 default y 1634 help 1635 Increase kernel security by ensuring that normal kernel accesses 1636 are unable to access userspace addresses. This can help prevent 1637 use-after-free bugs becoming an exploitable privilege escalation 1638 by ensuring that magic values (such as LIST_POISON) will always 1639 fault when dereferenced. 1640 1641 CPUs with low-vector mappings use a best-efforts implementation. 1642 Their lower 1MB needs to remain accessible for the vectors, but 1643 the remainder of userspace will become appropriately inaccessible. 1644 1645config HW_PERF_EVENTS 1646 def_bool y 1647 depends on ARM_PMU 1648 1649config SYS_SUPPORTS_HUGETLBFS 1650 def_bool y 1651 depends on ARM_LPAE 1652 1653config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1654 def_bool y 1655 depends on ARM_LPAE 1656 1657config ARCH_WANT_GENERAL_HUGETLB 1658 def_bool y 1659 1660config ARM_MODULE_PLTS 1661 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1662 depends on MODULES 1663 default y 1664 help 1665 Allocate PLTs when loading modules so that jumps and calls whose 1666 targets are too far away for their relative offsets to be encoded 1667 in the instructions themselves can be bounced via veneers in the 1668 module's PLT. This allows modules to be allocated in the generic 1669 vmalloc area after the dedicated module memory area has been 1670 exhausted. The modules will use slightly more memory, but after 1671 rounding up to page size, the actual memory footprint is usually 1672 the same. 1673 1674 Disabling this is usually safe for small single-platform 1675 configurations. If unsure, say y. 1676 1677config FORCE_MAX_ZONEORDER 1678 int "Maximum zone order" 1679 default "12" if SOC_AM33XX 1680 default "9" if SA1111 || ARCH_EFM32 1681 default "11" 1682 help 1683 The kernel memory allocator divides physically contiguous memory 1684 blocks into "zones", where each zone is a power of two number of 1685 pages. This option selects the largest power of two that the kernel 1686 keeps in the memory allocator. If you need to allocate very large 1687 blocks of physically contiguous memory, then you may need to 1688 increase this value. 1689 1690 This config option is actually maximum order plus one. For example, 1691 a value of 11 means that the largest free memory block is 2^10 pages. 1692 1693config ALIGNMENT_TRAP 1694 bool 1695 depends on CPU_CP15_MMU 1696 default y if !ARCH_EBSA110 1697 select HAVE_PROC_CPU if PROC_FS 1698 help 1699 ARM processors cannot fetch/store information which is not 1700 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1701 address divisible by 4. On 32-bit ARM processors, these non-aligned 1702 fetch/store instructions will be emulated in software if you say 1703 here, which has a severe performance impact. This is necessary for 1704 correct operation of some network protocols. With an IP-only 1705 configuration it is safe to say N, otherwise say Y. 1706 1707config UACCESS_WITH_MEMCPY 1708 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1709 depends on MMU 1710 default y if CPU_FEROCEON 1711 help 1712 Implement faster copy_to_user and clear_user methods for CPU 1713 cores where a 8-word STM instruction give significantly higher 1714 memory write throughput than a sequence of individual 32bit stores. 1715 1716 A possible side effect is a slight increase in scheduling latency 1717 between threads sharing the same address space if they invoke 1718 such copy operations with large buffers. 1719 1720 However, if the CPU data cache is using a write-allocate mode, 1721 this option is unlikely to provide any performance gain. 1722 1723config SECCOMP 1724 bool 1725 prompt "Enable seccomp to safely compute untrusted bytecode" 1726 ---help--- 1727 This kernel feature is useful for number crunching applications 1728 that may need to compute untrusted bytecode during their 1729 execution. By using pipes or other transports made available to 1730 the process as file descriptors supporting the read/write 1731 syscalls, it's possible to isolate those applications in 1732 their own address space using seccomp. Once seccomp is 1733 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1734 and the task is only allowed to execute a few safe syscalls 1735 defined by each seccomp mode. 1736 1737config PARAVIRT 1738 bool "Enable paravirtualization code" 1739 help 1740 This changes the kernel so it can modify itself when it is run 1741 under a hypervisor, potentially improving performance significantly 1742 over full virtualization. 1743 1744config PARAVIRT_TIME_ACCOUNTING 1745 bool "Paravirtual steal time accounting" 1746 select PARAVIRT 1747 help 1748 Select this option to enable fine granularity task steal time 1749 accounting. Time spent executing other tasks in parallel with 1750 the current vCPU is discounted from the vCPU power. To account for 1751 that, there can be a small performance impact. 1752 1753 If in doubt, say N here. 1754 1755config XEN_DOM0 1756 def_bool y 1757 depends on XEN 1758 1759config XEN 1760 bool "Xen guest support on ARM" 1761 depends on ARM && AEABI && OF 1762 depends on CPU_V7 && !CPU_V6 1763 depends on !GENERIC_ATOMIC64 1764 depends on MMU 1765 select ARCH_DMA_ADDR_T_64BIT 1766 select ARM_PSCI 1767 select SWIOTLB 1768 select SWIOTLB_XEN 1769 select PARAVIRT 1770 help 1771 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1772 1773config STACKPROTECTOR_PER_TASK 1774 bool "Use a unique stack canary value for each task" 1775 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1776 select GCC_PLUGIN_ARM_SSP_PER_TASK 1777 default y 1778 help 1779 Due to the fact that GCC uses an ordinary symbol reference from 1780 which to load the value of the stack canary, this value can only 1781 change at reboot time on SMP systems, and all tasks running in the 1782 kernel's address space are forced to use the same canary value for 1783 the entire duration that the system is up. 1784 1785 Enable this option to switch to a different method that uses a 1786 different canary value for each task. 1787 1788endmenu 1789 1790menu "Boot options" 1791 1792config USE_OF 1793 bool "Flattened Device Tree support" 1794 select IRQ_DOMAIN 1795 select OF 1796 help 1797 Include support for flattened device tree machine descriptions. 1798 1799config ATAGS 1800 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1801 default y 1802 help 1803 This is the traditional way of passing data to the kernel at boot 1804 time. If you are solely relying on the flattened device tree (or 1805 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1806 to remove ATAGS support from your kernel binary. If unsure, 1807 leave this to y. 1808 1809config DEPRECATED_PARAM_STRUCT 1810 bool "Provide old way to pass kernel parameters" 1811 depends on ATAGS 1812 help 1813 This was deprecated in 2001 and announced to live on for 5 years. 1814 Some old boot loaders still use this way. 1815 1816# Compressed boot loader in ROM. Yes, we really want to ask about 1817# TEXT and BSS so we preserve their values in the config files. 1818config ZBOOT_ROM_TEXT 1819 hex "Compressed ROM boot loader base address" 1820 default "0" 1821 help 1822 The physical address at which the ROM-able zImage is to be 1823 placed in the target. Platforms which normally make use of 1824 ROM-able zImage formats normally set this to a suitable 1825 value in their defconfig file. 1826 1827 If ZBOOT_ROM is not enabled, this has no effect. 1828 1829config ZBOOT_ROM_BSS 1830 hex "Compressed ROM boot loader BSS address" 1831 default "0" 1832 help 1833 The base address of an area of read/write memory in the target 1834 for the ROM-able zImage which must be available while the 1835 decompressor is running. It must be large enough to hold the 1836 entire decompressed kernel plus an additional 128 KiB. 1837 Platforms which normally make use of ROM-able zImage formats 1838 normally set this to a suitable value in their defconfig file. 1839 1840 If ZBOOT_ROM is not enabled, this has no effect. 1841 1842config ZBOOT_ROM 1843 bool "Compressed boot loader in ROM/flash" 1844 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1845 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1846 help 1847 Say Y here if you intend to execute your compressed kernel image 1848 (zImage) directly from ROM or flash. If unsure, say N. 1849 1850config ARM_APPENDED_DTB 1851 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1852 depends on OF 1853 help 1854 With this option, the boot code will look for a device tree binary 1855 (DTB) appended to zImage 1856 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1857 1858 This is meant as a backward compatibility convenience for those 1859 systems with a bootloader that can't be upgraded to accommodate 1860 the documented boot protocol using a device tree. 1861 1862 Beware that there is very little in terms of protection against 1863 this option being confused by leftover garbage in memory that might 1864 look like a DTB header after a reboot if no actual DTB is appended 1865 to zImage. Do not leave this option active in a production kernel 1866 if you don't intend to always append a DTB. Proper passing of the 1867 location into r2 of a bootloader provided DTB is always preferable 1868 to this option. 1869 1870config ARM_ATAG_DTB_COMPAT 1871 bool "Supplement the appended DTB with traditional ATAG information" 1872 depends on ARM_APPENDED_DTB 1873 help 1874 Some old bootloaders can't be updated to a DTB capable one, yet 1875 they provide ATAGs with memory configuration, the ramdisk address, 1876 the kernel cmdline string, etc. Such information is dynamically 1877 provided by the bootloader and can't always be stored in a static 1878 DTB. To allow a device tree enabled kernel to be used with such 1879 bootloaders, this option allows zImage to extract the information 1880 from the ATAG list and store it at run time into the appended DTB. 1881 1882choice 1883 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1884 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1885 1886config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1887 bool "Use bootloader kernel arguments if available" 1888 help 1889 Uses the command-line options passed by the boot loader instead of 1890 the device tree bootargs property. If the boot loader doesn't provide 1891 any, the device tree bootargs property will be used. 1892 1893config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1894 bool "Extend with bootloader kernel arguments" 1895 help 1896 The command-line arguments provided by the boot loader will be 1897 appended to the the device tree bootargs property. 1898 1899endchoice 1900 1901config CMDLINE 1902 string "Default kernel command string" 1903 default "" 1904 help 1905 On some architectures (EBSA110 and CATS), there is currently no way 1906 for the boot loader to pass arguments to the kernel. For these 1907 architectures, you should supply some command-line options at build 1908 time by entering them here. As a minimum, you should specify the 1909 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1910 1911choice 1912 prompt "Kernel command line type" if CMDLINE != "" 1913 default CMDLINE_FROM_BOOTLOADER 1914 depends on ATAGS 1915 1916config CMDLINE_FROM_BOOTLOADER 1917 bool "Use bootloader kernel arguments if available" 1918 help 1919 Uses the command-line options passed by the boot loader. If 1920 the boot loader doesn't provide any, the default kernel command 1921 string provided in CMDLINE will be used. 1922 1923config CMDLINE_EXTEND 1924 bool "Extend bootloader kernel arguments" 1925 help 1926 The command-line arguments provided by the boot loader will be 1927 appended to the default kernel command string. 1928 1929config CMDLINE_FORCE 1930 bool "Always use the default kernel command string" 1931 help 1932 Always use the default kernel command string, even if the boot 1933 loader passes other arguments to the kernel. 1934 This is useful if you cannot or don't want to change the 1935 command-line options your boot loader passes to the kernel. 1936endchoice 1937 1938config XIP_KERNEL 1939 bool "Kernel Execute-In-Place from ROM" 1940 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1941 help 1942 Execute-In-Place allows the kernel to run from non-volatile storage 1943 directly addressable by the CPU, such as NOR flash. This saves RAM 1944 space since the text section of the kernel is not loaded from flash 1945 to RAM. Read-write sections, such as the data section and stack, 1946 are still copied to RAM. The XIP kernel is not compressed since 1947 it has to run directly from flash, so it will take more space to 1948 store it. The flash address used to link the kernel object files, 1949 and for storing it, is configuration dependent. Therefore, if you 1950 say Y here, you must know the proper physical address where to 1951 store the kernel image depending on your own flash memory usage. 1952 1953 Also note that the make target becomes "make xipImage" rather than 1954 "make zImage" or "make Image". The final kernel binary to put in 1955 ROM memory will be arch/arm/boot/xipImage. 1956 1957 If unsure, say N. 1958 1959config XIP_PHYS_ADDR 1960 hex "XIP Kernel Physical Location" 1961 depends on XIP_KERNEL 1962 default "0x00080000" 1963 help 1964 This is the physical address in your flash memory the kernel will 1965 be linked for and stored to. This address is dependent on your 1966 own flash usage. 1967 1968config XIP_DEFLATED_DATA 1969 bool "Store kernel .data section compressed in ROM" 1970 depends on XIP_KERNEL 1971 select ZLIB_INFLATE 1972 help 1973 Before the kernel is actually executed, its .data section has to be 1974 copied to RAM from ROM. This option allows for storing that data 1975 in compressed form and decompressed to RAM rather than merely being 1976 copied, saving some precious ROM space. A possible drawback is a 1977 slightly longer boot delay. 1978 1979config KEXEC 1980 bool "Kexec system call (EXPERIMENTAL)" 1981 depends on (!SMP || PM_SLEEP_SMP) 1982 depends on !CPU_V7M 1983 select KEXEC_CORE 1984 help 1985 kexec is a system call that implements the ability to shutdown your 1986 current kernel, and to start another kernel. It is like a reboot 1987 but it is independent of the system firmware. And like a reboot 1988 you can start any kernel with it, not just Linux. 1989 1990 It is an ongoing process to be certain the hardware in a machine 1991 is properly shutdown, so do not be surprised if this code does not 1992 initially work for you. 1993 1994config ATAGS_PROC 1995 bool "Export atags in procfs" 1996 depends on ATAGS && KEXEC 1997 default y 1998 help 1999 Should the atags used to boot the kernel be exported in an "atags" 2000 file in procfs. Useful with kexec. 2001 2002config CRASH_DUMP 2003 bool "Build kdump crash kernel (EXPERIMENTAL)" 2004 help 2005 Generate crash dump after being started by kexec. This should 2006 be normally only set in special crash dump kernels which are 2007 loaded in the main kernel with kexec-tools into a specially 2008 reserved region and then later executed after a crash by 2009 kdump/kexec. The crash dump kernel must be compiled to a 2010 memory address not used by the main kernel 2011 2012 For more details see Documentation/kdump/kdump.txt 2013 2014config AUTO_ZRELADDR 2015 bool "Auto calculation of the decompressed kernel image address" 2016 help 2017 ZRELADDR is the physical address where the decompressed kernel 2018 image will be placed. If AUTO_ZRELADDR is selected, the address 2019 will be determined at run-time by masking the current IP with 2020 0xf8000000. This assumes the zImage being placed in the first 128MB 2021 from start of memory. 2022 2023config EFI_STUB 2024 bool 2025 2026config EFI 2027 bool "UEFI runtime support" 2028 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2029 select UCS2_STRING 2030 select EFI_PARAMS_FROM_FDT 2031 select EFI_STUB 2032 select EFI_ARMSTUB 2033 select EFI_RUNTIME_WRAPPERS 2034 ---help--- 2035 This option provides support for runtime services provided 2036 by UEFI firmware (such as non-volatile variables, realtime 2037 clock, and platform reset). A UEFI stub is also provided to 2038 allow the kernel to be booted as an EFI application. This 2039 is only useful for kernels that may run on systems that have 2040 UEFI firmware. 2041 2042config DMI 2043 bool "Enable support for SMBIOS (DMI) tables" 2044 depends on EFI 2045 default y 2046 help 2047 This enables SMBIOS/DMI feature for systems. 2048 2049 This option is only useful on systems that have UEFI firmware. 2050 However, even with this option, the resultant kernel should 2051 continue to boot on existing non-UEFI platforms. 2052 2053 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2054 i.e., the the practice of identifying the platform via DMI to 2055 decide whether certain workarounds for buggy hardware and/or 2056 firmware need to be enabled. This would require the DMI subsystem 2057 to be enabled much earlier than we do on ARM, which is non-trivial. 2058 2059endmenu 2060 2061menu "CPU Power Management" 2062 2063source "drivers/cpufreq/Kconfig" 2064 2065source "drivers/cpuidle/Kconfig" 2066 2067endmenu 2068 2069menu "Floating point emulation" 2070 2071comment "At least one emulation must be selected" 2072 2073config FPE_NWFPE 2074 bool "NWFPE math emulation" 2075 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2076 ---help--- 2077 Say Y to include the NWFPE floating point emulator in the kernel. 2078 This is necessary to run most binaries. Linux does not currently 2079 support floating point hardware so you need to say Y here even if 2080 your machine has an FPA or floating point co-processor podule. 2081 2082 You may say N here if you are going to load the Acorn FPEmulator 2083 early in the bootup. 2084 2085config FPE_NWFPE_XP 2086 bool "Support extended precision" 2087 depends on FPE_NWFPE 2088 help 2089 Say Y to include 80-bit support in the kernel floating-point 2090 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2091 Note that gcc does not generate 80-bit operations by default, 2092 so in most cases this option only enlarges the size of the 2093 floating point emulator without any good reason. 2094 2095 You almost surely want to say N here. 2096 2097config FPE_FASTFPE 2098 bool "FastFPE math emulation (EXPERIMENTAL)" 2099 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2100 ---help--- 2101 Say Y here to include the FAST floating point emulator in the kernel. 2102 This is an experimental much faster emulator which now also has full 2103 precision for the mantissa. It does not support any exceptions. 2104 It is very simple, and approximately 3-6 times faster than NWFPE. 2105 2106 It should be sufficient for most programs. It may be not suitable 2107 for scientific calculations, but you have to check this for yourself. 2108 If you do not feel you need a faster FP emulation you should better 2109 choose NWFPE. 2110 2111config VFP 2112 bool "VFP-format floating point maths" 2113 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2114 help 2115 Say Y to include VFP support code in the kernel. This is needed 2116 if your hardware includes a VFP unit. 2117 2118 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2119 release notes and additional status information. 2120 2121 Say N if your target does not have VFP hardware. 2122 2123config VFPv3 2124 bool 2125 depends on VFP 2126 default y if CPU_V7 2127 2128config NEON 2129 bool "Advanced SIMD (NEON) Extension support" 2130 depends on VFPv3 && CPU_V7 2131 help 2132 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2133 Extension. 2134 2135config KERNEL_MODE_NEON 2136 bool "Support for NEON in kernel mode" 2137 depends on NEON && AEABI 2138 help 2139 Say Y to include support for NEON in kernel mode. 2140 2141endmenu 2142 2143menu "Power management options" 2144 2145source "kernel/power/Kconfig" 2146 2147config ARCH_SUSPEND_POSSIBLE 2148 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2149 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2150 def_bool y 2151 2152config ARM_CPU_SUSPEND 2153 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2154 depends on ARCH_SUSPEND_POSSIBLE 2155 2156config ARCH_HIBERNATION_POSSIBLE 2157 bool 2158 depends on MMU 2159 default y if ARCH_SUSPEND_POSSIBLE 2160 2161endmenu 2162 2163source "drivers/firmware/Kconfig" 2164 2165if CRYPTO 2166source "arch/arm/crypto/Kconfig" 2167endif 2168 2169source "arch/arm/kvm/Kconfig" 2170