1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 23 select ARCH_HAVE_CUSTOM_GPIO_H 24 select ARCH_HAS_GCOV_PROFILE_ALL 25 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 26 select ARCH_MIGHT_HAVE_PC_PARPORT 27 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 28 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 29 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 30 select ARCH_SUPPORTS_ATOMIC_RMW 31 select ARCH_USE_BUILTIN_BSWAP 32 select ARCH_USE_CMPXCHG_LOCKREF 33 select ARCH_WANT_IPC_PARSE_VERSION 34 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 35 select BUILDTIME_EXTABLE_SORT if MMU 36 select CLONE_BACKWARDS 37 select CPU_PM if SUSPEND || CPU_IDLE 38 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 39 select DMA_DECLARE_COHERENT 40 select DMA_REMAP if MMU 41 select EDAC_SUPPORT 42 select EDAC_ATOMIC_SCRUB 43 select GENERIC_ALLOCATOR 44 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 45 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 46 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 47 select GENERIC_CPU_AUTOPROBE 48 select GENERIC_EARLY_IOREMAP 49 select GENERIC_IDLE_POLL_SETUP 50 select GENERIC_IRQ_PROBE 51 select GENERIC_IRQ_SHOW 52 select GENERIC_IRQ_SHOW_LEVEL 53 select GENERIC_PCI_IOMAP 54 select GENERIC_SCHED_CLOCK 55 select GENERIC_SMP_IDLE_THREAD 56 select GENERIC_STRNCPY_FROM_USER 57 select GENERIC_STRNLEN_USER 58 select HANDLE_DOMAIN_IRQ 59 select HARDIRQS_SW_RESEND 60 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 61 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 62 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 63 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 64 select HAVE_ARCH_MMAP_RND_BITS if MMU 65 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 66 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 67 select HAVE_ARCH_TRACEHOOK 68 select HAVE_ARM_SMCCC if CPU_V7 69 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 70 select HAVE_CONTEXT_TRACKING 71 select HAVE_C_RECORDMCOUNT 72 select HAVE_DEBUG_KMEMLEAK 73 select HAVE_DMA_CONTIGUOUS if MMU 74 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 76 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 77 select HAVE_EXIT_THREAD 78 select HAVE_FAST_GUP if ARM_LPAE 79 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 80 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 81 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 82 select HAVE_GCC_PLUGINS 83 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 84 select HAVE_IDE if PCI || ISA || PCMCIA 85 select HAVE_IRQ_TIME_ACCOUNTING 86 select HAVE_KERNEL_GZIP 87 select HAVE_KERNEL_LZ4 88 select HAVE_KERNEL_LZMA 89 select HAVE_KERNEL_LZO 90 select HAVE_KERNEL_XZ 91 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 92 select HAVE_KRETPROBES if HAVE_KPROBES 93 select HAVE_MOD_ARCH_SPECIFIC 94 select HAVE_NMI 95 select HAVE_OPROFILE if HAVE_PERF_EVENTS 96 select HAVE_OPTPROBES if !THUMB2_KERNEL 97 select HAVE_PERF_EVENTS 98 select HAVE_PERF_REGS 99 select HAVE_PERF_USER_STACK_DUMP 100 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 101 select HAVE_REGS_AND_STACK_ACCESS_API 102 select HAVE_RSEQ 103 select HAVE_STACKPROTECTOR 104 select HAVE_SYSCALL_TRACEPOINTS 105 select HAVE_UID16 106 select HAVE_VIRT_CPU_ACCOUNTING_GEN 107 select IRQ_FORCED_THREADING 108 select MODULES_USE_ELF_REL 109 select NEED_DMA_MAP_STATE 110 select OF_EARLY_FLATTREE if OF 111 select OLD_SIGACTION 112 select OLD_SIGSUSPEND3 113 select PCI_SYSCALL if PCI 114 select PERF_USE_VMALLOC 115 select REFCOUNT_FULL 116 select RTC_LIB 117 select SYS_SUPPORTS_APM_EMULATION 118 # Above selects are sorted alphabetically; please add new ones 119 # according to that. Thanks. 120 help 121 The ARM series is a line of low-power-consumption RISC chip designs 122 licensed by ARM Ltd and targeted at embedded applications and 123 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 124 manufactured, but legacy ARM-based PC hardware remains popular in 125 Europe. There is an ARM Linux project with a web page at 126 <http://www.arm.linux.org.uk/>. 127 128config ARM_HAS_SG_CHAIN 129 bool 130 131config ARM_DMA_USE_IOMMU 132 bool 133 select ARM_HAS_SG_CHAIN 134 select NEED_SG_DMA_LENGTH 135 136if ARM_DMA_USE_IOMMU 137 138config ARM_DMA_IOMMU_ALIGNMENT 139 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 140 range 4 9 141 default 8 142 help 143 DMA mapping framework by default aligns all buffers to the smallest 144 PAGE_SIZE order which is greater than or equal to the requested buffer 145 size. This works well for buffers up to a few hundreds kilobytes, but 146 for larger buffers it just a waste of address space. Drivers which has 147 relatively small addressing window (like 64Mib) might run out of 148 virtual space with just a few allocations. 149 150 With this parameter you can specify the maximum PAGE_SIZE order for 151 DMA IOMMU buffers. Larger buffers will be aligned only to this 152 specified order. The order is expressed as a power of two multiplied 153 by the PAGE_SIZE. 154 155endif 156 157config SYS_SUPPORTS_APM_EMULATION 158 bool 159 160config HAVE_TCM 161 bool 162 select GENERIC_ALLOCATOR 163 164config HAVE_PROC_CPU 165 bool 166 167config NO_IOPORT_MAP 168 bool 169 170config SBUS 171 bool 172 173config STACKTRACE_SUPPORT 174 bool 175 default y 176 177config LOCKDEP_SUPPORT 178 bool 179 default y 180 181config TRACE_IRQFLAGS_SUPPORT 182 bool 183 default !CPU_V7M 184 185config ARCH_HAS_ILOG2_U32 186 bool 187 188config ARCH_HAS_ILOG2_U64 189 bool 190 191config ARCH_HAS_BANDGAP 192 bool 193 194config FIX_EARLYCON_MEM 195 def_bool y if MMU 196 197config GENERIC_HWEIGHT 198 bool 199 default y 200 201config GENERIC_CALIBRATE_DELAY 202 bool 203 default y 204 205config ARCH_MAY_HAVE_PC_FDC 206 bool 207 208config ZONE_DMA 209 bool 210 211config ARCH_SUPPORTS_UPROBES 212 def_bool y 213 214config ARCH_HAS_DMA_SET_COHERENT_MASK 215 bool 216 217config GENERIC_ISA_DMA 218 bool 219 220config FIQ 221 bool 222 223config NEED_RET_TO_USER 224 bool 225 226config ARCH_MTD_XIP 227 bool 228 229config ARM_PATCH_PHYS_VIRT 230 bool "Patch physical to virtual translations at runtime" if EMBEDDED 231 default y 232 depends on !XIP_KERNEL && MMU 233 help 234 Patch phys-to-virt and virt-to-phys translation functions at 235 boot and module load time according to the position of the 236 kernel in system memory. 237 238 This can only be used with non-XIP MMU kernels where the base 239 of physical memory is at a 16MB boundary. 240 241 Only disable this option if you know that you do not require 242 this feature (eg, building a kernel for a single machine) and 243 you need to shrink the kernel to the minimal size. 244 245config NEED_MACH_IO_H 246 bool 247 help 248 Select this when mach/io.h is required to provide special 249 definitions for this platform. The need for mach/io.h should 250 be avoided when possible. 251 252config NEED_MACH_MEMORY_H 253 bool 254 help 255 Select this when mach/memory.h is required to provide special 256 definitions for this platform. The need for mach/memory.h should 257 be avoided when possible. 258 259config PHYS_OFFSET 260 hex "Physical address of main memory" if MMU 261 depends on !ARM_PATCH_PHYS_VIRT 262 default DRAM_BASE if !MMU 263 default 0x00000000 if ARCH_EBSA110 || \ 264 ARCH_FOOTBRIDGE || \ 265 ARCH_INTEGRATOR || \ 266 ARCH_IOP13XX || \ 267 ARCH_KS8695 || \ 268 ARCH_REALVIEW 269 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 270 default 0x20000000 if ARCH_S5PV210 271 default 0xc0000000 if ARCH_SA1100 272 help 273 Please provide the physical address corresponding to the 274 location of main memory in your system. 275 276config GENERIC_BUG 277 def_bool y 278 depends on BUG 279 280config PGTABLE_LEVELS 281 int 282 default 3 if ARM_LPAE 283 default 2 284 285menu "System Type" 286 287config MMU 288 bool "MMU-based Paged Memory Management Support" 289 default y 290 help 291 Select if you want MMU-based virtualised addressing space 292 support by paged memory management. If unsure, say 'Y'. 293 294config ARCH_MMAP_RND_BITS_MIN 295 default 8 296 297config ARCH_MMAP_RND_BITS_MAX 298 default 14 if PAGE_OFFSET=0x40000000 299 default 15 if PAGE_OFFSET=0x80000000 300 default 16 301 302# 303# The "ARM system type" choice list is ordered alphabetically by option 304# text. Please add new entries in the option alphabetic order. 305# 306choice 307 prompt "ARM system type" 308 default ARM_SINGLE_ARMV7M if !MMU 309 default ARCH_MULTIPLATFORM if MMU 310 311config ARCH_MULTIPLATFORM 312 bool "Allow multiple platforms to be selected" 313 depends on MMU 314 select ARM_HAS_SG_CHAIN 315 select ARM_PATCH_PHYS_VIRT 316 select AUTO_ZRELADDR 317 select TIMER_OF 318 select COMMON_CLK 319 select GENERIC_CLOCKEVENTS 320 select GENERIC_IRQ_MULTI_HANDLER 321 select HAVE_PCI 322 select PCI_DOMAINS_GENERIC if PCI 323 select SPARSE_IRQ 324 select USE_OF 325 326config ARM_SINGLE_ARMV7M 327 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 328 depends on !MMU 329 select ARM_NVIC 330 select AUTO_ZRELADDR 331 select TIMER_OF 332 select COMMON_CLK 333 select CPU_V7M 334 select GENERIC_CLOCKEVENTS 335 select NO_IOPORT_MAP 336 select SPARSE_IRQ 337 select USE_OF 338 339config ARCH_EBSA110 340 bool "EBSA-110" 341 select ARCH_USES_GETTIMEOFFSET 342 select CPU_SA110 343 select ISA 344 select NEED_MACH_IO_H 345 select NEED_MACH_MEMORY_H 346 select NO_IOPORT_MAP 347 help 348 This is an evaluation board for the StrongARM processor available 349 from Digital. It has limited hardware on-board, including an 350 Ethernet interface, two PCMCIA sockets, two serial ports and a 351 parallel port. 352 353config ARCH_EP93XX 354 bool "EP93xx-based" 355 select ARCH_SPARSEMEM_ENABLE 356 select ARM_AMBA 357 imply ARM_PATCH_PHYS_VIRT 358 select ARM_VIC 359 select AUTO_ZRELADDR 360 select CLKDEV_LOOKUP 361 select CLKSRC_MMIO 362 select CPU_ARM920T 363 select GENERIC_CLOCKEVENTS 364 select GPIOLIB 365 help 366 This enables support for the Cirrus EP93xx series of CPUs. 367 368config ARCH_FOOTBRIDGE 369 bool "FootBridge" 370 select CPU_SA110 371 select FOOTBRIDGE 372 select GENERIC_CLOCKEVENTS 373 select HAVE_IDE 374 select NEED_MACH_IO_H if !MMU 375 select NEED_MACH_MEMORY_H 376 help 377 Support for systems based on the DC21285 companion chip 378 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 379 380config ARCH_IOP13XX 381 bool "IOP13xx-based" 382 depends on MMU 383 select CPU_XSC3 384 select NEED_MACH_MEMORY_H 385 select NEED_RET_TO_USER 386 select FORCE_PCI 387 select PLAT_IOP 388 select VMSPLIT_1G 389 select SPARSE_IRQ 390 help 391 Support for Intel's IOP13XX (XScale) family of processors. 392 393config ARCH_IOP32X 394 bool "IOP32x-based" 395 depends on MMU 396 select CPU_XSCALE 397 select GPIO_IOP 398 select GPIOLIB 399 select NEED_RET_TO_USER 400 select FORCE_PCI 401 select PLAT_IOP 402 help 403 Support for Intel's 80219 and IOP32X (XScale) family of 404 processors. 405 406config ARCH_IOP33X 407 bool "IOP33x-based" 408 depends on MMU 409 select CPU_XSCALE 410 select GPIO_IOP 411 select GPIOLIB 412 select NEED_RET_TO_USER 413 select FORCE_PCI 414 select PLAT_IOP 415 help 416 Support for Intel's IOP33X (XScale) family of processors. 417 418config ARCH_IXP4XX 419 bool "IXP4xx-based" 420 depends on MMU 421 select ARCH_HAS_DMA_SET_COHERENT_MASK 422 select ARCH_SUPPORTS_BIG_ENDIAN 423 select CPU_XSCALE 424 select DMABOUNCE if PCI 425 select GENERIC_CLOCKEVENTS 426 select GENERIC_IRQ_MULTI_HANDLER 427 select GPIO_IXP4XX 428 select GPIOLIB 429 select HAVE_PCI 430 select IXP4XX_IRQ 431 select IXP4XX_TIMER 432 select NEED_MACH_IO_H 433 select USB_EHCI_BIG_ENDIAN_DESC 434 select USB_EHCI_BIG_ENDIAN_MMIO 435 help 436 Support for Intel's IXP4XX (XScale) family of processors. 437 438config ARCH_DOVE 439 bool "Marvell Dove" 440 select CPU_PJ4 441 select GENERIC_CLOCKEVENTS 442 select GENERIC_IRQ_MULTI_HANDLER 443 select GPIOLIB 444 select HAVE_PCI 445 select MVEBU_MBUS 446 select PINCTRL 447 select PINCTRL_DOVE 448 select PLAT_ORION_LEGACY 449 select SPARSE_IRQ 450 select PM_GENERIC_DOMAINS if PM 451 help 452 Support for the Marvell Dove SoC 88AP510 453 454config ARCH_KS8695 455 bool "Micrel/Kendin KS8695" 456 select CLKSRC_MMIO 457 select CPU_ARM922T 458 select GENERIC_CLOCKEVENTS 459 select GPIOLIB 460 select NEED_MACH_MEMORY_H 461 help 462 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 463 System-on-Chip devices. 464 465config ARCH_W90X900 466 bool "Nuvoton W90X900 CPU" 467 select CLKDEV_LOOKUP 468 select CLKSRC_MMIO 469 select CPU_ARM926T 470 select GENERIC_CLOCKEVENTS 471 select GPIOLIB 472 help 473 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 474 At present, the w90x900 has been renamed nuc900, regarding 475 the ARM series product line, you can login the following 476 link address to know more. 477 478 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 479 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 480 481config ARCH_LPC32XX 482 bool "NXP LPC32XX" 483 select ARM_AMBA 484 select CLKDEV_LOOKUP 485 select CLKSRC_LPC32XX 486 select COMMON_CLK 487 select CPU_ARM926T 488 select GENERIC_CLOCKEVENTS 489 select GENERIC_IRQ_MULTI_HANDLER 490 select GPIOLIB 491 select SPARSE_IRQ 492 select USE_OF 493 help 494 Support for the NXP LPC32XX family of processors 495 496config ARCH_PXA 497 bool "PXA2xx/PXA3xx-based" 498 depends on MMU 499 select ARCH_MTD_XIP 500 select ARM_CPU_SUSPEND if PM 501 select AUTO_ZRELADDR 502 select COMMON_CLK 503 select CLKDEV_LOOKUP 504 select CLKSRC_PXA 505 select CLKSRC_MMIO 506 select TIMER_OF 507 select CPU_XSCALE if !CPU_XSC3 508 select GENERIC_CLOCKEVENTS 509 select GENERIC_IRQ_MULTI_HANDLER 510 select GPIO_PXA 511 select GPIOLIB 512 select HAVE_IDE 513 select IRQ_DOMAIN 514 select PLAT_PXA 515 select SPARSE_IRQ 516 help 517 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 518 519config ARCH_RPC 520 bool "RiscPC" 521 depends on MMU 522 select ARCH_ACORN 523 select ARCH_MAY_HAVE_PC_FDC 524 select ARCH_SPARSEMEM_ENABLE 525 select ARM_HAS_SG_CHAIN 526 select CPU_SA110 527 select FIQ 528 select HAVE_IDE 529 select HAVE_PATA_PLATFORM 530 select ISA_DMA_API 531 select NEED_MACH_IO_H 532 select NEED_MACH_MEMORY_H 533 select NO_IOPORT_MAP 534 help 535 On the Acorn Risc-PC, Linux can support the internal IDE disk and 536 CD-ROM interface, serial and parallel port, and the floppy drive. 537 538config ARCH_SA1100 539 bool "SA1100-based" 540 select ARCH_MTD_XIP 541 select ARCH_SPARSEMEM_ENABLE 542 select CLKDEV_LOOKUP 543 select CLKSRC_MMIO 544 select CLKSRC_PXA 545 select TIMER_OF if OF 546 select COMMON_CLK 547 select CPU_FREQ 548 select CPU_SA1100 549 select GENERIC_CLOCKEVENTS 550 select GENERIC_IRQ_MULTI_HANDLER 551 select GPIOLIB 552 select HAVE_IDE 553 select IRQ_DOMAIN 554 select ISA 555 select NEED_MACH_MEMORY_H 556 select SPARSE_IRQ 557 help 558 Support for StrongARM 11x0 based boards. 559 560config ARCH_S3C24XX 561 bool "Samsung S3C24XX SoCs" 562 select ATAGS 563 select CLKDEV_LOOKUP 564 select CLKSRC_SAMSUNG_PWM 565 select GENERIC_CLOCKEVENTS 566 select GPIO_SAMSUNG 567 select GPIOLIB 568 select GENERIC_IRQ_MULTI_HANDLER 569 select HAVE_S3C2410_I2C if I2C 570 select HAVE_S3C2410_WATCHDOG if WATCHDOG 571 select HAVE_S3C_RTC if RTC_CLASS 572 select NEED_MACH_IO_H 573 select SAMSUNG_ATAGS 574 select USE_OF 575 help 576 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 577 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 578 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 579 Samsung SMDK2410 development board (and derivatives). 580 581config ARCH_DAVINCI 582 bool "TI DaVinci" 583 select ARCH_HAS_HOLES_MEMORYMODEL 584 select COMMON_CLK 585 select CPU_ARM926T 586 select GENERIC_ALLOCATOR 587 select GENERIC_CLOCKEVENTS 588 select GENERIC_IRQ_CHIP 589 select GENERIC_IRQ_MULTI_HANDLER 590 select GPIOLIB 591 select HAVE_IDE 592 select PM_GENERIC_DOMAINS if PM 593 select PM_GENERIC_DOMAINS_OF if PM && OF 594 select REGMAP_MMIO 595 select RESET_CONTROLLER 596 select SPARSE_IRQ 597 select USE_OF 598 select ZONE_DMA 599 help 600 Support for TI's DaVinci platform. 601 602config ARCH_OMAP1 603 bool "TI OMAP1" 604 depends on MMU 605 select ARCH_HAS_HOLES_MEMORYMODEL 606 select ARCH_OMAP 607 select CLKDEV_LOOKUP 608 select CLKSRC_MMIO 609 select GENERIC_CLOCKEVENTS 610 select GENERIC_IRQ_CHIP 611 select GENERIC_IRQ_MULTI_HANDLER 612 select GPIOLIB 613 select HAVE_IDE 614 select IRQ_DOMAIN 615 select NEED_MACH_IO_H if PCCARD 616 select NEED_MACH_MEMORY_H 617 select SPARSE_IRQ 618 help 619 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 620 621endchoice 622 623menu "Multiple platform selection" 624 depends on ARCH_MULTIPLATFORM 625 626comment "CPU Core family selection" 627 628config ARCH_MULTI_V4 629 bool "ARMv4 based platforms (FA526)" 630 depends on !ARCH_MULTI_V6_V7 631 select ARCH_MULTI_V4_V5 632 select CPU_FA526 633 634config ARCH_MULTI_V4T 635 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 636 depends on !ARCH_MULTI_V6_V7 637 select ARCH_MULTI_V4_V5 638 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 639 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 640 CPU_ARM925T || CPU_ARM940T) 641 642config ARCH_MULTI_V5 643 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 644 depends on !ARCH_MULTI_V6_V7 645 select ARCH_MULTI_V4_V5 646 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 647 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 648 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 649 650config ARCH_MULTI_V4_V5 651 bool 652 653config ARCH_MULTI_V6 654 bool "ARMv6 based platforms (ARM11)" 655 select ARCH_MULTI_V6_V7 656 select CPU_V6K 657 658config ARCH_MULTI_V7 659 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 660 default y 661 select ARCH_MULTI_V6_V7 662 select CPU_V7 663 select HAVE_SMP 664 665config ARCH_MULTI_V6_V7 666 bool 667 select MIGHT_HAVE_CACHE_L2X0 668 669config ARCH_MULTI_CPU_AUTO 670 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 671 select ARCH_MULTI_V5 672 673endmenu 674 675config ARCH_VIRT 676 bool "Dummy Virtual Machine" 677 depends on ARCH_MULTI_V7 678 select ARM_AMBA 679 select ARM_GIC 680 select ARM_GIC_V2M if PCI 681 select ARM_GIC_V3 682 select ARM_GIC_V3_ITS if PCI 683 select ARM_PSCI 684 select HAVE_ARM_ARCH_TIMER 685 select ARCH_SUPPORTS_BIG_ENDIAN 686 687# 688# This is sorted alphabetically by mach-* pathname. However, plat-* 689# Kconfigs may be included either alphabetically (according to the 690# plat- suffix) or along side the corresponding mach-* source. 691# 692source "arch/arm/mach-actions/Kconfig" 693 694source "arch/arm/mach-alpine/Kconfig" 695 696source "arch/arm/mach-artpec/Kconfig" 697 698source "arch/arm/mach-asm9260/Kconfig" 699 700source "arch/arm/mach-aspeed/Kconfig" 701 702source "arch/arm/mach-at91/Kconfig" 703 704source "arch/arm/mach-axxia/Kconfig" 705 706source "arch/arm/mach-bcm/Kconfig" 707 708source "arch/arm/mach-berlin/Kconfig" 709 710source "arch/arm/mach-clps711x/Kconfig" 711 712source "arch/arm/mach-cns3xxx/Kconfig" 713 714source "arch/arm/mach-davinci/Kconfig" 715 716source "arch/arm/mach-digicolor/Kconfig" 717 718source "arch/arm/mach-dove/Kconfig" 719 720source "arch/arm/mach-ep93xx/Kconfig" 721 722source "arch/arm/mach-exynos/Kconfig" 723source "arch/arm/plat-samsung/Kconfig" 724 725source "arch/arm/mach-footbridge/Kconfig" 726 727source "arch/arm/mach-gemini/Kconfig" 728 729source "arch/arm/mach-highbank/Kconfig" 730 731source "arch/arm/mach-hisi/Kconfig" 732 733source "arch/arm/mach-imx/Kconfig" 734 735source "arch/arm/mach-integrator/Kconfig" 736 737source "arch/arm/mach-iop13xx/Kconfig" 738 739source "arch/arm/mach-iop32x/Kconfig" 740 741source "arch/arm/mach-iop33x/Kconfig" 742 743source "arch/arm/mach-ixp4xx/Kconfig" 744 745source "arch/arm/mach-keystone/Kconfig" 746 747source "arch/arm/mach-ks8695/Kconfig" 748 749source "arch/arm/mach-mediatek/Kconfig" 750 751source "arch/arm/mach-meson/Kconfig" 752 753source "arch/arm/mach-milbeaut/Kconfig" 754 755source "arch/arm/mach-mmp/Kconfig" 756 757source "arch/arm/mach-moxart/Kconfig" 758 759source "arch/arm/mach-mv78xx0/Kconfig" 760 761source "arch/arm/mach-mvebu/Kconfig" 762 763source "arch/arm/mach-mxs/Kconfig" 764 765source "arch/arm/mach-nomadik/Kconfig" 766 767source "arch/arm/mach-npcm/Kconfig" 768 769source "arch/arm/mach-nspire/Kconfig" 770 771source "arch/arm/plat-omap/Kconfig" 772 773source "arch/arm/mach-omap1/Kconfig" 774 775source "arch/arm/mach-omap2/Kconfig" 776 777source "arch/arm/mach-orion5x/Kconfig" 778 779source "arch/arm/mach-oxnas/Kconfig" 780 781source "arch/arm/mach-picoxcell/Kconfig" 782 783source "arch/arm/mach-prima2/Kconfig" 784 785source "arch/arm/mach-pxa/Kconfig" 786source "arch/arm/plat-pxa/Kconfig" 787 788source "arch/arm/mach-qcom/Kconfig" 789 790source "arch/arm/mach-rda/Kconfig" 791 792source "arch/arm/mach-realview/Kconfig" 793 794source "arch/arm/mach-rockchip/Kconfig" 795 796source "arch/arm/mach-s3c24xx/Kconfig" 797 798source "arch/arm/mach-s3c64xx/Kconfig" 799 800source "arch/arm/mach-s5pv210/Kconfig" 801 802source "arch/arm/mach-sa1100/Kconfig" 803 804source "arch/arm/mach-shmobile/Kconfig" 805 806source "arch/arm/mach-socfpga/Kconfig" 807 808source "arch/arm/mach-spear/Kconfig" 809 810source "arch/arm/mach-sti/Kconfig" 811 812source "arch/arm/mach-stm32/Kconfig" 813 814source "arch/arm/mach-sunxi/Kconfig" 815 816source "arch/arm/mach-tango/Kconfig" 817 818source "arch/arm/mach-tegra/Kconfig" 819 820source "arch/arm/mach-u300/Kconfig" 821 822source "arch/arm/mach-uniphier/Kconfig" 823 824source "arch/arm/mach-ux500/Kconfig" 825 826source "arch/arm/mach-versatile/Kconfig" 827 828source "arch/arm/mach-vexpress/Kconfig" 829source "arch/arm/plat-versatile/Kconfig" 830 831source "arch/arm/mach-vt8500/Kconfig" 832 833source "arch/arm/mach-w90x900/Kconfig" 834 835source "arch/arm/mach-zx/Kconfig" 836 837source "arch/arm/mach-zynq/Kconfig" 838 839# ARMv7-M architecture 840config ARCH_EFM32 841 bool "Energy Micro efm32" 842 depends on ARM_SINGLE_ARMV7M 843 select GPIOLIB 844 help 845 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 846 processors. 847 848config ARCH_LPC18XX 849 bool "NXP LPC18xx/LPC43xx" 850 depends on ARM_SINGLE_ARMV7M 851 select ARCH_HAS_RESET_CONTROLLER 852 select ARM_AMBA 853 select CLKSRC_LPC32XX 854 select PINCTRL 855 help 856 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 857 high performance microcontrollers. 858 859config ARCH_MPS2 860 bool "ARM MPS2 platform" 861 depends on ARM_SINGLE_ARMV7M 862 select ARM_AMBA 863 select CLKSRC_MPS2 864 help 865 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 866 with a range of available cores like Cortex-M3/M4/M7. 867 868 Please, note that depends which Application Note is used memory map 869 for the platform may vary, so adjustment of RAM base might be needed. 870 871# Definitions to make life easier 872config ARCH_ACORN 873 bool 874 875config PLAT_IOP 876 bool 877 select GENERIC_CLOCKEVENTS 878 879config PLAT_ORION 880 bool 881 select CLKSRC_MMIO 882 select COMMON_CLK 883 select GENERIC_IRQ_CHIP 884 select IRQ_DOMAIN 885 886config PLAT_ORION_LEGACY 887 bool 888 select PLAT_ORION 889 890config PLAT_PXA 891 bool 892 893config PLAT_VERSATILE 894 bool 895 896source "arch/arm/mm/Kconfig" 897 898config IWMMXT 899 bool "Enable iWMMXt support" 900 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 901 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 902 help 903 Enable support for iWMMXt context switching at run time if 904 running on a CPU that supports it. 905 906if !MMU 907source "arch/arm/Kconfig-nommu" 908endif 909 910config PJ4B_ERRATA_4742 911 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 912 depends on CPU_PJ4B && MACH_ARMADA_370 913 default y 914 help 915 When coming out of either a Wait for Interrupt (WFI) or a Wait for 916 Event (WFE) IDLE states, a specific timing sensitivity exists between 917 the retiring WFI/WFE instructions and the newly issued subsequent 918 instructions. This sensitivity can result in a CPU hang scenario. 919 Workaround: 920 The software must insert either a Data Synchronization Barrier (DSB) 921 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 922 instruction 923 924config ARM_ERRATA_326103 925 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 926 depends on CPU_V6 927 help 928 Executing a SWP instruction to read-only memory does not set bit 11 929 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 930 treat the access as a read, preventing a COW from occurring and 931 causing the faulting task to livelock. 932 933config ARM_ERRATA_411920 934 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 935 depends on CPU_V6 || CPU_V6K 936 help 937 Invalidation of the Instruction Cache operation can 938 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 939 It does not affect the MPCore. This option enables the ARM Ltd. 940 recommended workaround. 941 942config ARM_ERRATA_430973 943 bool "ARM errata: Stale prediction on replaced interworking branch" 944 depends on CPU_V7 945 help 946 This option enables the workaround for the 430973 Cortex-A8 947 r1p* erratum. If a code sequence containing an ARM/Thumb 948 interworking branch is replaced with another code sequence at the 949 same virtual address, whether due to self-modifying code or virtual 950 to physical address re-mapping, Cortex-A8 does not recover from the 951 stale interworking branch prediction. This results in Cortex-A8 952 executing the new code sequence in the incorrect ARM or Thumb state. 953 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 954 and also flushes the branch target cache at every context switch. 955 Note that setting specific bits in the ACTLR register may not be 956 available in non-secure mode. 957 958config ARM_ERRATA_458693 959 bool "ARM errata: Processor deadlock when a false hazard is created" 960 depends on CPU_V7 961 depends on !ARCH_MULTIPLATFORM 962 help 963 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 964 erratum. For very specific sequences of memory operations, it is 965 possible for a hazard condition intended for a cache line to instead 966 be incorrectly associated with a different cache line. This false 967 hazard might then cause a processor deadlock. The workaround enables 968 the L1 caching of the NEON accesses and disables the PLD instruction 969 in the ACTLR register. Note that setting specific bits in the ACTLR 970 register may not be available in non-secure mode. 971 972config ARM_ERRATA_460075 973 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 974 depends on CPU_V7 975 depends on !ARCH_MULTIPLATFORM 976 help 977 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 978 erratum. Any asynchronous access to the L2 cache may encounter a 979 situation in which recent store transactions to the L2 cache are lost 980 and overwritten with stale memory contents from external memory. The 981 workaround disables the write-allocate mode for the L2 cache via the 982 ACTLR register. Note that setting specific bits in the ACTLR register 983 may not be available in non-secure mode. 984 985config ARM_ERRATA_742230 986 bool "ARM errata: DMB operation may be faulty" 987 depends on CPU_V7 && SMP 988 depends on !ARCH_MULTIPLATFORM 989 help 990 This option enables the workaround for the 742230 Cortex-A9 991 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 992 between two write operations may not ensure the correct visibility 993 ordering of the two writes. This workaround sets a specific bit in 994 the diagnostic register of the Cortex-A9 which causes the DMB 995 instruction to behave as a DSB, ensuring the correct behaviour of 996 the two writes. 997 998config ARM_ERRATA_742231 999 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1000 depends on CPU_V7 && SMP 1001 depends on !ARCH_MULTIPLATFORM 1002 help 1003 This option enables the workaround for the 742231 Cortex-A9 1004 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1005 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1006 accessing some data located in the same cache line, may get corrupted 1007 data due to bad handling of the address hazard when the line gets 1008 replaced from one of the CPUs at the same time as another CPU is 1009 accessing it. This workaround sets specific bits in the diagnostic 1010 register of the Cortex-A9 which reduces the linefill issuing 1011 capabilities of the processor. 1012 1013config ARM_ERRATA_643719 1014 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1015 depends on CPU_V7 && SMP 1016 default y 1017 help 1018 This option enables the workaround for the 643719 Cortex-A9 (prior to 1019 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1020 register returns zero when it should return one. The workaround 1021 corrects this value, ensuring cache maintenance operations which use 1022 it behave as intended and avoiding data corruption. 1023 1024config ARM_ERRATA_720789 1025 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1026 depends on CPU_V7 1027 help 1028 This option enables the workaround for the 720789 Cortex-A9 (prior to 1029 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1030 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1031 As a consequence of this erratum, some TLB entries which should be 1032 invalidated are not, resulting in an incoherency in the system page 1033 tables. The workaround changes the TLB flushing routines to invalidate 1034 entries regardless of the ASID. 1035 1036config ARM_ERRATA_743622 1037 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1038 depends on CPU_V7 1039 depends on !ARCH_MULTIPLATFORM 1040 help 1041 This option enables the workaround for the 743622 Cortex-A9 1042 (r2p*) erratum. Under very rare conditions, a faulty 1043 optimisation in the Cortex-A9 Store Buffer may lead to data 1044 corruption. This workaround sets a specific bit in the diagnostic 1045 register of the Cortex-A9 which disables the Store Buffer 1046 optimisation, preventing the defect from occurring. This has no 1047 visible impact on the overall performance or power consumption of the 1048 processor. 1049 1050config ARM_ERRATA_751472 1051 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1052 depends on CPU_V7 1053 depends on !ARCH_MULTIPLATFORM 1054 help 1055 This option enables the workaround for the 751472 Cortex-A9 (prior 1056 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1057 completion of a following broadcasted operation if the second 1058 operation is received by a CPU before the ICIALLUIS has completed, 1059 potentially leading to corrupted entries in the cache or TLB. 1060 1061config ARM_ERRATA_754322 1062 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1063 depends on CPU_V7 1064 help 1065 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1066 r3p*) erratum. A speculative memory access may cause a page table walk 1067 which starts prior to an ASID switch but completes afterwards. This 1068 can populate the micro-TLB with a stale entry which may be hit with 1069 the new ASID. This workaround places two dsb instructions in the mm 1070 switching code so that no page table walks can cross the ASID switch. 1071 1072config ARM_ERRATA_754327 1073 bool "ARM errata: no automatic Store Buffer drain" 1074 depends on CPU_V7 && SMP 1075 help 1076 This option enables the workaround for the 754327 Cortex-A9 (prior to 1077 r2p0) erratum. The Store Buffer does not have any automatic draining 1078 mechanism and therefore a livelock may occur if an external agent 1079 continuously polls a memory location waiting to observe an update. 1080 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1081 written polling loops from denying visibility of updates to memory. 1082 1083config ARM_ERRATA_364296 1084 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1085 depends on CPU_V6 1086 help 1087 This options enables the workaround for the 364296 ARM1136 1088 r0p2 erratum (possible cache data corruption with 1089 hit-under-miss enabled). It sets the undocumented bit 31 in 1090 the auxiliary control register and the FI bit in the control 1091 register, thus disabling hit-under-miss without putting the 1092 processor into full low interrupt latency mode. ARM11MPCore 1093 is not affected. 1094 1095config ARM_ERRATA_764369 1096 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1097 depends on CPU_V7 && SMP 1098 help 1099 This option enables the workaround for erratum 764369 1100 affecting Cortex-A9 MPCore with two or more processors (all 1101 current revisions). Under certain timing circumstances, a data 1102 cache line maintenance operation by MVA targeting an Inner 1103 Shareable memory region may fail to proceed up to either the 1104 Point of Coherency or to the Point of Unification of the 1105 system. This workaround adds a DSB instruction before the 1106 relevant cache maintenance functions and sets a specific bit 1107 in the diagnostic control register of the SCU. 1108 1109config ARM_ERRATA_775420 1110 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1111 depends on CPU_V7 1112 help 1113 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1114 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1115 operation aborts with MMU exception, it might cause the processor 1116 to deadlock. This workaround puts DSB before executing ISB if 1117 an abort may occur on cache maintenance. 1118 1119config ARM_ERRATA_798181 1120 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1121 depends on CPU_V7 && SMP 1122 help 1123 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1124 adequately shooting down all use of the old entries. This 1125 option enables the Linux kernel workaround for this erratum 1126 which sends an IPI to the CPUs that are running the same ASID 1127 as the one being invalidated. 1128 1129config ARM_ERRATA_773022 1130 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1131 depends on CPU_V7 1132 help 1133 This option enables the workaround for the 773022 Cortex-A15 1134 (up to r0p4) erratum. In certain rare sequences of code, the 1135 loop buffer may deliver incorrect instructions. This 1136 workaround disables the loop buffer to avoid the erratum. 1137 1138config ARM_ERRATA_818325_852422 1139 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1140 depends on CPU_V7 1141 help 1142 This option enables the workaround for: 1143 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1144 instruction might deadlock. Fixed in r0p1. 1145 - Cortex-A12 852422: Execution of a sequence of instructions might 1146 lead to either a data corruption or a CPU deadlock. Not fixed in 1147 any Cortex-A12 cores yet. 1148 This workaround for all both errata involves setting bit[12] of the 1149 Feature Register. This bit disables an optimisation applied to a 1150 sequence of 2 instructions that use opposing condition codes. 1151 1152config ARM_ERRATA_821420 1153 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1154 depends on CPU_V7 1155 help 1156 This option enables the workaround for the 821420 Cortex-A12 1157 (all revs) erratum. In very rare timing conditions, a sequence 1158 of VMOV to Core registers instructions, for which the second 1159 one is in the shadow of a branch or abort, can lead to a 1160 deadlock when the VMOV instructions are issued out-of-order. 1161 1162config ARM_ERRATA_825619 1163 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1164 depends on CPU_V7 1165 help 1166 This option enables the workaround for the 825619 Cortex-A12 1167 (all revs) erratum. Within rare timing constraints, executing a 1168 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1169 and Device/Strongly-Ordered loads and stores might cause deadlock 1170 1171config ARM_ERRATA_857271 1172 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1173 depends on CPU_V7 1174 help 1175 This option enables the workaround for the 857271 Cortex-A12 1176 (all revs) erratum. Under very rare timing conditions, the CPU might 1177 hang. The workaround is expected to have a < 1% performance impact. 1178 1179config ARM_ERRATA_852421 1180 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1181 depends on CPU_V7 1182 help 1183 This option enables the workaround for the 852421 Cortex-A17 1184 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1185 execution of a DMB ST instruction might fail to properly order 1186 stores from GroupA and stores from GroupB. 1187 1188config ARM_ERRATA_852423 1189 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1190 depends on CPU_V7 1191 help 1192 This option enables the workaround for: 1193 - Cortex-A17 852423: Execution of a sequence of instructions might 1194 lead to either a data corruption or a CPU deadlock. Not fixed in 1195 any Cortex-A17 cores yet. 1196 This is identical to Cortex-A12 erratum 852422. It is a separate 1197 config option from the A12 erratum due to the way errata are checked 1198 for and handled. 1199 1200config ARM_ERRATA_857272 1201 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1202 depends on CPU_V7 1203 help 1204 This option enables the workaround for the 857272 Cortex-A17 erratum. 1205 This erratum is not known to be fixed in any A17 revision. 1206 This is identical to Cortex-A12 erratum 857271. It is a separate 1207 config option from the A12 erratum due to the way errata are checked 1208 for and handled. 1209 1210endmenu 1211 1212source "arch/arm/common/Kconfig" 1213 1214menu "Bus support" 1215 1216config ISA 1217 bool 1218 help 1219 Find out whether you have ISA slots on your motherboard. ISA is the 1220 name of a bus system, i.e. the way the CPU talks to the other stuff 1221 inside your box. Other bus systems are PCI, EISA, MicroChannel 1222 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1223 newer boards don't support it. If you have ISA, say Y, otherwise N. 1224 1225# Select ISA DMA controller support 1226config ISA_DMA 1227 bool 1228 select ISA_DMA_API 1229 1230# Select ISA DMA interface 1231config ISA_DMA_API 1232 bool 1233 1234config PCI_NANOENGINE 1235 bool "BSE nanoEngine PCI support" 1236 depends on SA1100_NANOENGINE 1237 help 1238 Enable PCI on the BSE nanoEngine board. 1239 1240config PCI_HOST_ITE8152 1241 bool 1242 depends on PCI && MACH_ARMCORE 1243 default y 1244 select DMABOUNCE 1245 1246config ARM_ERRATA_814220 1247 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1248 depends on CPU_V7 1249 help 1250 The v7 ARM states that all cache and branch predictor maintenance 1251 operations that do not specify an address execute, relative to 1252 each other, in program order. 1253 However, because of this erratum, an L2 set/way cache maintenance 1254 operation can overtake an L1 set/way cache maintenance operation. 1255 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1256 r0p4, r0p5. 1257 1258endmenu 1259 1260menu "Kernel Features" 1261 1262config HAVE_SMP 1263 bool 1264 help 1265 This option should be selected by machines which have an SMP- 1266 capable CPU. 1267 1268 The only effect of this option is to make the SMP-related 1269 options available to the user for configuration. 1270 1271config SMP 1272 bool "Symmetric Multi-Processing" 1273 depends on CPU_V6K || CPU_V7 1274 depends on GENERIC_CLOCKEVENTS 1275 depends on HAVE_SMP 1276 depends on MMU || ARM_MPU 1277 select IRQ_WORK 1278 help 1279 This enables support for systems with more than one CPU. If you have 1280 a system with only one CPU, say N. If you have a system with more 1281 than one CPU, say Y. 1282 1283 If you say N here, the kernel will run on uni- and multiprocessor 1284 machines, but will use only one CPU of a multiprocessor machine. If 1285 you say Y here, the kernel will run on many, but not all, 1286 uniprocessor machines. On a uniprocessor machine, the kernel 1287 will run faster if you say N here. 1288 1289 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1290 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1291 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1292 1293 If you don't know what to do here, say N. 1294 1295config SMP_ON_UP 1296 bool "Allow booting SMP kernel on uniprocessor systems" 1297 depends on SMP && !XIP_KERNEL && MMU 1298 default y 1299 help 1300 SMP kernels contain instructions which fail on non-SMP processors. 1301 Enabling this option allows the kernel to modify itself to make 1302 these instructions safe. Disabling it allows about 1K of space 1303 savings. 1304 1305 If you don't know what to do here, say Y. 1306 1307config ARM_CPU_TOPOLOGY 1308 bool "Support cpu topology definition" 1309 depends on SMP && CPU_V7 1310 default y 1311 help 1312 Support ARM cpu topology definition. The MPIDR register defines 1313 affinity between processors which is then used to describe the cpu 1314 topology of an ARM System. 1315 1316config SCHED_MC 1317 bool "Multi-core scheduler support" 1318 depends on ARM_CPU_TOPOLOGY 1319 help 1320 Multi-core scheduler support improves the CPU scheduler's decision 1321 making when dealing with multi-core CPU chips at a cost of slightly 1322 increased overhead in some places. If unsure say N here. 1323 1324config SCHED_SMT 1325 bool "SMT scheduler support" 1326 depends on ARM_CPU_TOPOLOGY 1327 help 1328 Improves the CPU scheduler's decision making when dealing with 1329 MultiThreading at a cost of slightly increased overhead in some 1330 places. If unsure say N here. 1331 1332config HAVE_ARM_SCU 1333 bool 1334 help 1335 This option enables support for the ARM snoop control unit 1336 1337config HAVE_ARM_ARCH_TIMER 1338 bool "Architected timer support" 1339 depends on CPU_V7 1340 select ARM_ARCH_TIMER 1341 select GENERIC_CLOCKEVENTS 1342 help 1343 This option enables support for the ARM architected timer 1344 1345config HAVE_ARM_TWD 1346 bool 1347 help 1348 This options enables support for the ARM timer and watchdog unit 1349 1350config MCPM 1351 bool "Multi-Cluster Power Management" 1352 depends on CPU_V7 && SMP 1353 help 1354 This option provides the common power management infrastructure 1355 for (multi-)cluster based systems, such as big.LITTLE based 1356 systems. 1357 1358config MCPM_QUAD_CLUSTER 1359 bool 1360 depends on MCPM 1361 help 1362 To avoid wasting resources unnecessarily, MCPM only supports up 1363 to 2 clusters by default. 1364 Platforms with 3 or 4 clusters that use MCPM must select this 1365 option to allow the additional clusters to be managed. 1366 1367config BIG_LITTLE 1368 bool "big.LITTLE support (Experimental)" 1369 depends on CPU_V7 && SMP 1370 select MCPM 1371 help 1372 This option enables support selections for the big.LITTLE 1373 system architecture. 1374 1375config BL_SWITCHER 1376 bool "big.LITTLE switcher support" 1377 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1378 select CPU_PM 1379 help 1380 The big.LITTLE "switcher" provides the core functionality to 1381 transparently handle transition between a cluster of A15's 1382 and a cluster of A7's in a big.LITTLE system. 1383 1384config BL_SWITCHER_DUMMY_IF 1385 tristate "Simple big.LITTLE switcher user interface" 1386 depends on BL_SWITCHER && DEBUG_KERNEL 1387 help 1388 This is a simple and dummy char dev interface to control 1389 the big.LITTLE switcher core code. It is meant for 1390 debugging purposes only. 1391 1392choice 1393 prompt "Memory split" 1394 depends on MMU 1395 default VMSPLIT_3G 1396 help 1397 Select the desired split between kernel and user memory. 1398 1399 If you are not absolutely sure what you are doing, leave this 1400 option alone! 1401 1402 config VMSPLIT_3G 1403 bool "3G/1G user/kernel split" 1404 config VMSPLIT_3G_OPT 1405 depends on !ARM_LPAE 1406 bool "3G/1G user/kernel split (for full 1G low memory)" 1407 config VMSPLIT_2G 1408 bool "2G/2G user/kernel split" 1409 config VMSPLIT_1G 1410 bool "1G/3G user/kernel split" 1411endchoice 1412 1413config PAGE_OFFSET 1414 hex 1415 default PHYS_OFFSET if !MMU 1416 default 0x40000000 if VMSPLIT_1G 1417 default 0x80000000 if VMSPLIT_2G 1418 default 0xB0000000 if VMSPLIT_3G_OPT 1419 default 0xC0000000 1420 1421config NR_CPUS 1422 int "Maximum number of CPUs (2-32)" 1423 range 2 32 1424 depends on SMP 1425 default "4" 1426 1427config HOTPLUG_CPU 1428 bool "Support for hot-pluggable CPUs" 1429 depends on SMP 1430 select GENERIC_IRQ_MIGRATION 1431 help 1432 Say Y here to experiment with turning CPUs off and on. CPUs 1433 can be controlled through /sys/devices/system/cpu. 1434 1435config ARM_PSCI 1436 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1437 depends on HAVE_ARM_SMCCC 1438 select ARM_PSCI_FW 1439 help 1440 Say Y here if you want Linux to communicate with system firmware 1441 implementing the PSCI specification for CPU-centric power 1442 management operations described in ARM document number ARM DEN 1443 0022A ("Power State Coordination Interface System Software on 1444 ARM processors"). 1445 1446# The GPIO number here must be sorted by descending number. In case of 1447# a multiplatform kernel, we just want the highest value required by the 1448# selected platforms. 1449config ARCH_NR_GPIO 1450 int 1451 default 2048 if ARCH_SOCFPGA 1452 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1453 ARCH_ZYNQ 1454 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1455 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1456 default 416 if ARCH_SUNXI 1457 default 392 if ARCH_U8500 1458 default 352 if ARCH_VT8500 1459 default 288 if ARCH_ROCKCHIP 1460 default 264 if MACH_H4700 1461 default 0 1462 help 1463 Maximum number of GPIOs in the system. 1464 1465 If unsure, leave the default value. 1466 1467config HZ_FIXED 1468 int 1469 default 200 if ARCH_EBSA110 1470 default 128 if SOC_AT91RM9200 1471 default 0 1472 1473choice 1474 depends on HZ_FIXED = 0 1475 prompt "Timer frequency" 1476 1477config HZ_100 1478 bool "100 Hz" 1479 1480config HZ_200 1481 bool "200 Hz" 1482 1483config HZ_250 1484 bool "250 Hz" 1485 1486config HZ_300 1487 bool "300 Hz" 1488 1489config HZ_500 1490 bool "500 Hz" 1491 1492config HZ_1000 1493 bool "1000 Hz" 1494 1495endchoice 1496 1497config HZ 1498 int 1499 default HZ_FIXED if HZ_FIXED != 0 1500 default 100 if HZ_100 1501 default 200 if HZ_200 1502 default 250 if HZ_250 1503 default 300 if HZ_300 1504 default 500 if HZ_500 1505 default 1000 1506 1507config SCHED_HRTICK 1508 def_bool HIGH_RES_TIMERS 1509 1510config THUMB2_KERNEL 1511 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1512 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1513 default y if CPU_THUMBONLY 1514 select ARM_UNWIND 1515 help 1516 By enabling this option, the kernel will be compiled in 1517 Thumb-2 mode. 1518 1519 If unsure, say N. 1520 1521config THUMB2_AVOID_R_ARM_THM_JUMP11 1522 bool "Work around buggy Thumb-2 short branch relocations in gas" 1523 depends on THUMB2_KERNEL && MODULES 1524 default y 1525 help 1526 Various binutils versions can resolve Thumb-2 branches to 1527 locally-defined, preemptible global symbols as short-range "b.n" 1528 branch instructions. 1529 1530 This is a problem, because there's no guarantee the final 1531 destination of the symbol, or any candidate locations for a 1532 trampoline, are within range of the branch. For this reason, the 1533 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1534 relocation in modules at all, and it makes little sense to add 1535 support. 1536 1537 The symptom is that the kernel fails with an "unsupported 1538 relocation" error when loading some modules. 1539 1540 Until fixed tools are available, passing 1541 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1542 code which hits this problem, at the cost of a bit of extra runtime 1543 stack usage in some cases. 1544 1545 The problem is described in more detail at: 1546 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1547 1548 Only Thumb-2 kernels are affected. 1549 1550 Unless you are sure your tools don't have this problem, say Y. 1551 1552config ARM_PATCH_IDIV 1553 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1554 depends on CPU_32v7 && !XIP_KERNEL 1555 default y 1556 help 1557 The ARM compiler inserts calls to __aeabi_idiv() and 1558 __aeabi_uidiv() when it needs to perform division on signed 1559 and unsigned integers. Some v7 CPUs have support for the sdiv 1560 and udiv instructions that can be used to implement those 1561 functions. 1562 1563 Enabling this option allows the kernel to modify itself to 1564 replace the first two instructions of these library functions 1565 with the sdiv or udiv plus "bx lr" instructions when the CPU 1566 it is running on supports them. Typically this will be faster 1567 and less power intensive than running the original library 1568 code to do integer division. 1569 1570config AEABI 1571 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1572 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1573 help 1574 This option allows for the kernel to be compiled using the latest 1575 ARM ABI (aka EABI). This is only useful if you are using a user 1576 space environment that is also compiled with EABI. 1577 1578 Since there are major incompatibilities between the legacy ABI and 1579 EABI, especially with regard to structure member alignment, this 1580 option also changes the kernel syscall calling convention to 1581 disambiguate both ABIs and allow for backward compatibility support 1582 (selected with CONFIG_OABI_COMPAT). 1583 1584 To use this you need GCC version 4.0.0 or later. 1585 1586config OABI_COMPAT 1587 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1588 depends on AEABI && !THUMB2_KERNEL 1589 help 1590 This option preserves the old syscall interface along with the 1591 new (ARM EABI) one. It also provides a compatibility layer to 1592 intercept syscalls that have structure arguments which layout 1593 in memory differs between the legacy ABI and the new ARM EABI 1594 (only for non "thumb" binaries). This option adds a tiny 1595 overhead to all syscalls and produces a slightly larger kernel. 1596 1597 The seccomp filter system will not be available when this is 1598 selected, since there is no way yet to sensibly distinguish 1599 between calling conventions during filtering. 1600 1601 If you know you'll be using only pure EABI user space then you 1602 can say N here. If this option is not selected and you attempt 1603 to execute a legacy ABI binary then the result will be 1604 UNPREDICTABLE (in fact it can be predicted that it won't work 1605 at all). If in doubt say N. 1606 1607config ARCH_HAS_HOLES_MEMORYMODEL 1608 bool 1609 1610config ARCH_SPARSEMEM_ENABLE 1611 bool 1612 1613config ARCH_SPARSEMEM_DEFAULT 1614 def_bool ARCH_SPARSEMEM_ENABLE 1615 1616config HAVE_ARCH_PFN_VALID 1617 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1618 1619config HIGHMEM 1620 bool "High Memory Support" 1621 depends on MMU 1622 help 1623 The address space of ARM processors is only 4 Gigabytes large 1624 and it has to accommodate user address space, kernel address 1625 space as well as some memory mapped IO. That means that, if you 1626 have a large amount of physical memory and/or IO, not all of the 1627 memory can be "permanently mapped" by the kernel. The physical 1628 memory that is not permanently mapped is called "high memory". 1629 1630 Depending on the selected kernel/user memory split, minimum 1631 vmalloc space and actual amount of RAM, you may not need this 1632 option which should result in a slightly faster kernel. 1633 1634 If unsure, say n. 1635 1636config HIGHPTE 1637 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1638 depends on HIGHMEM 1639 default y 1640 help 1641 The VM uses one page of physical memory for each page table. 1642 For systems with a lot of processes, this can use a lot of 1643 precious low memory, eventually leading to low memory being 1644 consumed by page tables. Setting this option will allow 1645 user-space 2nd level page tables to reside in high memory. 1646 1647config CPU_SW_DOMAIN_PAN 1648 bool "Enable use of CPU domains to implement privileged no-access" 1649 depends on MMU && !ARM_LPAE 1650 default y 1651 help 1652 Increase kernel security by ensuring that normal kernel accesses 1653 are unable to access userspace addresses. This can help prevent 1654 use-after-free bugs becoming an exploitable privilege escalation 1655 by ensuring that magic values (such as LIST_POISON) will always 1656 fault when dereferenced. 1657 1658 CPUs with low-vector mappings use a best-efforts implementation. 1659 Their lower 1MB needs to remain accessible for the vectors, but 1660 the remainder of userspace will become appropriately inaccessible. 1661 1662config HW_PERF_EVENTS 1663 def_bool y 1664 depends on ARM_PMU 1665 1666config SYS_SUPPORTS_HUGETLBFS 1667 def_bool y 1668 depends on ARM_LPAE 1669 1670config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1671 def_bool y 1672 depends on ARM_LPAE 1673 1674config ARCH_WANT_GENERAL_HUGETLB 1675 def_bool y 1676 1677config ARM_MODULE_PLTS 1678 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1679 depends on MODULES 1680 default y 1681 help 1682 Allocate PLTs when loading modules so that jumps and calls whose 1683 targets are too far away for their relative offsets to be encoded 1684 in the instructions themselves can be bounced via veneers in the 1685 module's PLT. This allows modules to be allocated in the generic 1686 vmalloc area after the dedicated module memory area has been 1687 exhausted. The modules will use slightly more memory, but after 1688 rounding up to page size, the actual memory footprint is usually 1689 the same. 1690 1691 Disabling this is usually safe for small single-platform 1692 configurations. If unsure, say y. 1693 1694config FORCE_MAX_ZONEORDER 1695 int "Maximum zone order" 1696 default "12" if SOC_AM33XX 1697 default "9" if SA1111 || ARCH_EFM32 1698 default "11" 1699 help 1700 The kernel memory allocator divides physically contiguous memory 1701 blocks into "zones", where each zone is a power of two number of 1702 pages. This option selects the largest power of two that the kernel 1703 keeps in the memory allocator. If you need to allocate very large 1704 blocks of physically contiguous memory, then you may need to 1705 increase this value. 1706 1707 This config option is actually maximum order plus one. For example, 1708 a value of 11 means that the largest free memory block is 2^10 pages. 1709 1710config ALIGNMENT_TRAP 1711 bool 1712 depends on CPU_CP15_MMU 1713 default y if !ARCH_EBSA110 1714 select HAVE_PROC_CPU if PROC_FS 1715 help 1716 ARM processors cannot fetch/store information which is not 1717 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1718 address divisible by 4. On 32-bit ARM processors, these non-aligned 1719 fetch/store instructions will be emulated in software if you say 1720 here, which has a severe performance impact. This is necessary for 1721 correct operation of some network protocols. With an IP-only 1722 configuration it is safe to say N, otherwise say Y. 1723 1724config UACCESS_WITH_MEMCPY 1725 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1726 depends on MMU 1727 default y if CPU_FEROCEON 1728 help 1729 Implement faster copy_to_user and clear_user methods for CPU 1730 cores where a 8-word STM instruction give significantly higher 1731 memory write throughput than a sequence of individual 32bit stores. 1732 1733 A possible side effect is a slight increase in scheduling latency 1734 between threads sharing the same address space if they invoke 1735 such copy operations with large buffers. 1736 1737 However, if the CPU data cache is using a write-allocate mode, 1738 this option is unlikely to provide any performance gain. 1739 1740config SECCOMP 1741 bool 1742 prompt "Enable seccomp to safely compute untrusted bytecode" 1743 ---help--- 1744 This kernel feature is useful for number crunching applications 1745 that may need to compute untrusted bytecode during their 1746 execution. By using pipes or other transports made available to 1747 the process as file descriptors supporting the read/write 1748 syscalls, it's possible to isolate those applications in 1749 their own address space using seccomp. Once seccomp is 1750 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1751 and the task is only allowed to execute a few safe syscalls 1752 defined by each seccomp mode. 1753 1754config PARAVIRT 1755 bool "Enable paravirtualization code" 1756 help 1757 This changes the kernel so it can modify itself when it is run 1758 under a hypervisor, potentially improving performance significantly 1759 over full virtualization. 1760 1761config PARAVIRT_TIME_ACCOUNTING 1762 bool "Paravirtual steal time accounting" 1763 select PARAVIRT 1764 help 1765 Select this option to enable fine granularity task steal time 1766 accounting. Time spent executing other tasks in parallel with 1767 the current vCPU is discounted from the vCPU power. To account for 1768 that, there can be a small performance impact. 1769 1770 If in doubt, say N here. 1771 1772config XEN_DOM0 1773 def_bool y 1774 depends on XEN 1775 1776config XEN 1777 bool "Xen guest support on ARM" 1778 depends on ARM && AEABI && OF 1779 depends on CPU_V7 && !CPU_V6 1780 depends on !GENERIC_ATOMIC64 1781 depends on MMU 1782 select ARCH_DMA_ADDR_T_64BIT 1783 select ARM_PSCI 1784 select SWIOTLB 1785 select SWIOTLB_XEN 1786 select PARAVIRT 1787 help 1788 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1789 1790config STACKPROTECTOR_PER_TASK 1791 bool "Use a unique stack canary value for each task" 1792 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1793 select GCC_PLUGIN_ARM_SSP_PER_TASK 1794 default y 1795 help 1796 Due to the fact that GCC uses an ordinary symbol reference from 1797 which to load the value of the stack canary, this value can only 1798 change at reboot time on SMP systems, and all tasks running in the 1799 kernel's address space are forced to use the same canary value for 1800 the entire duration that the system is up. 1801 1802 Enable this option to switch to a different method that uses a 1803 different canary value for each task. 1804 1805endmenu 1806 1807menu "Boot options" 1808 1809config USE_OF 1810 bool "Flattened Device Tree support" 1811 select IRQ_DOMAIN 1812 select OF 1813 help 1814 Include support for flattened device tree machine descriptions. 1815 1816config ATAGS 1817 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1818 default y 1819 help 1820 This is the traditional way of passing data to the kernel at boot 1821 time. If you are solely relying on the flattened device tree (or 1822 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1823 to remove ATAGS support from your kernel binary. If unsure, 1824 leave this to y. 1825 1826config DEPRECATED_PARAM_STRUCT 1827 bool "Provide old way to pass kernel parameters" 1828 depends on ATAGS 1829 help 1830 This was deprecated in 2001 and announced to live on for 5 years. 1831 Some old boot loaders still use this way. 1832 1833# Compressed boot loader in ROM. Yes, we really want to ask about 1834# TEXT and BSS so we preserve their values in the config files. 1835config ZBOOT_ROM_TEXT 1836 hex "Compressed ROM boot loader base address" 1837 default "0" 1838 help 1839 The physical address at which the ROM-able zImage is to be 1840 placed in the target. Platforms which normally make use of 1841 ROM-able zImage formats normally set this to a suitable 1842 value in their defconfig file. 1843 1844 If ZBOOT_ROM is not enabled, this has no effect. 1845 1846config ZBOOT_ROM_BSS 1847 hex "Compressed ROM boot loader BSS address" 1848 default "0" 1849 help 1850 The base address of an area of read/write memory in the target 1851 for the ROM-able zImage which must be available while the 1852 decompressor is running. It must be large enough to hold the 1853 entire decompressed kernel plus an additional 128 KiB. 1854 Platforms which normally make use of ROM-able zImage formats 1855 normally set this to a suitable value in their defconfig file. 1856 1857 If ZBOOT_ROM is not enabled, this has no effect. 1858 1859config ZBOOT_ROM 1860 bool "Compressed boot loader in ROM/flash" 1861 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1862 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1863 help 1864 Say Y here if you intend to execute your compressed kernel image 1865 (zImage) directly from ROM or flash. If unsure, say N. 1866 1867config ARM_APPENDED_DTB 1868 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1869 depends on OF 1870 help 1871 With this option, the boot code will look for a device tree binary 1872 (DTB) appended to zImage 1873 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1874 1875 This is meant as a backward compatibility convenience for those 1876 systems with a bootloader that can't be upgraded to accommodate 1877 the documented boot protocol using a device tree. 1878 1879 Beware that there is very little in terms of protection against 1880 this option being confused by leftover garbage in memory that might 1881 look like a DTB header after a reboot if no actual DTB is appended 1882 to zImage. Do not leave this option active in a production kernel 1883 if you don't intend to always append a DTB. Proper passing of the 1884 location into r2 of a bootloader provided DTB is always preferable 1885 to this option. 1886 1887config ARM_ATAG_DTB_COMPAT 1888 bool "Supplement the appended DTB with traditional ATAG information" 1889 depends on ARM_APPENDED_DTB 1890 help 1891 Some old bootloaders can't be updated to a DTB capable one, yet 1892 they provide ATAGs with memory configuration, the ramdisk address, 1893 the kernel cmdline string, etc. Such information is dynamically 1894 provided by the bootloader and can't always be stored in a static 1895 DTB. To allow a device tree enabled kernel to be used with such 1896 bootloaders, this option allows zImage to extract the information 1897 from the ATAG list and store it at run time into the appended DTB. 1898 1899choice 1900 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1901 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1902 1903config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1904 bool "Use bootloader kernel arguments if available" 1905 help 1906 Uses the command-line options passed by the boot loader instead of 1907 the device tree bootargs property. If the boot loader doesn't provide 1908 any, the device tree bootargs property will be used. 1909 1910config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1911 bool "Extend with bootloader kernel arguments" 1912 help 1913 The command-line arguments provided by the boot loader will be 1914 appended to the the device tree bootargs property. 1915 1916endchoice 1917 1918config CMDLINE 1919 string "Default kernel command string" 1920 default "" 1921 help 1922 On some architectures (EBSA110 and CATS), there is currently no way 1923 for the boot loader to pass arguments to the kernel. For these 1924 architectures, you should supply some command-line options at build 1925 time by entering them here. As a minimum, you should specify the 1926 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1927 1928choice 1929 prompt "Kernel command line type" if CMDLINE != "" 1930 default CMDLINE_FROM_BOOTLOADER 1931 depends on ATAGS 1932 1933config CMDLINE_FROM_BOOTLOADER 1934 bool "Use bootloader kernel arguments if available" 1935 help 1936 Uses the command-line options passed by the boot loader. If 1937 the boot loader doesn't provide any, the default kernel command 1938 string provided in CMDLINE will be used. 1939 1940config CMDLINE_EXTEND 1941 bool "Extend bootloader kernel arguments" 1942 help 1943 The command-line arguments provided by the boot loader will be 1944 appended to the default kernel command string. 1945 1946config CMDLINE_FORCE 1947 bool "Always use the default kernel command string" 1948 help 1949 Always use the default kernel command string, even if the boot 1950 loader passes other arguments to the kernel. 1951 This is useful if you cannot or don't want to change the 1952 command-line options your boot loader passes to the kernel. 1953endchoice 1954 1955config XIP_KERNEL 1956 bool "Kernel Execute-In-Place from ROM" 1957 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1958 help 1959 Execute-In-Place allows the kernel to run from non-volatile storage 1960 directly addressable by the CPU, such as NOR flash. This saves RAM 1961 space since the text section of the kernel is not loaded from flash 1962 to RAM. Read-write sections, such as the data section and stack, 1963 are still copied to RAM. The XIP kernel is not compressed since 1964 it has to run directly from flash, so it will take more space to 1965 store it. The flash address used to link the kernel object files, 1966 and for storing it, is configuration dependent. Therefore, if you 1967 say Y here, you must know the proper physical address where to 1968 store the kernel image depending on your own flash memory usage. 1969 1970 Also note that the make target becomes "make xipImage" rather than 1971 "make zImage" or "make Image". The final kernel binary to put in 1972 ROM memory will be arch/arm/boot/xipImage. 1973 1974 If unsure, say N. 1975 1976config XIP_PHYS_ADDR 1977 hex "XIP Kernel Physical Location" 1978 depends on XIP_KERNEL 1979 default "0x00080000" 1980 help 1981 This is the physical address in your flash memory the kernel will 1982 be linked for and stored to. This address is dependent on your 1983 own flash usage. 1984 1985config XIP_DEFLATED_DATA 1986 bool "Store kernel .data section compressed in ROM" 1987 depends on XIP_KERNEL 1988 select ZLIB_INFLATE 1989 help 1990 Before the kernel is actually executed, its .data section has to be 1991 copied to RAM from ROM. This option allows for storing that data 1992 in compressed form and decompressed to RAM rather than merely being 1993 copied, saving some precious ROM space. A possible drawback is a 1994 slightly longer boot delay. 1995 1996config KEXEC 1997 bool "Kexec system call (EXPERIMENTAL)" 1998 depends on (!SMP || PM_SLEEP_SMP) 1999 depends on !CPU_V7M 2000 select KEXEC_CORE 2001 help 2002 kexec is a system call that implements the ability to shutdown your 2003 current kernel, and to start another kernel. It is like a reboot 2004 but it is independent of the system firmware. And like a reboot 2005 you can start any kernel with it, not just Linux. 2006 2007 It is an ongoing process to be certain the hardware in a machine 2008 is properly shutdown, so do not be surprised if this code does not 2009 initially work for you. 2010 2011config ATAGS_PROC 2012 bool "Export atags in procfs" 2013 depends on ATAGS && KEXEC 2014 default y 2015 help 2016 Should the atags used to boot the kernel be exported in an "atags" 2017 file in procfs. Useful with kexec. 2018 2019config CRASH_DUMP 2020 bool "Build kdump crash kernel (EXPERIMENTAL)" 2021 help 2022 Generate crash dump after being started by kexec. This should 2023 be normally only set in special crash dump kernels which are 2024 loaded in the main kernel with kexec-tools into a specially 2025 reserved region and then later executed after a crash by 2026 kdump/kexec. The crash dump kernel must be compiled to a 2027 memory address not used by the main kernel 2028 2029 For more details see Documentation/admin-guide/kdump/kdump.rst 2030 2031config AUTO_ZRELADDR 2032 bool "Auto calculation of the decompressed kernel image address" 2033 help 2034 ZRELADDR is the physical address where the decompressed kernel 2035 image will be placed. If AUTO_ZRELADDR is selected, the address 2036 will be determined at run-time by masking the current IP with 2037 0xf8000000. This assumes the zImage being placed in the first 128MB 2038 from start of memory. 2039 2040config EFI_STUB 2041 bool 2042 2043config EFI 2044 bool "UEFI runtime support" 2045 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2046 select UCS2_STRING 2047 select EFI_PARAMS_FROM_FDT 2048 select EFI_STUB 2049 select EFI_ARMSTUB 2050 select EFI_RUNTIME_WRAPPERS 2051 ---help--- 2052 This option provides support for runtime services provided 2053 by UEFI firmware (such as non-volatile variables, realtime 2054 clock, and platform reset). A UEFI stub is also provided to 2055 allow the kernel to be booted as an EFI application. This 2056 is only useful for kernels that may run on systems that have 2057 UEFI firmware. 2058 2059config DMI 2060 bool "Enable support for SMBIOS (DMI) tables" 2061 depends on EFI 2062 default y 2063 help 2064 This enables SMBIOS/DMI feature for systems. 2065 2066 This option is only useful on systems that have UEFI firmware. 2067 However, even with this option, the resultant kernel should 2068 continue to boot on existing non-UEFI platforms. 2069 2070 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2071 i.e., the the practice of identifying the platform via DMI to 2072 decide whether certain workarounds for buggy hardware and/or 2073 firmware need to be enabled. This would require the DMI subsystem 2074 to be enabled much earlier than we do on ARM, which is non-trivial. 2075 2076endmenu 2077 2078menu "CPU Power Management" 2079 2080source "drivers/cpufreq/Kconfig" 2081 2082source "drivers/cpuidle/Kconfig" 2083 2084endmenu 2085 2086menu "Floating point emulation" 2087 2088comment "At least one emulation must be selected" 2089 2090config FPE_NWFPE 2091 bool "NWFPE math emulation" 2092 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2093 ---help--- 2094 Say Y to include the NWFPE floating point emulator in the kernel. 2095 This is necessary to run most binaries. Linux does not currently 2096 support floating point hardware so you need to say Y here even if 2097 your machine has an FPA or floating point co-processor podule. 2098 2099 You may say N here if you are going to load the Acorn FPEmulator 2100 early in the bootup. 2101 2102config FPE_NWFPE_XP 2103 bool "Support extended precision" 2104 depends on FPE_NWFPE 2105 help 2106 Say Y to include 80-bit support in the kernel floating-point 2107 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2108 Note that gcc does not generate 80-bit operations by default, 2109 so in most cases this option only enlarges the size of the 2110 floating point emulator without any good reason. 2111 2112 You almost surely want to say N here. 2113 2114config FPE_FASTFPE 2115 bool "FastFPE math emulation (EXPERIMENTAL)" 2116 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2117 ---help--- 2118 Say Y here to include the FAST floating point emulator in the kernel. 2119 This is an experimental much faster emulator which now also has full 2120 precision for the mantissa. It does not support any exceptions. 2121 It is very simple, and approximately 3-6 times faster than NWFPE. 2122 2123 It should be sufficient for most programs. It may be not suitable 2124 for scientific calculations, but you have to check this for yourself. 2125 If you do not feel you need a faster FP emulation you should better 2126 choose NWFPE. 2127 2128config VFP 2129 bool "VFP-format floating point maths" 2130 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2131 help 2132 Say Y to include VFP support code in the kernel. This is needed 2133 if your hardware includes a VFP unit. 2134 2135 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2136 release notes and additional status information. 2137 2138 Say N if your target does not have VFP hardware. 2139 2140config VFPv3 2141 bool 2142 depends on VFP 2143 default y if CPU_V7 2144 2145config NEON 2146 bool "Advanced SIMD (NEON) Extension support" 2147 depends on VFPv3 && CPU_V7 2148 help 2149 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2150 Extension. 2151 2152config KERNEL_MODE_NEON 2153 bool "Support for NEON in kernel mode" 2154 depends on NEON && AEABI 2155 help 2156 Say Y to include support for NEON in kernel mode. 2157 2158endmenu 2159 2160menu "Power management options" 2161 2162source "kernel/power/Kconfig" 2163 2164config ARCH_SUSPEND_POSSIBLE 2165 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2166 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2167 def_bool y 2168 2169config ARM_CPU_SUSPEND 2170 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2171 depends on ARCH_SUSPEND_POSSIBLE 2172 2173config ARCH_HIBERNATION_POSSIBLE 2174 bool 2175 depends on MMU 2176 default y if ARCH_SUSPEND_POSSIBLE 2177 2178endmenu 2179 2180source "drivers/firmware/Kconfig" 2181 2182if CRYPTO 2183source "arch/arm/crypto/Kconfig" 2184endif 2185 2186source "arch/arm/kvm/Kconfig" 2187