1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_FOOTBRIDGE 351 bool "FootBridge" 352 depends on CPU_LITTLE_ENDIAN 353 select CPU_SA110 354 select FOOTBRIDGE 355 select NEED_MACH_MEMORY_H 356 help 357 Support for systems based on the DC21285 companion chip 358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 359 360config ARCH_IXP4XX 361 bool "IXP4xx-based" 362 depends on CPU_BIG_ENDIAN 363 select ARM_PATCH_PHYS_VIRT 364 select CPU_XSCALE 365 select GPIO_IXP4XX 366 select GPIOLIB 367 select HAVE_PCI 368 select IXP4XX_IRQ 369 select IXP4XX_TIMER 370 select SPARSE_IRQ 371 select USB_EHCI_BIG_ENDIAN_DESC 372 select USB_EHCI_BIG_ENDIAN_MMIO 373 help 374 Support for Intel's IXP4XX (XScale) family of processors. 375 376config ARCH_PXA 377 bool "PXA2xx/PXA3xx-based" 378 depends on CPU_LITTLE_ENDIAN 379 select ARCH_MTD_XIP 380 select ARM_CPU_SUSPEND if PM 381 select AUTO_ZRELADDR 382 select COMMON_CLK 383 select CLKSRC_PXA 384 select CLKSRC_MMIO 385 select TIMER_OF 386 select CPU_XSCALE if !CPU_XSC3 387 select GPIO_PXA 388 select GPIOLIB 389 select IRQ_DOMAIN 390 select PLAT_PXA 391 select SPARSE_IRQ 392 help 393 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 394 395config ARCH_RPC 396 bool "RiscPC" 397 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 398 depends on CPU_LITTLE_ENDIAN 399 select ARCH_ACORN 400 select ARCH_MAY_HAVE_PC_FDC 401 select ARCH_SPARSEMEM_ENABLE 402 select ARM_HAS_SG_CHAIN 403 select CPU_SA110 404 select FIQ 405 select HAVE_PATA_PLATFORM 406 select ISA_DMA_API 407 select LEGACY_TIMER_TICK 408 select NEED_MACH_IO_H 409 select NEED_MACH_MEMORY_H 410 select NO_IOPORT_MAP 411 help 412 On the Acorn Risc-PC, Linux can support the internal IDE disk and 413 CD-ROM interface, serial and parallel port, and the floppy drive. 414 415config ARCH_SA1100 416 bool "SA1100-based" 417 depends on CPU_LITTLE_ENDIAN 418 select ARCH_MTD_XIP 419 select ARCH_SPARSEMEM_ENABLE 420 select CLKSRC_MMIO 421 select CLKSRC_PXA 422 select TIMER_OF if OF 423 select COMMON_CLK 424 select CPU_FREQ 425 select CPU_SA1100 426 select GPIOLIB 427 select IRQ_DOMAIN 428 select ISA 429 select NEED_MACH_MEMORY_H 430 select SPARSE_IRQ 431 help 432 Support for StrongARM 11x0 based boards. 433 434config ARCH_OMAP1 435 bool "TI OMAP1" 436 depends on CPU_LITTLE_ENDIAN 437 select ARCH_OMAP 438 select CLKSRC_MMIO 439 select GENERIC_IRQ_CHIP 440 select GPIOLIB 441 select HAVE_LEGACY_CLK 442 select IRQ_DOMAIN 443 select NEED_MACH_IO_H if PCCARD 444 select NEED_MACH_MEMORY_H 445 select SPARSE_IRQ 446 help 447 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 448 449endchoice 450 451menu "Multiple platform selection" 452 depends on ARCH_MULTIPLATFORM 453 454comment "CPU Core family selection" 455 456config ARCH_MULTI_V4 457 bool "ARMv4 based platforms (FA526)" 458 depends on !ARCH_MULTI_V6_V7 459 select ARCH_MULTI_V4_V5 460 select CPU_FA526 461 462config ARCH_MULTI_V4T 463 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 464 depends on !ARCH_MULTI_V6_V7 465 select ARCH_MULTI_V4_V5 466 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 467 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 468 CPU_ARM925T || CPU_ARM940T) 469 470config ARCH_MULTI_V5 471 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 472 depends on !ARCH_MULTI_V6_V7 473 select ARCH_MULTI_V4_V5 474 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 475 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 476 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 477 478config ARCH_MULTI_V4_V5 479 bool 480 481config ARCH_MULTI_V6 482 bool "ARMv6 based platforms (ARM11)" 483 select ARCH_MULTI_V6_V7 484 select CPU_V6K 485 486config ARCH_MULTI_V7 487 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 488 default y 489 select ARCH_MULTI_V6_V7 490 select CPU_V7 491 select HAVE_SMP 492 493config ARCH_MULTI_V6_V7 494 bool 495 select MIGHT_HAVE_CACHE_L2X0 496 497config ARCH_MULTI_CPU_AUTO 498 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 499 select ARCH_MULTI_V5 500 501endmenu 502 503config ARCH_VIRT 504 bool "Dummy Virtual Machine" 505 depends on ARCH_MULTI_V7 506 select ARM_AMBA 507 select ARM_GIC 508 select ARM_GIC_V2M if PCI 509 select ARM_GIC_V3 510 select ARM_GIC_V3_ITS if PCI 511 select ARM_PSCI 512 select HAVE_ARM_ARCH_TIMER 513 514config ARCH_AIROHA 515 bool "Airoha SoC Support" 516 depends on ARCH_MULTI_V7 517 select ARM_AMBA 518 select ARM_GIC 519 select ARM_GIC_V3 520 select ARM_PSCI 521 select HAVE_ARM_ARCH_TIMER 522 select COMMON_CLK 523 help 524 Support for Airoha EN7523 SoCs 525 526# 527# This is sorted alphabetically by mach-* pathname. However, plat-* 528# Kconfigs may be included either alphabetically (according to the 529# plat- suffix) or along side the corresponding mach-* source. 530# 531source "arch/arm/mach-actions/Kconfig" 532 533source "arch/arm/mach-alpine/Kconfig" 534 535source "arch/arm/mach-artpec/Kconfig" 536 537source "arch/arm/mach-asm9260/Kconfig" 538 539source "arch/arm/mach-aspeed/Kconfig" 540 541source "arch/arm/mach-at91/Kconfig" 542 543source "arch/arm/mach-axxia/Kconfig" 544 545source "arch/arm/mach-bcm/Kconfig" 546 547source "arch/arm/mach-berlin/Kconfig" 548 549source "arch/arm/mach-clps711x/Kconfig" 550 551source "arch/arm/mach-cns3xxx/Kconfig" 552 553source "arch/arm/mach-davinci/Kconfig" 554 555source "arch/arm/mach-digicolor/Kconfig" 556 557source "arch/arm/mach-dove/Kconfig" 558 559source "arch/arm/mach-ep93xx/Kconfig" 560 561source "arch/arm/mach-exynos/Kconfig" 562 563source "arch/arm/mach-footbridge/Kconfig" 564 565source "arch/arm/mach-gemini/Kconfig" 566 567source "arch/arm/mach-highbank/Kconfig" 568 569source "arch/arm/mach-hisi/Kconfig" 570 571source "arch/arm/mach-imx/Kconfig" 572 573source "arch/arm/mach-iop32x/Kconfig" 574 575source "arch/arm/mach-ixp4xx/Kconfig" 576 577source "arch/arm/mach-keystone/Kconfig" 578 579source "arch/arm/mach-lpc32xx/Kconfig" 580 581source "arch/arm/mach-mediatek/Kconfig" 582 583source "arch/arm/mach-meson/Kconfig" 584 585source "arch/arm/mach-milbeaut/Kconfig" 586 587source "arch/arm/mach-mmp/Kconfig" 588 589source "arch/arm/mach-moxart/Kconfig" 590 591source "arch/arm/mach-mstar/Kconfig" 592 593source "arch/arm/mach-mv78xx0/Kconfig" 594 595source "arch/arm/mach-mvebu/Kconfig" 596 597source "arch/arm/mach-mxs/Kconfig" 598 599source "arch/arm/mach-nomadik/Kconfig" 600 601source "arch/arm/mach-npcm/Kconfig" 602 603source "arch/arm/mach-nspire/Kconfig" 604 605source "arch/arm/plat-omap/Kconfig" 606 607source "arch/arm/mach-omap1/Kconfig" 608 609source "arch/arm/mach-omap2/Kconfig" 610 611source "arch/arm/mach-orion5x/Kconfig" 612 613source "arch/arm/mach-oxnas/Kconfig" 614 615source "arch/arm/mach-pxa/Kconfig" 616source "arch/arm/plat-pxa/Kconfig" 617 618source "arch/arm/mach-qcom/Kconfig" 619 620source "arch/arm/mach-rda/Kconfig" 621 622source "arch/arm/mach-realtek/Kconfig" 623 624source "arch/arm/mach-rockchip/Kconfig" 625 626source "arch/arm/mach-s3c/Kconfig" 627 628source "arch/arm/mach-s5pv210/Kconfig" 629 630source "arch/arm/mach-sa1100/Kconfig" 631 632source "arch/arm/mach-shmobile/Kconfig" 633 634source "arch/arm/mach-socfpga/Kconfig" 635 636source "arch/arm/mach-spear/Kconfig" 637 638source "arch/arm/mach-sti/Kconfig" 639 640source "arch/arm/mach-stm32/Kconfig" 641 642source "arch/arm/mach-sunxi/Kconfig" 643 644source "arch/arm/mach-tegra/Kconfig" 645 646source "arch/arm/mach-uniphier/Kconfig" 647 648source "arch/arm/mach-ux500/Kconfig" 649 650source "arch/arm/mach-versatile/Kconfig" 651 652source "arch/arm/mach-vt8500/Kconfig" 653 654source "arch/arm/mach-zynq/Kconfig" 655 656# ARMv7-M architecture 657config ARCH_LPC18XX 658 bool "NXP LPC18xx/LPC43xx" 659 depends on ARM_SINGLE_ARMV7M 660 select ARCH_HAS_RESET_CONTROLLER 661 select ARM_AMBA 662 select CLKSRC_LPC32XX 663 select PINCTRL 664 help 665 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 666 high performance microcontrollers. 667 668config ARCH_MPS2 669 bool "ARM MPS2 platform" 670 depends on ARM_SINGLE_ARMV7M 671 select ARM_AMBA 672 select CLKSRC_MPS2 673 help 674 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 675 with a range of available cores like Cortex-M3/M4/M7. 676 677 Please, note that depends which Application Note is used memory map 678 for the platform may vary, so adjustment of RAM base might be needed. 679 680# Definitions to make life easier 681config ARCH_ACORN 682 bool 683 684config PLAT_ORION 685 bool 686 select CLKSRC_MMIO 687 select COMMON_CLK 688 select GENERIC_IRQ_CHIP 689 select IRQ_DOMAIN 690 691config PLAT_ORION_LEGACY 692 bool 693 select PLAT_ORION 694 695config PLAT_PXA 696 bool 697 698config PLAT_VERSATILE 699 bool 700 701source "arch/arm/mm/Kconfig" 702 703config IWMMXT 704 bool "Enable iWMMXt support" 705 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 706 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 707 help 708 Enable support for iWMMXt context switching at run time if 709 running on a CPU that supports it. 710 711if !MMU 712source "arch/arm/Kconfig-nommu" 713endif 714 715config PJ4B_ERRATA_4742 716 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 717 depends on CPU_PJ4B && MACH_ARMADA_370 718 default y 719 help 720 When coming out of either a Wait for Interrupt (WFI) or a Wait for 721 Event (WFE) IDLE states, a specific timing sensitivity exists between 722 the retiring WFI/WFE instructions and the newly issued subsequent 723 instructions. This sensitivity can result in a CPU hang scenario. 724 Workaround: 725 The software must insert either a Data Synchronization Barrier (DSB) 726 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 727 instruction 728 729config ARM_ERRATA_326103 730 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 731 depends on CPU_V6 732 help 733 Executing a SWP instruction to read-only memory does not set bit 11 734 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 735 treat the access as a read, preventing a COW from occurring and 736 causing the faulting task to livelock. 737 738config ARM_ERRATA_411920 739 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 740 depends on CPU_V6 || CPU_V6K 741 help 742 Invalidation of the Instruction Cache operation can 743 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 744 It does not affect the MPCore. This option enables the ARM Ltd. 745 recommended workaround. 746 747config ARM_ERRATA_430973 748 bool "ARM errata: Stale prediction on replaced interworking branch" 749 depends on CPU_V7 750 help 751 This option enables the workaround for the 430973 Cortex-A8 752 r1p* erratum. If a code sequence containing an ARM/Thumb 753 interworking branch is replaced with another code sequence at the 754 same virtual address, whether due to self-modifying code or virtual 755 to physical address re-mapping, Cortex-A8 does not recover from the 756 stale interworking branch prediction. This results in Cortex-A8 757 executing the new code sequence in the incorrect ARM or Thumb state. 758 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 759 and also flushes the branch target cache at every context switch. 760 Note that setting specific bits in the ACTLR register may not be 761 available in non-secure mode. 762 763config ARM_ERRATA_458693 764 bool "ARM errata: Processor deadlock when a false hazard is created" 765 depends on CPU_V7 766 depends on !ARCH_MULTIPLATFORM 767 help 768 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 769 erratum. For very specific sequences of memory operations, it is 770 possible for a hazard condition intended for a cache line to instead 771 be incorrectly associated with a different cache line. This false 772 hazard might then cause a processor deadlock. The workaround enables 773 the L1 caching of the NEON accesses and disables the PLD instruction 774 in the ACTLR register. Note that setting specific bits in the ACTLR 775 register may not be available in non-secure mode. 776 777config ARM_ERRATA_460075 778 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 779 depends on CPU_V7 780 depends on !ARCH_MULTIPLATFORM 781 help 782 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 783 erratum. Any asynchronous access to the L2 cache may encounter a 784 situation in which recent store transactions to the L2 cache are lost 785 and overwritten with stale memory contents from external memory. The 786 workaround disables the write-allocate mode for the L2 cache via the 787 ACTLR register. Note that setting specific bits in the ACTLR register 788 may not be available in non-secure mode. 789 790config ARM_ERRATA_742230 791 bool "ARM errata: DMB operation may be faulty" 792 depends on CPU_V7 && SMP 793 depends on !ARCH_MULTIPLATFORM 794 help 795 This option enables the workaround for the 742230 Cortex-A9 796 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 797 between two write operations may not ensure the correct visibility 798 ordering of the two writes. This workaround sets a specific bit in 799 the diagnostic register of the Cortex-A9 which causes the DMB 800 instruction to behave as a DSB, ensuring the correct behaviour of 801 the two writes. 802 803config ARM_ERRATA_742231 804 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 805 depends on CPU_V7 && SMP 806 depends on !ARCH_MULTIPLATFORM 807 help 808 This option enables the workaround for the 742231 Cortex-A9 809 (r2p0..r2p2) erratum. Under certain conditions, specific to the 810 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 811 accessing some data located in the same cache line, may get corrupted 812 data due to bad handling of the address hazard when the line gets 813 replaced from one of the CPUs at the same time as another CPU is 814 accessing it. This workaround sets specific bits in the diagnostic 815 register of the Cortex-A9 which reduces the linefill issuing 816 capabilities of the processor. 817 818config ARM_ERRATA_643719 819 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 820 depends on CPU_V7 && SMP 821 default y 822 help 823 This option enables the workaround for the 643719 Cortex-A9 (prior to 824 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 825 register returns zero when it should return one. The workaround 826 corrects this value, ensuring cache maintenance operations which use 827 it behave as intended and avoiding data corruption. 828 829config ARM_ERRATA_720789 830 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 831 depends on CPU_V7 832 help 833 This option enables the workaround for the 720789 Cortex-A9 (prior to 834 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 835 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 836 As a consequence of this erratum, some TLB entries which should be 837 invalidated are not, resulting in an incoherency in the system page 838 tables. The workaround changes the TLB flushing routines to invalidate 839 entries regardless of the ASID. 840 841config ARM_ERRATA_743622 842 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 843 depends on CPU_V7 844 depends on !ARCH_MULTIPLATFORM 845 help 846 This option enables the workaround for the 743622 Cortex-A9 847 (r2p*) erratum. Under very rare conditions, a faulty 848 optimisation in the Cortex-A9 Store Buffer may lead to data 849 corruption. This workaround sets a specific bit in the diagnostic 850 register of the Cortex-A9 which disables the Store Buffer 851 optimisation, preventing the defect from occurring. This has no 852 visible impact on the overall performance or power consumption of the 853 processor. 854 855config ARM_ERRATA_751472 856 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 857 depends on CPU_V7 858 depends on !ARCH_MULTIPLATFORM 859 help 860 This option enables the workaround for the 751472 Cortex-A9 (prior 861 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 862 completion of a following broadcasted operation if the second 863 operation is received by a CPU before the ICIALLUIS has completed, 864 potentially leading to corrupted entries in the cache or TLB. 865 866config ARM_ERRATA_754322 867 bool "ARM errata: possible faulty MMU translations following an ASID switch" 868 depends on CPU_V7 869 help 870 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 871 r3p*) erratum. A speculative memory access may cause a page table walk 872 which starts prior to an ASID switch but completes afterwards. This 873 can populate the micro-TLB with a stale entry which may be hit with 874 the new ASID. This workaround places two dsb instructions in the mm 875 switching code so that no page table walks can cross the ASID switch. 876 877config ARM_ERRATA_754327 878 bool "ARM errata: no automatic Store Buffer drain" 879 depends on CPU_V7 && SMP 880 help 881 This option enables the workaround for the 754327 Cortex-A9 (prior to 882 r2p0) erratum. The Store Buffer does not have any automatic draining 883 mechanism and therefore a livelock may occur if an external agent 884 continuously polls a memory location waiting to observe an update. 885 This workaround defines cpu_relax() as smp_mb(), preventing correctly 886 written polling loops from denying visibility of updates to memory. 887 888config ARM_ERRATA_364296 889 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 890 depends on CPU_V6 891 help 892 This options enables the workaround for the 364296 ARM1136 893 r0p2 erratum (possible cache data corruption with 894 hit-under-miss enabled). It sets the undocumented bit 31 in 895 the auxiliary control register and the FI bit in the control 896 register, thus disabling hit-under-miss without putting the 897 processor into full low interrupt latency mode. ARM11MPCore 898 is not affected. 899 900config ARM_ERRATA_764369 901 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 902 depends on CPU_V7 && SMP 903 help 904 This option enables the workaround for erratum 764369 905 affecting Cortex-A9 MPCore with two or more processors (all 906 current revisions). Under certain timing circumstances, a data 907 cache line maintenance operation by MVA targeting an Inner 908 Shareable memory region may fail to proceed up to either the 909 Point of Coherency or to the Point of Unification of the 910 system. This workaround adds a DSB instruction before the 911 relevant cache maintenance functions and sets a specific bit 912 in the diagnostic control register of the SCU. 913 914config ARM_ERRATA_775420 915 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 916 depends on CPU_V7 917 help 918 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 919 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 920 operation aborts with MMU exception, it might cause the processor 921 to deadlock. This workaround puts DSB before executing ISB if 922 an abort may occur on cache maintenance. 923 924config ARM_ERRATA_798181 925 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 926 depends on CPU_V7 && SMP 927 help 928 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 929 adequately shooting down all use of the old entries. This 930 option enables the Linux kernel workaround for this erratum 931 which sends an IPI to the CPUs that are running the same ASID 932 as the one being invalidated. 933 934config ARM_ERRATA_773022 935 bool "ARM errata: incorrect instructions may be executed from loop buffer" 936 depends on CPU_V7 937 help 938 This option enables the workaround for the 773022 Cortex-A15 939 (up to r0p4) erratum. In certain rare sequences of code, the 940 loop buffer may deliver incorrect instructions. This 941 workaround disables the loop buffer to avoid the erratum. 942 943config ARM_ERRATA_818325_852422 944 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 945 depends on CPU_V7 946 help 947 This option enables the workaround for: 948 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 949 instruction might deadlock. Fixed in r0p1. 950 - Cortex-A12 852422: Execution of a sequence of instructions might 951 lead to either a data corruption or a CPU deadlock. Not fixed in 952 any Cortex-A12 cores yet. 953 This workaround for all both errata involves setting bit[12] of the 954 Feature Register. This bit disables an optimisation applied to a 955 sequence of 2 instructions that use opposing condition codes. 956 957config ARM_ERRATA_821420 958 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 959 depends on CPU_V7 960 help 961 This option enables the workaround for the 821420 Cortex-A12 962 (all revs) erratum. In very rare timing conditions, a sequence 963 of VMOV to Core registers instructions, for which the second 964 one is in the shadow of a branch or abort, can lead to a 965 deadlock when the VMOV instructions are issued out-of-order. 966 967config ARM_ERRATA_825619 968 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 969 depends on CPU_V7 970 help 971 This option enables the workaround for the 825619 Cortex-A12 972 (all revs) erratum. Within rare timing constraints, executing a 973 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 974 and Device/Strongly-Ordered loads and stores might cause deadlock 975 976config ARM_ERRATA_857271 977 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 978 depends on CPU_V7 979 help 980 This option enables the workaround for the 857271 Cortex-A12 981 (all revs) erratum. Under very rare timing conditions, the CPU might 982 hang. The workaround is expected to have a < 1% performance impact. 983 984config ARM_ERRATA_852421 985 bool "ARM errata: A17: DMB ST might fail to create order between stores" 986 depends on CPU_V7 987 help 988 This option enables the workaround for the 852421 Cortex-A17 989 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 990 execution of a DMB ST instruction might fail to properly order 991 stores from GroupA and stores from GroupB. 992 993config ARM_ERRATA_852423 994 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 995 depends on CPU_V7 996 help 997 This option enables the workaround for: 998 - Cortex-A17 852423: Execution of a sequence of instructions might 999 lead to either a data corruption or a CPU deadlock. Not fixed in 1000 any Cortex-A17 cores yet. 1001 This is identical to Cortex-A12 erratum 852422. It is a separate 1002 config option from the A12 erratum due to the way errata are checked 1003 for and handled. 1004 1005config ARM_ERRATA_857272 1006 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1007 depends on CPU_V7 1008 help 1009 This option enables the workaround for the 857272 Cortex-A17 erratum. 1010 This erratum is not known to be fixed in any A17 revision. 1011 This is identical to Cortex-A12 erratum 857271. It is a separate 1012 config option from the A12 erratum due to the way errata are checked 1013 for and handled. 1014 1015endmenu 1016 1017source "arch/arm/common/Kconfig" 1018 1019menu "Bus support" 1020 1021config ISA 1022 bool 1023 help 1024 Find out whether you have ISA slots on your motherboard. ISA is the 1025 name of a bus system, i.e. the way the CPU talks to the other stuff 1026 inside your box. Other bus systems are PCI, EISA, MicroChannel 1027 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1028 newer boards don't support it. If you have ISA, say Y, otherwise N. 1029 1030# Select ISA DMA controller support 1031config ISA_DMA 1032 bool 1033 select ISA_DMA_API 1034 1035# Select ISA DMA interface 1036config ISA_DMA_API 1037 bool 1038 1039config PCI_NANOENGINE 1040 bool "BSE nanoEngine PCI support" 1041 depends on SA1100_NANOENGINE 1042 help 1043 Enable PCI on the BSE nanoEngine board. 1044 1045config ARM_ERRATA_814220 1046 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1047 depends on CPU_V7 1048 help 1049 The v7 ARM states that all cache and branch predictor maintenance 1050 operations that do not specify an address execute, relative to 1051 each other, in program order. 1052 However, because of this erratum, an L2 set/way cache maintenance 1053 operation can overtake an L1 set/way cache maintenance operation. 1054 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1055 r0p4, r0p5. 1056 1057endmenu 1058 1059menu "Kernel Features" 1060 1061config HAVE_SMP 1062 bool 1063 help 1064 This option should be selected by machines which have an SMP- 1065 capable CPU. 1066 1067 The only effect of this option is to make the SMP-related 1068 options available to the user for configuration. 1069 1070config SMP 1071 bool "Symmetric Multi-Processing" 1072 depends on CPU_V6K || CPU_V7 1073 depends on HAVE_SMP 1074 depends on MMU || ARM_MPU 1075 select IRQ_WORK 1076 help 1077 This enables support for systems with more than one CPU. If you have 1078 a system with only one CPU, say N. If you have a system with more 1079 than one CPU, say Y. 1080 1081 If you say N here, the kernel will run on uni- and multiprocessor 1082 machines, but will use only one CPU of a multiprocessor machine. If 1083 you say Y here, the kernel will run on many, but not all, 1084 uniprocessor machines. On a uniprocessor machine, the kernel 1085 will run faster if you say N here. 1086 1087 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1088 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1089 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1090 1091 If you don't know what to do here, say N. 1092 1093config SMP_ON_UP 1094 bool "Allow booting SMP kernel on uniprocessor systems" 1095 depends on SMP && !XIP_KERNEL && MMU 1096 default y 1097 help 1098 SMP kernels contain instructions which fail on non-SMP processors. 1099 Enabling this option allows the kernel to modify itself to make 1100 these instructions safe. Disabling it allows about 1K of space 1101 savings. 1102 1103 If you don't know what to do here, say Y. 1104 1105 1106config CURRENT_POINTER_IN_TPIDRURO 1107 def_bool y 1108 depends on CPU_32v6K && !CPU_V6 1109 1110config IRQSTACKS 1111 def_bool y 1112 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1113 select HAVE_SOFTIRQ_ON_OWN_STACK 1114 1115config ARM_CPU_TOPOLOGY 1116 bool "Support cpu topology definition" 1117 depends on SMP && CPU_V7 1118 default y 1119 help 1120 Support ARM cpu topology definition. The MPIDR register defines 1121 affinity between processors which is then used to describe the cpu 1122 topology of an ARM System. 1123 1124config SCHED_MC 1125 bool "Multi-core scheduler support" 1126 depends on ARM_CPU_TOPOLOGY 1127 help 1128 Multi-core scheduler support improves the CPU scheduler's decision 1129 making when dealing with multi-core CPU chips at a cost of slightly 1130 increased overhead in some places. If unsure say N here. 1131 1132config SCHED_SMT 1133 bool "SMT scheduler support" 1134 depends on ARM_CPU_TOPOLOGY 1135 help 1136 Improves the CPU scheduler's decision making when dealing with 1137 MultiThreading at a cost of slightly increased overhead in some 1138 places. If unsure say N here. 1139 1140config HAVE_ARM_SCU 1141 bool 1142 help 1143 This option enables support for the ARM snoop control unit 1144 1145config HAVE_ARM_ARCH_TIMER 1146 bool "Architected timer support" 1147 depends on CPU_V7 1148 select ARM_ARCH_TIMER 1149 help 1150 This option enables support for the ARM architected timer 1151 1152config HAVE_ARM_TWD 1153 bool 1154 help 1155 This options enables support for the ARM timer and watchdog unit 1156 1157config MCPM 1158 bool "Multi-Cluster Power Management" 1159 depends on CPU_V7 && SMP 1160 help 1161 This option provides the common power management infrastructure 1162 for (multi-)cluster based systems, such as big.LITTLE based 1163 systems. 1164 1165config MCPM_QUAD_CLUSTER 1166 bool 1167 depends on MCPM 1168 help 1169 To avoid wasting resources unnecessarily, MCPM only supports up 1170 to 2 clusters by default. 1171 Platforms with 3 or 4 clusters that use MCPM must select this 1172 option to allow the additional clusters to be managed. 1173 1174config BIG_LITTLE 1175 bool "big.LITTLE support (Experimental)" 1176 depends on CPU_V7 && SMP 1177 select MCPM 1178 help 1179 This option enables support selections for the big.LITTLE 1180 system architecture. 1181 1182config BL_SWITCHER 1183 bool "big.LITTLE switcher support" 1184 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1185 select CPU_PM 1186 help 1187 The big.LITTLE "switcher" provides the core functionality to 1188 transparently handle transition between a cluster of A15's 1189 and a cluster of A7's in a big.LITTLE system. 1190 1191config BL_SWITCHER_DUMMY_IF 1192 tristate "Simple big.LITTLE switcher user interface" 1193 depends on BL_SWITCHER && DEBUG_KERNEL 1194 help 1195 This is a simple and dummy char dev interface to control 1196 the big.LITTLE switcher core code. It is meant for 1197 debugging purposes only. 1198 1199choice 1200 prompt "Memory split" 1201 depends on MMU 1202 default VMSPLIT_3G 1203 help 1204 Select the desired split between kernel and user memory. 1205 1206 If you are not absolutely sure what you are doing, leave this 1207 option alone! 1208 1209 config VMSPLIT_3G 1210 bool "3G/1G user/kernel split" 1211 config VMSPLIT_3G_OPT 1212 depends on !ARM_LPAE 1213 bool "3G/1G user/kernel split (for full 1G low memory)" 1214 config VMSPLIT_2G 1215 bool "2G/2G user/kernel split" 1216 config VMSPLIT_1G 1217 bool "1G/3G user/kernel split" 1218endchoice 1219 1220config PAGE_OFFSET 1221 hex 1222 default PHYS_OFFSET if !MMU 1223 default 0x40000000 if VMSPLIT_1G 1224 default 0x80000000 if VMSPLIT_2G 1225 default 0xB0000000 if VMSPLIT_3G_OPT 1226 default 0xC0000000 1227 1228config KASAN_SHADOW_OFFSET 1229 hex 1230 depends on KASAN 1231 default 0x1f000000 if PAGE_OFFSET=0x40000000 1232 default 0x5f000000 if PAGE_OFFSET=0x80000000 1233 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1234 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1235 default 0xffffffff 1236 1237config NR_CPUS 1238 int "Maximum number of CPUs (2-32)" 1239 range 2 16 if DEBUG_KMAP_LOCAL 1240 range 2 32 if !DEBUG_KMAP_LOCAL 1241 depends on SMP 1242 default "4" 1243 help 1244 The maximum number of CPUs that the kernel can support. 1245 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1246 debugging is enabled, which uses half of the per-CPU fixmap 1247 slots as guard regions. 1248 1249config HOTPLUG_CPU 1250 bool "Support for hot-pluggable CPUs" 1251 depends on SMP 1252 select GENERIC_IRQ_MIGRATION 1253 help 1254 Say Y here to experiment with turning CPUs off and on. CPUs 1255 can be controlled through /sys/devices/system/cpu. 1256 1257config ARM_PSCI 1258 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1259 depends on HAVE_ARM_SMCCC 1260 select ARM_PSCI_FW 1261 help 1262 Say Y here if you want Linux to communicate with system firmware 1263 implementing the PSCI specification for CPU-centric power 1264 management operations described in ARM document number ARM DEN 1265 0022A ("Power State Coordination Interface System Software on 1266 ARM processors"). 1267 1268# The GPIO number here must be sorted by descending number. In case of 1269# a multiplatform kernel, we just want the highest value required by the 1270# selected platforms. 1271config ARCH_NR_GPIO 1272 int 1273 default 2048 if ARCH_INTEL_SOCFPGA 1274 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1275 ARCH_ZYNQ || ARCH_ASPEED 1276 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1277 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1278 default 416 if ARCH_SUNXI 1279 default 392 if ARCH_U8500 1280 default 352 if ARCH_VT8500 1281 default 288 if ARCH_ROCKCHIP 1282 default 264 if MACH_H4700 1283 default 0 1284 help 1285 Maximum number of GPIOs in the system. 1286 1287 If unsure, leave the default value. 1288 1289config HZ_FIXED 1290 int 1291 default 128 if SOC_AT91RM9200 1292 default 0 1293 1294choice 1295 depends on HZ_FIXED = 0 1296 prompt "Timer frequency" 1297 1298config HZ_100 1299 bool "100 Hz" 1300 1301config HZ_200 1302 bool "200 Hz" 1303 1304config HZ_250 1305 bool "250 Hz" 1306 1307config HZ_300 1308 bool "300 Hz" 1309 1310config HZ_500 1311 bool "500 Hz" 1312 1313config HZ_1000 1314 bool "1000 Hz" 1315 1316endchoice 1317 1318config HZ 1319 int 1320 default HZ_FIXED if HZ_FIXED != 0 1321 default 100 if HZ_100 1322 default 200 if HZ_200 1323 default 250 if HZ_250 1324 default 300 if HZ_300 1325 default 500 if HZ_500 1326 default 1000 1327 1328config SCHED_HRTICK 1329 def_bool HIGH_RES_TIMERS 1330 1331config THUMB2_KERNEL 1332 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1333 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1334 default y if CPU_THUMBONLY 1335 select ARM_UNWIND 1336 help 1337 By enabling this option, the kernel will be compiled in 1338 Thumb-2 mode. 1339 1340 If unsure, say N. 1341 1342config ARM_PATCH_IDIV 1343 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1344 depends on CPU_32v7 && !XIP_KERNEL 1345 default y 1346 help 1347 The ARM compiler inserts calls to __aeabi_idiv() and 1348 __aeabi_uidiv() when it needs to perform division on signed 1349 and unsigned integers. Some v7 CPUs have support for the sdiv 1350 and udiv instructions that can be used to implement those 1351 functions. 1352 1353 Enabling this option allows the kernel to modify itself to 1354 replace the first two instructions of these library functions 1355 with the sdiv or udiv plus "bx lr" instructions when the CPU 1356 it is running on supports them. Typically this will be faster 1357 and less power intensive than running the original library 1358 code to do integer division. 1359 1360config AEABI 1361 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1362 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1363 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1364 help 1365 This option allows for the kernel to be compiled using the latest 1366 ARM ABI (aka EABI). This is only useful if you are using a user 1367 space environment that is also compiled with EABI. 1368 1369 Since there are major incompatibilities between the legacy ABI and 1370 EABI, especially with regard to structure member alignment, this 1371 option also changes the kernel syscall calling convention to 1372 disambiguate both ABIs and allow for backward compatibility support 1373 (selected with CONFIG_OABI_COMPAT). 1374 1375 To use this you need GCC version 4.0.0 or later. 1376 1377config OABI_COMPAT 1378 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1379 depends on AEABI && !THUMB2_KERNEL 1380 help 1381 This option preserves the old syscall interface along with the 1382 new (ARM EABI) one. It also provides a compatibility layer to 1383 intercept syscalls that have structure arguments which layout 1384 in memory differs between the legacy ABI and the new ARM EABI 1385 (only for non "thumb" binaries). This option adds a tiny 1386 overhead to all syscalls and produces a slightly larger kernel. 1387 1388 The seccomp filter system will not be available when this is 1389 selected, since there is no way yet to sensibly distinguish 1390 between calling conventions during filtering. 1391 1392 If you know you'll be using only pure EABI user space then you 1393 can say N here. If this option is not selected and you attempt 1394 to execute a legacy ABI binary then the result will be 1395 UNPREDICTABLE (in fact it can be predicted that it won't work 1396 at all). If in doubt say N. 1397 1398config ARCH_SELECT_MEMORY_MODEL 1399 bool 1400 1401config ARCH_FLATMEM_ENABLE 1402 bool 1403 1404config ARCH_SPARSEMEM_ENABLE 1405 bool 1406 select SPARSEMEM_STATIC if SPARSEMEM 1407 1408config HIGHMEM 1409 bool "High Memory Support" 1410 depends on MMU 1411 select KMAP_LOCAL 1412 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1413 help 1414 The address space of ARM processors is only 4 Gigabytes large 1415 and it has to accommodate user address space, kernel address 1416 space as well as some memory mapped IO. That means that, if you 1417 have a large amount of physical memory and/or IO, not all of the 1418 memory can be "permanently mapped" by the kernel. The physical 1419 memory that is not permanently mapped is called "high memory". 1420 1421 Depending on the selected kernel/user memory split, minimum 1422 vmalloc space and actual amount of RAM, you may not need this 1423 option which should result in a slightly faster kernel. 1424 1425 If unsure, say n. 1426 1427config HIGHPTE 1428 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1429 depends on HIGHMEM 1430 default y 1431 help 1432 The VM uses one page of physical memory for each page table. 1433 For systems with a lot of processes, this can use a lot of 1434 precious low memory, eventually leading to low memory being 1435 consumed by page tables. Setting this option will allow 1436 user-space 2nd level page tables to reside in high memory. 1437 1438config CPU_SW_DOMAIN_PAN 1439 bool "Enable use of CPU domains to implement privileged no-access" 1440 depends on MMU && !ARM_LPAE 1441 default y 1442 help 1443 Increase kernel security by ensuring that normal kernel accesses 1444 are unable to access userspace addresses. This can help prevent 1445 use-after-free bugs becoming an exploitable privilege escalation 1446 by ensuring that magic values (such as LIST_POISON) will always 1447 fault when dereferenced. 1448 1449 CPUs with low-vector mappings use a best-efforts implementation. 1450 Their lower 1MB needs to remain accessible for the vectors, but 1451 the remainder of userspace will become appropriately inaccessible. 1452 1453config HW_PERF_EVENTS 1454 def_bool y 1455 depends on ARM_PMU 1456 1457config ARM_MODULE_PLTS 1458 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1459 depends on MODULES 1460 default y 1461 help 1462 Allocate PLTs when loading modules so that jumps and calls whose 1463 targets are too far away for their relative offsets to be encoded 1464 in the instructions themselves can be bounced via veneers in the 1465 module's PLT. This allows modules to be allocated in the generic 1466 vmalloc area after the dedicated module memory area has been 1467 exhausted. The modules will use slightly more memory, but after 1468 rounding up to page size, the actual memory footprint is usually 1469 the same. 1470 1471 Disabling this is usually safe for small single-platform 1472 configurations. If unsure, say y. 1473 1474config FORCE_MAX_ZONEORDER 1475 int "Maximum zone order" 1476 default "12" if SOC_AM33XX 1477 default "9" if SA1111 1478 default "11" 1479 help 1480 The kernel memory allocator divides physically contiguous memory 1481 blocks into "zones", where each zone is a power of two number of 1482 pages. This option selects the largest power of two that the kernel 1483 keeps in the memory allocator. If you need to allocate very large 1484 blocks of physically contiguous memory, then you may need to 1485 increase this value. 1486 1487 This config option is actually maximum order plus one. For example, 1488 a value of 11 means that the largest free memory block is 2^10 pages. 1489 1490config ALIGNMENT_TRAP 1491 def_bool CPU_CP15_MMU 1492 select HAVE_PROC_CPU if PROC_FS 1493 help 1494 ARM processors cannot fetch/store information which is not 1495 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1496 address divisible by 4. On 32-bit ARM processors, these non-aligned 1497 fetch/store instructions will be emulated in software if you say 1498 here, which has a severe performance impact. This is necessary for 1499 correct operation of some network protocols. With an IP-only 1500 configuration it is safe to say N, otherwise say Y. 1501 1502config UACCESS_WITH_MEMCPY 1503 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1504 depends on MMU 1505 default y if CPU_FEROCEON 1506 help 1507 Implement faster copy_to_user and clear_user methods for CPU 1508 cores where a 8-word STM instruction give significantly higher 1509 memory write throughput than a sequence of individual 32bit stores. 1510 1511 A possible side effect is a slight increase in scheduling latency 1512 between threads sharing the same address space if they invoke 1513 such copy operations with large buffers. 1514 1515 However, if the CPU data cache is using a write-allocate mode, 1516 this option is unlikely to provide any performance gain. 1517 1518config PARAVIRT 1519 bool "Enable paravirtualization code" 1520 help 1521 This changes the kernel so it can modify itself when it is run 1522 under a hypervisor, potentially improving performance significantly 1523 over full virtualization. 1524 1525config PARAVIRT_TIME_ACCOUNTING 1526 bool "Paravirtual steal time accounting" 1527 select PARAVIRT 1528 help 1529 Select this option to enable fine granularity task steal time 1530 accounting. Time spent executing other tasks in parallel with 1531 the current vCPU is discounted from the vCPU power. To account for 1532 that, there can be a small performance impact. 1533 1534 If in doubt, say N here. 1535 1536config XEN_DOM0 1537 def_bool y 1538 depends on XEN 1539 1540config XEN 1541 bool "Xen guest support on ARM" 1542 depends on ARM && AEABI && OF 1543 depends on CPU_V7 && !CPU_V6 1544 depends on !GENERIC_ATOMIC64 1545 depends on MMU 1546 select ARCH_DMA_ADDR_T_64BIT 1547 select ARM_PSCI 1548 select SWIOTLB 1549 select SWIOTLB_XEN 1550 select PARAVIRT 1551 help 1552 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1553 1554config CC_HAVE_STACKPROTECTOR_TLS 1555 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1556 1557config STACKPROTECTOR_PER_TASK 1558 bool "Use a unique stack canary value for each task" 1559 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1560 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1561 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1562 default y 1563 help 1564 Due to the fact that GCC uses an ordinary symbol reference from 1565 which to load the value of the stack canary, this value can only 1566 change at reboot time on SMP systems, and all tasks running in the 1567 kernel's address space are forced to use the same canary value for 1568 the entire duration that the system is up. 1569 1570 Enable this option to switch to a different method that uses a 1571 different canary value for each task. 1572 1573endmenu 1574 1575menu "Boot options" 1576 1577config USE_OF 1578 bool "Flattened Device Tree support" 1579 select IRQ_DOMAIN 1580 select OF 1581 help 1582 Include support for flattened device tree machine descriptions. 1583 1584config ATAGS 1585 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1586 default y 1587 help 1588 This is the traditional way of passing data to the kernel at boot 1589 time. If you are solely relying on the flattened device tree (or 1590 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1591 to remove ATAGS support from your kernel binary. If unsure, 1592 leave this to y. 1593 1594config DEPRECATED_PARAM_STRUCT 1595 bool "Provide old way to pass kernel parameters" 1596 depends on ATAGS 1597 help 1598 This was deprecated in 2001 and announced to live on for 5 years. 1599 Some old boot loaders still use this way. 1600 1601# Compressed boot loader in ROM. Yes, we really want to ask about 1602# TEXT and BSS so we preserve their values in the config files. 1603config ZBOOT_ROM_TEXT 1604 hex "Compressed ROM boot loader base address" 1605 default 0x0 1606 help 1607 The physical address at which the ROM-able zImage is to be 1608 placed in the target. Platforms which normally make use of 1609 ROM-able zImage formats normally set this to a suitable 1610 value in their defconfig file. 1611 1612 If ZBOOT_ROM is not enabled, this has no effect. 1613 1614config ZBOOT_ROM_BSS 1615 hex "Compressed ROM boot loader BSS address" 1616 default 0x0 1617 help 1618 The base address of an area of read/write memory in the target 1619 for the ROM-able zImage which must be available while the 1620 decompressor is running. It must be large enough to hold the 1621 entire decompressed kernel plus an additional 128 KiB. 1622 Platforms which normally make use of ROM-able zImage formats 1623 normally set this to a suitable value in their defconfig file. 1624 1625 If ZBOOT_ROM is not enabled, this has no effect. 1626 1627config ZBOOT_ROM 1628 bool "Compressed boot loader in ROM/flash" 1629 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1630 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1631 help 1632 Say Y here if you intend to execute your compressed kernel image 1633 (zImage) directly from ROM or flash. If unsure, say N. 1634 1635config ARM_APPENDED_DTB 1636 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1637 depends on OF 1638 help 1639 With this option, the boot code will look for a device tree binary 1640 (DTB) appended to zImage 1641 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1642 1643 This is meant as a backward compatibility convenience for those 1644 systems with a bootloader that can't be upgraded to accommodate 1645 the documented boot protocol using a device tree. 1646 1647 Beware that there is very little in terms of protection against 1648 this option being confused by leftover garbage in memory that might 1649 look like a DTB header after a reboot if no actual DTB is appended 1650 to zImage. Do not leave this option active in a production kernel 1651 if you don't intend to always append a DTB. Proper passing of the 1652 location into r2 of a bootloader provided DTB is always preferable 1653 to this option. 1654 1655config ARM_ATAG_DTB_COMPAT 1656 bool "Supplement the appended DTB with traditional ATAG information" 1657 depends on ARM_APPENDED_DTB 1658 help 1659 Some old bootloaders can't be updated to a DTB capable one, yet 1660 they provide ATAGs with memory configuration, the ramdisk address, 1661 the kernel cmdline string, etc. Such information is dynamically 1662 provided by the bootloader and can't always be stored in a static 1663 DTB. To allow a device tree enabled kernel to be used with such 1664 bootloaders, this option allows zImage to extract the information 1665 from the ATAG list and store it at run time into the appended DTB. 1666 1667choice 1668 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1669 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1670 1671config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1672 bool "Use bootloader kernel arguments if available" 1673 help 1674 Uses the command-line options passed by the boot loader instead of 1675 the device tree bootargs property. If the boot loader doesn't provide 1676 any, the device tree bootargs property will be used. 1677 1678config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1679 bool "Extend with bootloader kernel arguments" 1680 help 1681 The command-line arguments provided by the boot loader will be 1682 appended to the the device tree bootargs property. 1683 1684endchoice 1685 1686config CMDLINE 1687 string "Default kernel command string" 1688 default "" 1689 help 1690 On some architectures (e.g. CATS), there is currently no way 1691 for the boot loader to pass arguments to the kernel. For these 1692 architectures, you should supply some command-line options at build 1693 time by entering them here. As a minimum, you should specify the 1694 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1695 1696choice 1697 prompt "Kernel command line type" if CMDLINE != "" 1698 default CMDLINE_FROM_BOOTLOADER 1699 depends on ATAGS 1700 1701config CMDLINE_FROM_BOOTLOADER 1702 bool "Use bootloader kernel arguments if available" 1703 help 1704 Uses the command-line options passed by the boot loader. If 1705 the boot loader doesn't provide any, the default kernel command 1706 string provided in CMDLINE will be used. 1707 1708config CMDLINE_EXTEND 1709 bool "Extend bootloader kernel arguments" 1710 help 1711 The command-line arguments provided by the boot loader will be 1712 appended to the default kernel command string. 1713 1714config CMDLINE_FORCE 1715 bool "Always use the default kernel command string" 1716 help 1717 Always use the default kernel command string, even if the boot 1718 loader passes other arguments to the kernel. 1719 This is useful if you cannot or don't want to change the 1720 command-line options your boot loader passes to the kernel. 1721endchoice 1722 1723config XIP_KERNEL 1724 bool "Kernel Execute-In-Place from ROM" 1725 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1726 help 1727 Execute-In-Place allows the kernel to run from non-volatile storage 1728 directly addressable by the CPU, such as NOR flash. This saves RAM 1729 space since the text section of the kernel is not loaded from flash 1730 to RAM. Read-write sections, such as the data section and stack, 1731 are still copied to RAM. The XIP kernel is not compressed since 1732 it has to run directly from flash, so it will take more space to 1733 store it. The flash address used to link the kernel object files, 1734 and for storing it, is configuration dependent. Therefore, if you 1735 say Y here, you must know the proper physical address where to 1736 store the kernel image depending on your own flash memory usage. 1737 1738 Also note that the make target becomes "make xipImage" rather than 1739 "make zImage" or "make Image". The final kernel binary to put in 1740 ROM memory will be arch/arm/boot/xipImage. 1741 1742 If unsure, say N. 1743 1744config XIP_PHYS_ADDR 1745 hex "XIP Kernel Physical Location" 1746 depends on XIP_KERNEL 1747 default "0x00080000" 1748 help 1749 This is the physical address in your flash memory the kernel will 1750 be linked for and stored to. This address is dependent on your 1751 own flash usage. 1752 1753config XIP_DEFLATED_DATA 1754 bool "Store kernel .data section compressed in ROM" 1755 depends on XIP_KERNEL 1756 select ZLIB_INFLATE 1757 help 1758 Before the kernel is actually executed, its .data section has to be 1759 copied to RAM from ROM. This option allows for storing that data 1760 in compressed form and decompressed to RAM rather than merely being 1761 copied, saving some precious ROM space. A possible drawback is a 1762 slightly longer boot delay. 1763 1764config KEXEC 1765 bool "Kexec system call (EXPERIMENTAL)" 1766 depends on (!SMP || PM_SLEEP_SMP) 1767 depends on MMU 1768 select KEXEC_CORE 1769 help 1770 kexec is a system call that implements the ability to shutdown your 1771 current kernel, and to start another kernel. It is like a reboot 1772 but it is independent of the system firmware. And like a reboot 1773 you can start any kernel with it, not just Linux. 1774 1775 It is an ongoing process to be certain the hardware in a machine 1776 is properly shutdown, so do not be surprised if this code does not 1777 initially work for you. 1778 1779config ATAGS_PROC 1780 bool "Export atags in procfs" 1781 depends on ATAGS && KEXEC 1782 default y 1783 help 1784 Should the atags used to boot the kernel be exported in an "atags" 1785 file in procfs. Useful with kexec. 1786 1787config CRASH_DUMP 1788 bool "Build kdump crash kernel (EXPERIMENTAL)" 1789 help 1790 Generate crash dump after being started by kexec. This should 1791 be normally only set in special crash dump kernels which are 1792 loaded in the main kernel with kexec-tools into a specially 1793 reserved region and then later executed after a crash by 1794 kdump/kexec. The crash dump kernel must be compiled to a 1795 memory address not used by the main kernel 1796 1797 For more details see Documentation/admin-guide/kdump/kdump.rst 1798 1799config AUTO_ZRELADDR 1800 bool "Auto calculation of the decompressed kernel image address" 1801 help 1802 ZRELADDR is the physical address where the decompressed kernel 1803 image will be placed. If AUTO_ZRELADDR is selected, the address 1804 will be determined at run-time, either by masking the current IP 1805 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1806 This assumes the zImage being placed in the first 128MB from 1807 start of memory. 1808 1809config EFI_STUB 1810 bool 1811 1812config EFI 1813 bool "UEFI runtime support" 1814 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1815 select UCS2_STRING 1816 select EFI_PARAMS_FROM_FDT 1817 select EFI_STUB 1818 select EFI_GENERIC_STUB 1819 select EFI_RUNTIME_WRAPPERS 1820 help 1821 This option provides support for runtime services provided 1822 by UEFI firmware (such as non-volatile variables, realtime 1823 clock, and platform reset). A UEFI stub is also provided to 1824 allow the kernel to be booted as an EFI application. This 1825 is only useful for kernels that may run on systems that have 1826 UEFI firmware. 1827 1828config DMI 1829 bool "Enable support for SMBIOS (DMI) tables" 1830 depends on EFI 1831 default y 1832 help 1833 This enables SMBIOS/DMI feature for systems. 1834 1835 This option is only useful on systems that have UEFI firmware. 1836 However, even with this option, the resultant kernel should 1837 continue to boot on existing non-UEFI platforms. 1838 1839 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1840 i.e., the the practice of identifying the platform via DMI to 1841 decide whether certain workarounds for buggy hardware and/or 1842 firmware need to be enabled. This would require the DMI subsystem 1843 to be enabled much earlier than we do on ARM, which is non-trivial. 1844 1845endmenu 1846 1847menu "CPU Power Management" 1848 1849source "drivers/cpufreq/Kconfig" 1850 1851source "drivers/cpuidle/Kconfig" 1852 1853endmenu 1854 1855menu "Floating point emulation" 1856 1857comment "At least one emulation must be selected" 1858 1859config FPE_NWFPE 1860 bool "NWFPE math emulation" 1861 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1862 help 1863 Say Y to include the NWFPE floating point emulator in the kernel. 1864 This is necessary to run most binaries. Linux does not currently 1865 support floating point hardware so you need to say Y here even if 1866 your machine has an FPA or floating point co-processor podule. 1867 1868 You may say N here if you are going to load the Acorn FPEmulator 1869 early in the bootup. 1870 1871config FPE_NWFPE_XP 1872 bool "Support extended precision" 1873 depends on FPE_NWFPE 1874 help 1875 Say Y to include 80-bit support in the kernel floating-point 1876 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1877 Note that gcc does not generate 80-bit operations by default, 1878 so in most cases this option only enlarges the size of the 1879 floating point emulator without any good reason. 1880 1881 You almost surely want to say N here. 1882 1883config FPE_FASTFPE 1884 bool "FastFPE math emulation (EXPERIMENTAL)" 1885 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1886 help 1887 Say Y here to include the FAST floating point emulator in the kernel. 1888 This is an experimental much faster emulator which now also has full 1889 precision for the mantissa. It does not support any exceptions. 1890 It is very simple, and approximately 3-6 times faster than NWFPE. 1891 1892 It should be sufficient for most programs. It may be not suitable 1893 for scientific calculations, but you have to check this for yourself. 1894 If you do not feel you need a faster FP emulation you should better 1895 choose NWFPE. 1896 1897config VFP 1898 bool "VFP-format floating point maths" 1899 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1900 help 1901 Say Y to include VFP support code in the kernel. This is needed 1902 if your hardware includes a VFP unit. 1903 1904 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1905 release notes and additional status information. 1906 1907 Say N if your target does not have VFP hardware. 1908 1909config VFPv3 1910 bool 1911 depends on VFP 1912 default y if CPU_V7 1913 1914config NEON 1915 bool "Advanced SIMD (NEON) Extension support" 1916 depends on VFPv3 && CPU_V7 1917 help 1918 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1919 Extension. 1920 1921config KERNEL_MODE_NEON 1922 bool "Support for NEON in kernel mode" 1923 depends on NEON && AEABI 1924 help 1925 Say Y to include support for NEON in kernel mode. 1926 1927endmenu 1928 1929menu "Power management options" 1930 1931source "kernel/power/Kconfig" 1932 1933config ARCH_SUSPEND_POSSIBLE 1934 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1935 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1936 def_bool y 1937 1938config ARM_CPU_SUSPEND 1939 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1940 depends on ARCH_SUSPEND_POSSIBLE 1941 1942config ARCH_HIBERNATION_POSSIBLE 1943 bool 1944 depends on MMU 1945 default y if ARCH_SUSPEND_POSSIBLE 1946 1947endmenu 1948 1949if CRYPTO 1950source "arch/arm/crypto/Kconfig" 1951endif 1952 1953source "arch/arm/Kconfig.assembler" 1954