1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_DEVMEM_IS_ALLOWED 6 select ARCH_HAS_ELF_RANDOMIZE 7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 8 select ARCH_HAVE_CUSTOM_GPIO_H 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_MIGHT_HAVE_PC_PARPORT 11 select ARCH_SUPPORTS_ATOMIC_RMW 12 select ARCH_USE_BUILTIN_BSWAP 13 select ARCH_USE_CMPXCHG_LOCKREF 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_EXTABLE_SORT if MMU 16 select CLONE_BACKWARDS 17 select CPU_PM if (SUSPEND || CPU_IDLE) 18 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 19 select EDAC_SUPPORT 20 select EDAC_ATOMIC_SCRUB 21 select GENERIC_ALLOCATOR 22 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 23 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 24 select GENERIC_EARLY_IOREMAP 25 select GENERIC_IDLE_POLL_SETUP 26 select GENERIC_IRQ_PROBE 27 select GENERIC_IRQ_SHOW 28 select GENERIC_IRQ_SHOW_LEVEL 29 select GENERIC_PCI_IOMAP 30 select GENERIC_SCHED_CLOCK 31 select GENERIC_SMP_IDLE_THREAD 32 select GENERIC_STRNCPY_FROM_USER 33 select GENERIC_STRNLEN_USER 34 select HANDLE_DOMAIN_IRQ 35 select HARDIRQS_SW_RESEND 36 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 37 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 38 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 39 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 40 select HAVE_ARCH_MMAP_RND_BITS if MMU 41 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 42 select HAVE_ARCH_TRACEHOOK 43 select HAVE_ARM_SMCCC if CPU_V7 44 select HAVE_BPF_JIT 45 select HAVE_CC_STACKPROTECTOR 46 select HAVE_CONTEXT_TRACKING 47 select HAVE_C_RECORDMCOUNT 48 select HAVE_DEBUG_KMEMLEAK 49 select HAVE_DMA_API_DEBUG 50 select HAVE_DMA_CONTIGUOUS if MMU 51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 56 select HAVE_GENERIC_DMA_COHERENT 57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 58 select HAVE_IDE if PCI || ISA || PCMCIA 59 select HAVE_IRQ_TIME_ACCOUNTING 60 select HAVE_KERNEL_GZIP 61 select HAVE_KERNEL_LZ4 62 select HAVE_KERNEL_LZMA 63 select HAVE_KERNEL_LZO 64 select HAVE_KERNEL_XZ 65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 66 select HAVE_KRETPROBES if (HAVE_KPROBES) 67 select HAVE_MEMBLOCK 68 select HAVE_MOD_ARCH_SPECIFIC 69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 70 select HAVE_OPTPROBES if !THUMB2_KERNEL 71 select HAVE_PERF_EVENTS 72 select HAVE_PERF_REGS 73 select HAVE_PERF_USER_STACK_DUMP 74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 75 select HAVE_REGS_AND_STACK_ACCESS_API 76 select HAVE_SYSCALL_TRACEPOINTS 77 select HAVE_UID16 78 select HAVE_VIRT_CPU_ACCOUNTING_GEN 79 select IRQ_FORCED_THREADING 80 select MODULES_USE_ELF_REL 81 select NO_BOOTMEM 82 select OF_EARLY_FLATTREE if OF 83 select OF_RESERVED_MEM if OF 84 select OLD_SIGACTION 85 select OLD_SIGSUSPEND3 86 select PERF_USE_VMALLOC 87 select RTC_LIB 88 select SYS_SUPPORTS_APM_EMULATION 89 # Above selects are sorted alphabetically; please add new ones 90 # according to that. Thanks. 91 help 92 The ARM series is a line of low-power-consumption RISC chip designs 93 licensed by ARM Ltd and targeted at embedded applications and 94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 95 manufactured, but legacy ARM-based PC hardware remains popular in 96 Europe. There is an ARM Linux project with a web page at 97 <http://www.arm.linux.org.uk/>. 98 99config ARM_HAS_SG_CHAIN 100 select ARCH_HAS_SG_CHAIN 101 bool 102 103config NEED_SG_DMA_LENGTH 104 bool 105 106config ARM_DMA_USE_IOMMU 107 bool 108 select ARM_HAS_SG_CHAIN 109 select NEED_SG_DMA_LENGTH 110 111if ARM_DMA_USE_IOMMU 112 113config ARM_DMA_IOMMU_ALIGNMENT 114 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 115 range 4 9 116 default 8 117 help 118 DMA mapping framework by default aligns all buffers to the smallest 119 PAGE_SIZE order which is greater than or equal to the requested buffer 120 size. This works well for buffers up to a few hundreds kilobytes, but 121 for larger buffers it just a waste of address space. Drivers which has 122 relatively small addressing window (like 64Mib) might run out of 123 virtual space with just a few allocations. 124 125 With this parameter you can specify the maximum PAGE_SIZE order for 126 DMA IOMMU buffers. Larger buffers will be aligned only to this 127 specified order. The order is expressed as a power of two multiplied 128 by the PAGE_SIZE. 129 130endif 131 132config MIGHT_HAVE_PCI 133 bool 134 135config SYS_SUPPORTS_APM_EMULATION 136 bool 137 138config HAVE_TCM 139 bool 140 select GENERIC_ALLOCATOR 141 142config HAVE_PROC_CPU 143 bool 144 145config NO_IOPORT_MAP 146 bool 147 148config EISA 149 bool 150 ---help--- 151 The Extended Industry Standard Architecture (EISA) bus was 152 developed as an open alternative to the IBM MicroChannel bus. 153 154 The EISA bus provided some of the features of the IBM MicroChannel 155 bus while maintaining backward compatibility with cards made for 156 the older ISA bus. The EISA bus saw limited use between 1988 and 157 1995 when it was made obsolete by the PCI bus. 158 159 Say Y here if you are building a kernel for an EISA-based machine. 160 161 Otherwise, say N. 162 163config SBUS 164 bool 165 166config STACKTRACE_SUPPORT 167 bool 168 default y 169 170config LOCKDEP_SUPPORT 171 bool 172 default y 173 174config TRACE_IRQFLAGS_SUPPORT 175 bool 176 default !CPU_V7M 177 178config RWSEM_XCHGADD_ALGORITHM 179 bool 180 default y 181 182config ARCH_HAS_ILOG2_U32 183 bool 184 185config ARCH_HAS_ILOG2_U64 186 bool 187 188config ARCH_HAS_BANDGAP 189 bool 190 191config FIX_EARLYCON_MEM 192 def_bool y if MMU 193 194config GENERIC_HWEIGHT 195 bool 196 default y 197 198config GENERIC_CALIBRATE_DELAY 199 bool 200 default y 201 202config ARCH_MAY_HAVE_PC_FDC 203 bool 204 205config ZONE_DMA 206 bool 207 208config NEED_DMA_MAP_STATE 209 def_bool y 210 211config ARCH_SUPPORTS_UPROBES 212 def_bool y 213 214config ARCH_HAS_DMA_SET_COHERENT_MASK 215 bool 216 217config GENERIC_ISA_DMA 218 bool 219 220config FIQ 221 bool 222 223config NEED_RET_TO_USER 224 bool 225 226config ARCH_MTD_XIP 227 bool 228 229config VECTORS_BASE 230 hex 231 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 232 default DRAM_BASE if REMAP_VECTORS_TO_RAM 233 default 0x00000000 234 help 235 The base address of exception vectors. This must be two pages 236 in size. 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 help 243 Patch phys-to-virt and virt-to-phys translation functions at 244 boot and module load time according to the position of the 245 kernel in system memory. 246 247 This can only be used with non-XIP MMU kernels where the base 248 of physical memory is at a 16MB boundary. 249 250 Only disable this option if you know that you do not require 251 this feature (eg, building a kernel for a single machine) and 252 you need to shrink the kernel to the minimal size. 253 254config NEED_MACH_IO_H 255 bool 256 help 257 Select this when mach/io.h is required to provide special 258 definitions for this platform. The need for mach/io.h should 259 be avoided when possible. 260 261config NEED_MACH_MEMORY_H 262 bool 263 help 264 Select this when mach/memory.h is required to provide special 265 definitions for this platform. The need for mach/memory.h should 266 be avoided when possible. 267 268config PHYS_OFFSET 269 hex "Physical address of main memory" if MMU 270 depends on !ARM_PATCH_PHYS_VIRT 271 default DRAM_BASE if !MMU 272 default 0x00000000 if ARCH_EBSA110 || \ 273 ARCH_FOOTBRIDGE || \ 274 ARCH_INTEGRATOR || \ 275 ARCH_IOP13XX || \ 276 ARCH_KS8695 || \ 277 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 278 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 279 default 0x20000000 if ARCH_S5PV210 280 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 281 default 0xc0000000 if ARCH_SA1100 282 help 283 Please provide the physical address corresponding to the 284 location of main memory in your system. 285 286config GENERIC_BUG 287 def_bool y 288 depends on BUG 289 290config PGTABLE_LEVELS 291 int 292 default 3 if ARM_LPAE 293 default 2 294 295source "init/Kconfig" 296 297source "kernel/Kconfig.freezer" 298 299menu "System Type" 300 301config MMU 302 bool "MMU-based Paged Memory Management Support" 303 default y 304 help 305 Select if you want MMU-based virtualised addressing space 306 support by paged memory management. If unsure, say 'Y'. 307 308config ARCH_MMAP_RND_BITS_MIN 309 default 8 310 311config ARCH_MMAP_RND_BITS_MAX 312 default 14 if PAGE_OFFSET=0x40000000 313 default 15 if PAGE_OFFSET=0x80000000 314 default 16 315 316# 317# The "ARM system type" choice list is ordered alphabetically by option 318# text. Please add new entries in the option alphabetic order. 319# 320choice 321 prompt "ARM system type" 322 default ARM_SINGLE_ARMV7M if !MMU 323 default ARCH_MULTIPLATFORM if MMU 324 325config ARCH_MULTIPLATFORM 326 bool "Allow multiple platforms to be selected" 327 depends on MMU 328 select ARCH_WANT_OPTIONAL_GPIOLIB 329 select ARM_HAS_SG_CHAIN 330 select ARM_PATCH_PHYS_VIRT 331 select AUTO_ZRELADDR 332 select CLKSRC_OF 333 select COMMON_CLK 334 select GENERIC_CLOCKEVENTS 335 select MIGHT_HAVE_PCI 336 select MULTI_IRQ_HANDLER 337 select SPARSE_IRQ 338 select USE_OF 339 340config ARM_SINGLE_ARMV7M 341 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 342 depends on !MMU 343 select ARCH_WANT_OPTIONAL_GPIOLIB 344 select ARM_NVIC 345 select AUTO_ZRELADDR 346 select CLKSRC_OF 347 select COMMON_CLK 348 select CPU_V7M 349 select GENERIC_CLOCKEVENTS 350 select NO_IOPORT_MAP 351 select SPARSE_IRQ 352 select USE_OF 353 354 355config ARCH_CLPS711X 356 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 357 select ARCH_REQUIRE_GPIOLIB 358 select AUTO_ZRELADDR 359 select CLKSRC_MMIO 360 select COMMON_CLK 361 select CPU_ARM720T 362 select GENERIC_CLOCKEVENTS 363 select MFD_SYSCON 364 select SOC_BUS 365 help 366 Support for Cirrus Logic 711x/721x/731x based boards. 367 368config ARCH_GEMINI 369 bool "Cortina Systems Gemini" 370 select ARCH_REQUIRE_GPIOLIB 371 select CLKSRC_MMIO 372 select CPU_FA526 373 select GENERIC_CLOCKEVENTS 374 help 375 Support for the Cortina Systems Gemini family SoCs 376 377config ARCH_EBSA110 378 bool "EBSA-110" 379 select ARCH_USES_GETTIMEOFFSET 380 select CPU_SA110 381 select ISA 382 select NEED_MACH_IO_H 383 select NEED_MACH_MEMORY_H 384 select NO_IOPORT_MAP 385 help 386 This is an evaluation board for the StrongARM processor available 387 from Digital. It has limited hardware on-board, including an 388 Ethernet interface, two PCMCIA sockets, two serial ports and a 389 parallel port. 390 391config ARCH_EP93XX 392 bool "EP93xx-based" 393 select ARCH_HAS_HOLES_MEMORYMODEL 394 select ARCH_REQUIRE_GPIOLIB 395 select ARM_AMBA 396 select ARM_PATCH_PHYS_VIRT 397 select ARM_VIC 398 select AUTO_ZRELADDR 399 select CLKDEV_LOOKUP 400 select CLKSRC_MMIO 401 select CPU_ARM920T 402 select GENERIC_CLOCKEVENTS 403 help 404 This enables support for the Cirrus EP93xx series of CPUs. 405 406config ARCH_FOOTBRIDGE 407 bool "FootBridge" 408 select CPU_SA110 409 select FOOTBRIDGE 410 select GENERIC_CLOCKEVENTS 411 select HAVE_IDE 412 select NEED_MACH_IO_H if !MMU 413 select NEED_MACH_MEMORY_H 414 help 415 Support for systems based on the DC21285 companion chip 416 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 417 418config ARCH_NETX 419 bool "Hilscher NetX based" 420 select ARM_VIC 421 select CLKSRC_MMIO 422 select CPU_ARM926T 423 select GENERIC_CLOCKEVENTS 424 help 425 This enables support for systems based on the Hilscher NetX Soc 426 427config ARCH_IOP13XX 428 bool "IOP13xx-based" 429 depends on MMU 430 select CPU_XSC3 431 select NEED_MACH_MEMORY_H 432 select NEED_RET_TO_USER 433 select PCI 434 select PLAT_IOP 435 select VMSPLIT_1G 436 select SPARSE_IRQ 437 help 438 Support for Intel's IOP13XX (XScale) family of processors. 439 440config ARCH_IOP32X 441 bool "IOP32x-based" 442 depends on MMU 443 select ARCH_REQUIRE_GPIOLIB 444 select CPU_XSCALE 445 select GPIO_IOP 446 select NEED_RET_TO_USER 447 select PCI 448 select PLAT_IOP 449 help 450 Support for Intel's 80219 and IOP32X (XScale) family of 451 processors. 452 453config ARCH_IOP33X 454 bool "IOP33x-based" 455 depends on MMU 456 select ARCH_REQUIRE_GPIOLIB 457 select CPU_XSCALE 458 select GPIO_IOP 459 select NEED_RET_TO_USER 460 select PCI 461 select PLAT_IOP 462 help 463 Support for Intel's IOP33X (XScale) family of processors. 464 465config ARCH_IXP4XX 466 bool "IXP4xx-based" 467 depends on MMU 468 select ARCH_HAS_DMA_SET_COHERENT_MASK 469 select ARCH_REQUIRE_GPIOLIB 470 select ARCH_SUPPORTS_BIG_ENDIAN 471 select CLKSRC_MMIO 472 select CPU_XSCALE 473 select DMABOUNCE if PCI 474 select GENERIC_CLOCKEVENTS 475 select MIGHT_HAVE_PCI 476 select NEED_MACH_IO_H 477 select USB_EHCI_BIG_ENDIAN_DESC 478 select USB_EHCI_BIG_ENDIAN_MMIO 479 help 480 Support for Intel's IXP4XX (XScale) family of processors. 481 482config ARCH_DOVE 483 bool "Marvell Dove" 484 select ARCH_REQUIRE_GPIOLIB 485 select CPU_PJ4 486 select GENERIC_CLOCKEVENTS 487 select MIGHT_HAVE_PCI 488 select MULTI_IRQ_HANDLER 489 select MVEBU_MBUS 490 select PINCTRL 491 select PINCTRL_DOVE 492 select PLAT_ORION_LEGACY 493 select SPARSE_IRQ 494 select PM_GENERIC_DOMAINS if PM 495 help 496 Support for the Marvell Dove SoC 88AP510 497 498config ARCH_KS8695 499 bool "Micrel/Kendin KS8695" 500 select ARCH_REQUIRE_GPIOLIB 501 select CLKSRC_MMIO 502 select CPU_ARM922T 503 select GENERIC_CLOCKEVENTS 504 select NEED_MACH_MEMORY_H 505 help 506 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 507 System-on-Chip devices. 508 509config ARCH_W90X900 510 bool "Nuvoton W90X900 CPU" 511 select ARCH_REQUIRE_GPIOLIB 512 select CLKDEV_LOOKUP 513 select CLKSRC_MMIO 514 select CPU_ARM926T 515 select GENERIC_CLOCKEVENTS 516 help 517 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 518 At present, the w90x900 has been renamed nuc900, regarding 519 the ARM series product line, you can login the following 520 link address to know more. 521 522 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 523 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 524 525config ARCH_LPC32XX 526 bool "NXP LPC32XX" 527 select ARCH_REQUIRE_GPIOLIB 528 select ARM_AMBA 529 select CLKDEV_LOOKUP 530 select CLKSRC_LPC32XX 531 select COMMON_CLK 532 select CPU_ARM926T 533 select GENERIC_CLOCKEVENTS 534 select USE_OF 535 help 536 Support for the NXP LPC32XX family of processors 537 538config ARCH_PXA 539 bool "PXA2xx/PXA3xx-based" 540 depends on MMU 541 select ARCH_MTD_XIP 542 select ARCH_REQUIRE_GPIOLIB 543 select ARM_CPU_SUSPEND if PM 544 select AUTO_ZRELADDR 545 select COMMON_CLK 546 select CLKDEV_LOOKUP 547 select CLKSRC_PXA 548 select CLKSRC_MMIO 549 select CLKSRC_OF 550 select CPU_XSCALE if !CPU_XSC3 551 select GENERIC_CLOCKEVENTS 552 select GPIO_PXA 553 select HAVE_IDE 554 select IRQ_DOMAIN 555 select MULTI_IRQ_HANDLER 556 select PLAT_PXA 557 select SPARSE_IRQ 558 help 559 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 560 561config ARCH_RPC 562 bool "RiscPC" 563 depends on MMU 564 select ARCH_ACORN 565 select ARCH_MAY_HAVE_PC_FDC 566 select ARCH_SPARSEMEM_ENABLE 567 select ARCH_USES_GETTIMEOFFSET 568 select CPU_SA110 569 select FIQ 570 select HAVE_IDE 571 select HAVE_PATA_PLATFORM 572 select ISA_DMA_API 573 select NEED_MACH_IO_H 574 select NEED_MACH_MEMORY_H 575 select NO_IOPORT_MAP 576 help 577 On the Acorn Risc-PC, Linux can support the internal IDE disk and 578 CD-ROM interface, serial and parallel port, and the floppy drive. 579 580config ARCH_SA1100 581 bool "SA1100-based" 582 select ARCH_MTD_XIP 583 select ARCH_REQUIRE_GPIOLIB 584 select ARCH_SPARSEMEM_ENABLE 585 select CLKDEV_LOOKUP 586 select CLKSRC_MMIO 587 select CLKSRC_PXA 588 select CLKSRC_OF if OF 589 select CPU_FREQ 590 select CPU_SA1100 591 select GENERIC_CLOCKEVENTS 592 select HAVE_IDE 593 select IRQ_DOMAIN 594 select ISA 595 select MULTI_IRQ_HANDLER 596 select NEED_MACH_MEMORY_H 597 select SPARSE_IRQ 598 help 599 Support for StrongARM 11x0 based boards. 600 601config ARCH_S3C24XX 602 bool "Samsung S3C24XX SoCs" 603 select ARCH_REQUIRE_GPIOLIB 604 select ATAGS 605 select CLKDEV_LOOKUP 606 select CLKSRC_SAMSUNG_PWM 607 select GENERIC_CLOCKEVENTS 608 select GPIO_SAMSUNG 609 select HAVE_S3C2410_I2C if I2C 610 select HAVE_S3C2410_WATCHDOG if WATCHDOG 611 select HAVE_S3C_RTC if RTC_CLASS 612 select MULTI_IRQ_HANDLER 613 select NEED_MACH_IO_H 614 select SAMSUNG_ATAGS 615 help 616 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 617 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 618 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 619 Samsung SMDK2410 development board (and derivatives). 620 621config ARCH_DAVINCI 622 bool "TI DaVinci" 623 select ARCH_HAS_HOLES_MEMORYMODEL 624 select ARCH_REQUIRE_GPIOLIB 625 select CLKDEV_LOOKUP 626 select CPU_ARM926T 627 select GENERIC_ALLOCATOR 628 select GENERIC_CLOCKEVENTS 629 select GENERIC_IRQ_CHIP 630 select HAVE_IDE 631 select USE_OF 632 select ZONE_DMA 633 help 634 Support for TI's DaVinci platform. 635 636config ARCH_OMAP1 637 bool "TI OMAP1" 638 depends on MMU 639 select ARCH_HAS_HOLES_MEMORYMODEL 640 select ARCH_OMAP 641 select ARCH_REQUIRE_GPIOLIB 642 select CLKDEV_LOOKUP 643 select CLKSRC_MMIO 644 select GENERIC_CLOCKEVENTS 645 select GENERIC_IRQ_CHIP 646 select HAVE_IDE 647 select IRQ_DOMAIN 648 select MULTI_IRQ_HANDLER 649 select NEED_MACH_IO_H if PCCARD 650 select NEED_MACH_MEMORY_H 651 select SPARSE_IRQ 652 help 653 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 654 655endchoice 656 657menu "Multiple platform selection" 658 depends on ARCH_MULTIPLATFORM 659 660comment "CPU Core family selection" 661 662config ARCH_MULTI_V4 663 bool "ARMv4 based platforms (FA526)" 664 depends on !ARCH_MULTI_V6_V7 665 select ARCH_MULTI_V4_V5 666 select CPU_FA526 667 668config ARCH_MULTI_V4T 669 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 670 depends on !ARCH_MULTI_V6_V7 671 select ARCH_MULTI_V4_V5 672 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 673 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 674 CPU_ARM925T || CPU_ARM940T) 675 676config ARCH_MULTI_V5 677 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 678 depends on !ARCH_MULTI_V6_V7 679 select ARCH_MULTI_V4_V5 680 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 681 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 682 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 683 684config ARCH_MULTI_V4_V5 685 bool 686 687config ARCH_MULTI_V6 688 bool "ARMv6 based platforms (ARM11)" 689 select ARCH_MULTI_V6_V7 690 select CPU_V6K 691 692config ARCH_MULTI_V7 693 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 694 default y 695 select ARCH_MULTI_V6_V7 696 select CPU_V7 697 select HAVE_SMP 698 699config ARCH_MULTI_V6_V7 700 bool 701 select MIGHT_HAVE_CACHE_L2X0 702 703config ARCH_MULTI_CPU_AUTO 704 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 705 select ARCH_MULTI_V5 706 707endmenu 708 709config ARCH_VIRT 710 bool "Dummy Virtual Machine" 711 depends on ARCH_MULTI_V7 712 select ARM_AMBA 713 select ARM_GIC 714 select ARM_GIC_V2M if PCI_MSI 715 select ARM_GIC_V3 716 select ARM_PSCI 717 select HAVE_ARM_ARCH_TIMER 718 719# 720# This is sorted alphabetically by mach-* pathname. However, plat-* 721# Kconfigs may be included either alphabetically (according to the 722# plat- suffix) or along side the corresponding mach-* source. 723# 724source "arch/arm/mach-mvebu/Kconfig" 725 726source "arch/arm/mach-alpine/Kconfig" 727 728source "arch/arm/mach-artpec/Kconfig" 729 730source "arch/arm/mach-asm9260/Kconfig" 731 732source "arch/arm/mach-at91/Kconfig" 733 734source "arch/arm/mach-axxia/Kconfig" 735 736source "arch/arm/mach-bcm/Kconfig" 737 738source "arch/arm/mach-berlin/Kconfig" 739 740source "arch/arm/mach-clps711x/Kconfig" 741 742source "arch/arm/mach-cns3xxx/Kconfig" 743 744source "arch/arm/mach-davinci/Kconfig" 745 746source "arch/arm/mach-digicolor/Kconfig" 747 748source "arch/arm/mach-dove/Kconfig" 749 750source "arch/arm/mach-ep93xx/Kconfig" 751 752source "arch/arm/mach-footbridge/Kconfig" 753 754source "arch/arm/mach-gemini/Kconfig" 755 756source "arch/arm/mach-highbank/Kconfig" 757 758source "arch/arm/mach-hisi/Kconfig" 759 760source "arch/arm/mach-integrator/Kconfig" 761 762source "arch/arm/mach-iop32x/Kconfig" 763 764source "arch/arm/mach-iop33x/Kconfig" 765 766source "arch/arm/mach-iop13xx/Kconfig" 767 768source "arch/arm/mach-ixp4xx/Kconfig" 769 770source "arch/arm/mach-keystone/Kconfig" 771 772source "arch/arm/mach-ks8695/Kconfig" 773 774source "arch/arm/mach-meson/Kconfig" 775 776source "arch/arm/mach-moxart/Kconfig" 777 778source "arch/arm/mach-mv78xx0/Kconfig" 779 780source "arch/arm/mach-imx/Kconfig" 781 782source "arch/arm/mach-mediatek/Kconfig" 783 784source "arch/arm/mach-mxs/Kconfig" 785 786source "arch/arm/mach-netx/Kconfig" 787 788source "arch/arm/mach-nomadik/Kconfig" 789 790source "arch/arm/mach-nspire/Kconfig" 791 792source "arch/arm/plat-omap/Kconfig" 793 794source "arch/arm/mach-omap1/Kconfig" 795 796source "arch/arm/mach-omap2/Kconfig" 797 798source "arch/arm/mach-orion5x/Kconfig" 799 800source "arch/arm/mach-picoxcell/Kconfig" 801 802source "arch/arm/mach-pxa/Kconfig" 803source "arch/arm/plat-pxa/Kconfig" 804 805source "arch/arm/mach-mmp/Kconfig" 806 807source "arch/arm/mach-qcom/Kconfig" 808 809source "arch/arm/mach-realview/Kconfig" 810 811source "arch/arm/mach-rockchip/Kconfig" 812 813source "arch/arm/mach-sa1100/Kconfig" 814 815source "arch/arm/mach-socfpga/Kconfig" 816 817source "arch/arm/mach-spear/Kconfig" 818 819source "arch/arm/mach-sti/Kconfig" 820 821source "arch/arm/mach-s3c24xx/Kconfig" 822 823source "arch/arm/mach-s3c64xx/Kconfig" 824 825source "arch/arm/mach-s5pv210/Kconfig" 826 827source "arch/arm/mach-exynos/Kconfig" 828source "arch/arm/plat-samsung/Kconfig" 829 830source "arch/arm/mach-shmobile/Kconfig" 831 832source "arch/arm/mach-sunxi/Kconfig" 833 834source "arch/arm/mach-prima2/Kconfig" 835 836source "arch/arm/mach-tango/Kconfig" 837 838source "arch/arm/mach-tegra/Kconfig" 839 840source "arch/arm/mach-u300/Kconfig" 841 842source "arch/arm/mach-uniphier/Kconfig" 843 844source "arch/arm/mach-ux500/Kconfig" 845 846source "arch/arm/mach-versatile/Kconfig" 847 848source "arch/arm/mach-vexpress/Kconfig" 849source "arch/arm/plat-versatile/Kconfig" 850 851source "arch/arm/mach-vt8500/Kconfig" 852 853source "arch/arm/mach-w90x900/Kconfig" 854 855source "arch/arm/mach-zx/Kconfig" 856 857source "arch/arm/mach-zynq/Kconfig" 858 859# ARMv7-M architecture 860config ARCH_EFM32 861 bool "Energy Micro efm32" 862 depends on ARM_SINGLE_ARMV7M 863 select ARCH_REQUIRE_GPIOLIB 864 help 865 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 866 processors. 867 868config ARCH_LPC18XX 869 bool "NXP LPC18xx/LPC43xx" 870 depends on ARM_SINGLE_ARMV7M 871 select ARCH_HAS_RESET_CONTROLLER 872 select ARM_AMBA 873 select CLKSRC_LPC32XX 874 select PINCTRL 875 help 876 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 877 high performance microcontrollers. 878 879config ARCH_STM32 880 bool "STMicrolectronics STM32" 881 depends on ARM_SINGLE_ARMV7M 882 select ARCH_HAS_RESET_CONTROLLER 883 select ARMV7M_SYSTICK 884 select CLKSRC_STM32 885 select PINCTRL 886 select RESET_CONTROLLER 887 help 888 Support for STMicroelectronics STM32 processors. 889 890config MACH_STM32F429 891 bool "STMicrolectronics STM32F429" 892 depends on ARCH_STM32 893 default y 894 895# Definitions to make life easier 896config ARCH_ACORN 897 bool 898 899config PLAT_IOP 900 bool 901 select GENERIC_CLOCKEVENTS 902 903config PLAT_ORION 904 bool 905 select CLKSRC_MMIO 906 select COMMON_CLK 907 select GENERIC_IRQ_CHIP 908 select IRQ_DOMAIN 909 910config PLAT_ORION_LEGACY 911 bool 912 select PLAT_ORION 913 914config PLAT_PXA 915 bool 916 917config PLAT_VERSATILE 918 bool 919 920source "arch/arm/firmware/Kconfig" 921 922source arch/arm/mm/Kconfig 923 924config IWMMXT 925 bool "Enable iWMMXt support" 926 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 927 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 928 help 929 Enable support for iWMMXt context switching at run time if 930 running on a CPU that supports it. 931 932config MULTI_IRQ_HANDLER 933 bool 934 help 935 Allow each machine to specify it's own IRQ handler at run time. 936 937if !MMU 938source "arch/arm/Kconfig-nommu" 939endif 940 941config PJ4B_ERRATA_4742 942 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 943 depends on CPU_PJ4B && MACH_ARMADA_370 944 default y 945 help 946 When coming out of either a Wait for Interrupt (WFI) or a Wait for 947 Event (WFE) IDLE states, a specific timing sensitivity exists between 948 the retiring WFI/WFE instructions and the newly issued subsequent 949 instructions. This sensitivity can result in a CPU hang scenario. 950 Workaround: 951 The software must insert either a Data Synchronization Barrier (DSB) 952 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 953 instruction 954 955config ARM_ERRATA_326103 956 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 957 depends on CPU_V6 958 help 959 Executing a SWP instruction to read-only memory does not set bit 11 960 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 961 treat the access as a read, preventing a COW from occurring and 962 causing the faulting task to livelock. 963 964config ARM_ERRATA_411920 965 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 966 depends on CPU_V6 || CPU_V6K 967 help 968 Invalidation of the Instruction Cache operation can 969 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 970 It does not affect the MPCore. This option enables the ARM Ltd. 971 recommended workaround. 972 973config ARM_ERRATA_430973 974 bool "ARM errata: Stale prediction on replaced interworking branch" 975 depends on CPU_V7 976 help 977 This option enables the workaround for the 430973 Cortex-A8 978 r1p* erratum. If a code sequence containing an ARM/Thumb 979 interworking branch is replaced with another code sequence at the 980 same virtual address, whether due to self-modifying code or virtual 981 to physical address re-mapping, Cortex-A8 does not recover from the 982 stale interworking branch prediction. This results in Cortex-A8 983 executing the new code sequence in the incorrect ARM or Thumb state. 984 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 985 and also flushes the branch target cache at every context switch. 986 Note that setting specific bits in the ACTLR register may not be 987 available in non-secure mode. 988 989config ARM_ERRATA_458693 990 bool "ARM errata: Processor deadlock when a false hazard is created" 991 depends on CPU_V7 992 depends on !ARCH_MULTIPLATFORM 993 help 994 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 995 erratum. For very specific sequences of memory operations, it is 996 possible for a hazard condition intended for a cache line to instead 997 be incorrectly associated with a different cache line. This false 998 hazard might then cause a processor deadlock. The workaround enables 999 the L1 caching of the NEON accesses and disables the PLD instruction 1000 in the ACTLR register. Note that setting specific bits in the ACTLR 1001 register may not be available in non-secure mode. 1002 1003config ARM_ERRATA_460075 1004 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1005 depends on CPU_V7 1006 depends on !ARCH_MULTIPLATFORM 1007 help 1008 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1009 erratum. Any asynchronous access to the L2 cache may encounter a 1010 situation in which recent store transactions to the L2 cache are lost 1011 and overwritten with stale memory contents from external memory. The 1012 workaround disables the write-allocate mode for the L2 cache via the 1013 ACTLR register. Note that setting specific bits in the ACTLR register 1014 may not be available in non-secure mode. 1015 1016config ARM_ERRATA_742230 1017 bool "ARM errata: DMB operation may be faulty" 1018 depends on CPU_V7 && SMP 1019 depends on !ARCH_MULTIPLATFORM 1020 help 1021 This option enables the workaround for the 742230 Cortex-A9 1022 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1023 between two write operations may not ensure the correct visibility 1024 ordering of the two writes. This workaround sets a specific bit in 1025 the diagnostic register of the Cortex-A9 which causes the DMB 1026 instruction to behave as a DSB, ensuring the correct behaviour of 1027 the two writes. 1028 1029config ARM_ERRATA_742231 1030 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1031 depends on CPU_V7 && SMP 1032 depends on !ARCH_MULTIPLATFORM 1033 help 1034 This option enables the workaround for the 742231 Cortex-A9 1035 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1036 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1037 accessing some data located in the same cache line, may get corrupted 1038 data due to bad handling of the address hazard when the line gets 1039 replaced from one of the CPUs at the same time as another CPU is 1040 accessing it. This workaround sets specific bits in the diagnostic 1041 register of the Cortex-A9 which reduces the linefill issuing 1042 capabilities of the processor. 1043 1044config ARM_ERRATA_643719 1045 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1046 depends on CPU_V7 && SMP 1047 default y 1048 help 1049 This option enables the workaround for the 643719 Cortex-A9 (prior to 1050 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1051 register returns zero when it should return one. The workaround 1052 corrects this value, ensuring cache maintenance operations which use 1053 it behave as intended and avoiding data corruption. 1054 1055config ARM_ERRATA_720789 1056 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1057 depends on CPU_V7 1058 help 1059 This option enables the workaround for the 720789 Cortex-A9 (prior to 1060 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1061 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1062 As a consequence of this erratum, some TLB entries which should be 1063 invalidated are not, resulting in an incoherency in the system page 1064 tables. The workaround changes the TLB flushing routines to invalidate 1065 entries regardless of the ASID. 1066 1067config ARM_ERRATA_743622 1068 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1069 depends on CPU_V7 1070 depends on !ARCH_MULTIPLATFORM 1071 help 1072 This option enables the workaround for the 743622 Cortex-A9 1073 (r2p*) erratum. Under very rare conditions, a faulty 1074 optimisation in the Cortex-A9 Store Buffer may lead to data 1075 corruption. This workaround sets a specific bit in the diagnostic 1076 register of the Cortex-A9 which disables the Store Buffer 1077 optimisation, preventing the defect from occurring. This has no 1078 visible impact on the overall performance or power consumption of the 1079 processor. 1080 1081config ARM_ERRATA_751472 1082 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1083 depends on CPU_V7 1084 depends on !ARCH_MULTIPLATFORM 1085 help 1086 This option enables the workaround for the 751472 Cortex-A9 (prior 1087 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1088 completion of a following broadcasted operation if the second 1089 operation is received by a CPU before the ICIALLUIS has completed, 1090 potentially leading to corrupted entries in the cache or TLB. 1091 1092config ARM_ERRATA_754322 1093 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1094 depends on CPU_V7 1095 help 1096 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1097 r3p*) erratum. A speculative memory access may cause a page table walk 1098 which starts prior to an ASID switch but completes afterwards. This 1099 can populate the micro-TLB with a stale entry which may be hit with 1100 the new ASID. This workaround places two dsb instructions in the mm 1101 switching code so that no page table walks can cross the ASID switch. 1102 1103config ARM_ERRATA_754327 1104 bool "ARM errata: no automatic Store Buffer drain" 1105 depends on CPU_V7 && SMP 1106 help 1107 This option enables the workaround for the 754327 Cortex-A9 (prior to 1108 r2p0) erratum. The Store Buffer does not have any automatic draining 1109 mechanism and therefore a livelock may occur if an external agent 1110 continuously polls a memory location waiting to observe an update. 1111 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1112 written polling loops from denying visibility of updates to memory. 1113 1114config ARM_ERRATA_364296 1115 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1116 depends on CPU_V6 1117 help 1118 This options enables the workaround for the 364296 ARM1136 1119 r0p2 erratum (possible cache data corruption with 1120 hit-under-miss enabled). It sets the undocumented bit 31 in 1121 the auxiliary control register and the FI bit in the control 1122 register, thus disabling hit-under-miss without putting the 1123 processor into full low interrupt latency mode. ARM11MPCore 1124 is not affected. 1125 1126config ARM_ERRATA_764369 1127 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1128 depends on CPU_V7 && SMP 1129 help 1130 This option enables the workaround for erratum 764369 1131 affecting Cortex-A9 MPCore with two or more processors (all 1132 current revisions). Under certain timing circumstances, a data 1133 cache line maintenance operation by MVA targeting an Inner 1134 Shareable memory region may fail to proceed up to either the 1135 Point of Coherency or to the Point of Unification of the 1136 system. This workaround adds a DSB instruction before the 1137 relevant cache maintenance functions and sets a specific bit 1138 in the diagnostic control register of the SCU. 1139 1140config ARM_ERRATA_775420 1141 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1142 depends on CPU_V7 1143 help 1144 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1145 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1146 operation aborts with MMU exception, it might cause the processor 1147 to deadlock. This workaround puts DSB before executing ISB if 1148 an abort may occur on cache maintenance. 1149 1150config ARM_ERRATA_798181 1151 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1152 depends on CPU_V7 && SMP 1153 help 1154 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1155 adequately shooting down all use of the old entries. This 1156 option enables the Linux kernel workaround for this erratum 1157 which sends an IPI to the CPUs that are running the same ASID 1158 as the one being invalidated. 1159 1160config ARM_ERRATA_773022 1161 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1162 depends on CPU_V7 1163 help 1164 This option enables the workaround for the 773022 Cortex-A15 1165 (up to r0p4) erratum. In certain rare sequences of code, the 1166 loop buffer may deliver incorrect instructions. This 1167 workaround disables the loop buffer to avoid the erratum. 1168 1169endmenu 1170 1171source "arch/arm/common/Kconfig" 1172 1173menu "Bus support" 1174 1175config ISA 1176 bool 1177 help 1178 Find out whether you have ISA slots on your motherboard. ISA is the 1179 name of a bus system, i.e. the way the CPU talks to the other stuff 1180 inside your box. Other bus systems are PCI, EISA, MicroChannel 1181 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1182 newer boards don't support it. If you have ISA, say Y, otherwise N. 1183 1184# Select ISA DMA controller support 1185config ISA_DMA 1186 bool 1187 select ISA_DMA_API 1188 1189# Select ISA DMA interface 1190config ISA_DMA_API 1191 bool 1192 1193config PCI 1194 bool "PCI support" if MIGHT_HAVE_PCI 1195 help 1196 Find out whether you have a PCI motherboard. PCI is the name of a 1197 bus system, i.e. the way the CPU talks to the other stuff inside 1198 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1199 VESA. If you have PCI, say Y, otherwise N. 1200 1201config PCI_DOMAINS 1202 bool 1203 depends on PCI 1204 1205config PCI_DOMAINS_GENERIC 1206 def_bool PCI_DOMAINS 1207 1208config PCI_NANOENGINE 1209 bool "BSE nanoEngine PCI support" 1210 depends on SA1100_NANOENGINE 1211 help 1212 Enable PCI on the BSE nanoEngine board. 1213 1214config PCI_SYSCALL 1215 def_bool PCI 1216 1217config PCI_HOST_ITE8152 1218 bool 1219 depends on PCI && MACH_ARMCORE 1220 default y 1221 select DMABOUNCE 1222 1223source "drivers/pci/Kconfig" 1224 1225source "drivers/pcmcia/Kconfig" 1226 1227endmenu 1228 1229menu "Kernel Features" 1230 1231config HAVE_SMP 1232 bool 1233 help 1234 This option should be selected by machines which have an SMP- 1235 capable CPU. 1236 1237 The only effect of this option is to make the SMP-related 1238 options available to the user for configuration. 1239 1240config SMP 1241 bool "Symmetric Multi-Processing" 1242 depends on CPU_V6K || CPU_V7 1243 depends on GENERIC_CLOCKEVENTS 1244 depends on HAVE_SMP 1245 depends on MMU || ARM_MPU 1246 select IRQ_WORK 1247 help 1248 This enables support for systems with more than one CPU. If you have 1249 a system with only one CPU, say N. If you have a system with more 1250 than one CPU, say Y. 1251 1252 If you say N here, the kernel will run on uni- and multiprocessor 1253 machines, but will use only one CPU of a multiprocessor machine. If 1254 you say Y here, the kernel will run on many, but not all, 1255 uniprocessor machines. On a uniprocessor machine, the kernel 1256 will run faster if you say N here. 1257 1258 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1259 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1260 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1261 1262 If you don't know what to do here, say N. 1263 1264config SMP_ON_UP 1265 bool "Allow booting SMP kernel on uniprocessor systems" 1266 depends on SMP && !XIP_KERNEL && MMU 1267 default y 1268 help 1269 SMP kernels contain instructions which fail on non-SMP processors. 1270 Enabling this option allows the kernel to modify itself to make 1271 these instructions safe. Disabling it allows about 1K of space 1272 savings. 1273 1274 If you don't know what to do here, say Y. 1275 1276config ARM_CPU_TOPOLOGY 1277 bool "Support cpu topology definition" 1278 depends on SMP && CPU_V7 1279 default y 1280 help 1281 Support ARM cpu topology definition. The MPIDR register defines 1282 affinity between processors which is then used to describe the cpu 1283 topology of an ARM System. 1284 1285config SCHED_MC 1286 bool "Multi-core scheduler support" 1287 depends on ARM_CPU_TOPOLOGY 1288 help 1289 Multi-core scheduler support improves the CPU scheduler's decision 1290 making when dealing with multi-core CPU chips at a cost of slightly 1291 increased overhead in some places. If unsure say N here. 1292 1293config SCHED_SMT 1294 bool "SMT scheduler support" 1295 depends on ARM_CPU_TOPOLOGY 1296 help 1297 Improves the CPU scheduler's decision making when dealing with 1298 MultiThreading at a cost of slightly increased overhead in some 1299 places. If unsure say N here. 1300 1301config HAVE_ARM_SCU 1302 bool 1303 help 1304 This option enables support for the ARM system coherency unit 1305 1306config HAVE_ARM_ARCH_TIMER 1307 bool "Architected timer support" 1308 depends on CPU_V7 1309 select ARM_ARCH_TIMER 1310 select GENERIC_CLOCKEVENTS 1311 help 1312 This option enables support for the ARM architected timer 1313 1314config HAVE_ARM_TWD 1315 bool 1316 select CLKSRC_OF if OF 1317 help 1318 This options enables support for the ARM timer and watchdog unit 1319 1320config MCPM 1321 bool "Multi-Cluster Power Management" 1322 depends on CPU_V7 && SMP 1323 help 1324 This option provides the common power management infrastructure 1325 for (multi-)cluster based systems, such as big.LITTLE based 1326 systems. 1327 1328config MCPM_QUAD_CLUSTER 1329 bool 1330 depends on MCPM 1331 help 1332 To avoid wasting resources unnecessarily, MCPM only supports up 1333 to 2 clusters by default. 1334 Platforms with 3 or 4 clusters that use MCPM must select this 1335 option to allow the additional clusters to be managed. 1336 1337config BIG_LITTLE 1338 bool "big.LITTLE support (Experimental)" 1339 depends on CPU_V7 && SMP 1340 select MCPM 1341 help 1342 This option enables support selections for the big.LITTLE 1343 system architecture. 1344 1345config BL_SWITCHER 1346 bool "big.LITTLE switcher support" 1347 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1348 select CPU_PM 1349 help 1350 The big.LITTLE "switcher" provides the core functionality to 1351 transparently handle transition between a cluster of A15's 1352 and a cluster of A7's in a big.LITTLE system. 1353 1354config BL_SWITCHER_DUMMY_IF 1355 tristate "Simple big.LITTLE switcher user interface" 1356 depends on BL_SWITCHER && DEBUG_KERNEL 1357 help 1358 This is a simple and dummy char dev interface to control 1359 the big.LITTLE switcher core code. It is meant for 1360 debugging purposes only. 1361 1362choice 1363 prompt "Memory split" 1364 depends on MMU 1365 default VMSPLIT_3G 1366 help 1367 Select the desired split between kernel and user memory. 1368 1369 If you are not absolutely sure what you are doing, leave this 1370 option alone! 1371 1372 config VMSPLIT_3G 1373 bool "3G/1G user/kernel split" 1374 config VMSPLIT_3G_OPT 1375 bool "3G/1G user/kernel split (for full 1G low memory)" 1376 config VMSPLIT_2G 1377 bool "2G/2G user/kernel split" 1378 config VMSPLIT_1G 1379 bool "1G/3G user/kernel split" 1380endchoice 1381 1382config PAGE_OFFSET 1383 hex 1384 default PHYS_OFFSET if !MMU 1385 default 0x40000000 if VMSPLIT_1G 1386 default 0x80000000 if VMSPLIT_2G 1387 default 0xB0000000 if VMSPLIT_3G_OPT 1388 default 0xC0000000 1389 1390config NR_CPUS 1391 int "Maximum number of CPUs (2-32)" 1392 range 2 32 1393 depends on SMP 1394 default "4" 1395 1396config HOTPLUG_CPU 1397 bool "Support for hot-pluggable CPUs" 1398 depends on SMP 1399 help 1400 Say Y here to experiment with turning CPUs off and on. CPUs 1401 can be controlled through /sys/devices/system/cpu. 1402 1403config ARM_PSCI 1404 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1405 depends on HAVE_ARM_SMCCC 1406 select ARM_PSCI_FW 1407 help 1408 Say Y here if you want Linux to communicate with system firmware 1409 implementing the PSCI specification for CPU-centric power 1410 management operations described in ARM document number ARM DEN 1411 0022A ("Power State Coordination Interface System Software on 1412 ARM processors"). 1413 1414# The GPIO number here must be sorted by descending number. In case of 1415# a multiplatform kernel, we just want the highest value required by the 1416# selected platforms. 1417config ARCH_NR_GPIO 1418 int 1419 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1420 ARCH_ZYNQ 1421 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1422 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1423 default 416 if ARCH_SUNXI 1424 default 392 if ARCH_U8500 1425 default 352 if ARCH_VT8500 1426 default 288 if ARCH_ROCKCHIP 1427 default 264 if MACH_H4700 1428 default 0 1429 help 1430 Maximum number of GPIOs in the system. 1431 1432 If unsure, leave the default value. 1433 1434source kernel/Kconfig.preempt 1435 1436config HZ_FIXED 1437 int 1438 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1439 ARCH_S5PV210 || ARCH_EXYNOS4 1440 default 128 if SOC_AT91RM9200 1441 default 0 1442 1443choice 1444 depends on HZ_FIXED = 0 1445 prompt "Timer frequency" 1446 1447config HZ_100 1448 bool "100 Hz" 1449 1450config HZ_200 1451 bool "200 Hz" 1452 1453config HZ_250 1454 bool "250 Hz" 1455 1456config HZ_300 1457 bool "300 Hz" 1458 1459config HZ_500 1460 bool "500 Hz" 1461 1462config HZ_1000 1463 bool "1000 Hz" 1464 1465endchoice 1466 1467config HZ 1468 int 1469 default HZ_FIXED if HZ_FIXED != 0 1470 default 100 if HZ_100 1471 default 200 if HZ_200 1472 default 250 if HZ_250 1473 default 300 if HZ_300 1474 default 500 if HZ_500 1475 default 1000 1476 1477config SCHED_HRTICK 1478 def_bool HIGH_RES_TIMERS 1479 1480config THUMB2_KERNEL 1481 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1482 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1483 default y if CPU_THUMBONLY 1484 select AEABI 1485 select ARM_ASM_UNIFIED 1486 select ARM_UNWIND 1487 help 1488 By enabling this option, the kernel will be compiled in 1489 Thumb-2 mode. A compiler/assembler that understand the unified 1490 ARM-Thumb syntax is needed. 1491 1492 If unsure, say N. 1493 1494config THUMB2_AVOID_R_ARM_THM_JUMP11 1495 bool "Work around buggy Thumb-2 short branch relocations in gas" 1496 depends on THUMB2_KERNEL && MODULES 1497 default y 1498 help 1499 Various binutils versions can resolve Thumb-2 branches to 1500 locally-defined, preemptible global symbols as short-range "b.n" 1501 branch instructions. 1502 1503 This is a problem, because there's no guarantee the final 1504 destination of the symbol, or any candidate locations for a 1505 trampoline, are within range of the branch. For this reason, the 1506 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1507 relocation in modules at all, and it makes little sense to add 1508 support. 1509 1510 The symptom is that the kernel fails with an "unsupported 1511 relocation" error when loading some modules. 1512 1513 Until fixed tools are available, passing 1514 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1515 code which hits this problem, at the cost of a bit of extra runtime 1516 stack usage in some cases. 1517 1518 The problem is described in more detail at: 1519 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1520 1521 Only Thumb-2 kernels are affected. 1522 1523 Unless you are sure your tools don't have this problem, say Y. 1524 1525config ARM_ASM_UNIFIED 1526 bool 1527 1528config ARM_PATCH_IDIV 1529 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1530 depends on CPU_32v7 && !XIP_KERNEL 1531 default y 1532 help 1533 The ARM compiler inserts calls to __aeabi_idiv() and 1534 __aeabi_uidiv() when it needs to perform division on signed 1535 and unsigned integers. Some v7 CPUs have support for the sdiv 1536 and udiv instructions that can be used to implement those 1537 functions. 1538 1539 Enabling this option allows the kernel to modify itself to 1540 replace the first two instructions of these library functions 1541 with the sdiv or udiv plus "bx lr" instructions when the CPU 1542 it is running on supports them. Typically this will be faster 1543 and less power intensive than running the original library 1544 code to do integer division. 1545 1546config AEABI 1547 bool "Use the ARM EABI to compile the kernel" 1548 help 1549 This option allows for the kernel to be compiled using the latest 1550 ARM ABI (aka EABI). This is only useful if you are using a user 1551 space environment that is also compiled with EABI. 1552 1553 Since there are major incompatibilities between the legacy ABI and 1554 EABI, especially with regard to structure member alignment, this 1555 option also changes the kernel syscall calling convention to 1556 disambiguate both ABIs and allow for backward compatibility support 1557 (selected with CONFIG_OABI_COMPAT). 1558 1559 To use this you need GCC version 4.0.0 or later. 1560 1561config OABI_COMPAT 1562 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1563 depends on AEABI && !THUMB2_KERNEL 1564 help 1565 This option preserves the old syscall interface along with the 1566 new (ARM EABI) one. It also provides a compatibility layer to 1567 intercept syscalls that have structure arguments which layout 1568 in memory differs between the legacy ABI and the new ARM EABI 1569 (only for non "thumb" binaries). This option adds a tiny 1570 overhead to all syscalls and produces a slightly larger kernel. 1571 1572 The seccomp filter system will not be available when this is 1573 selected, since there is no way yet to sensibly distinguish 1574 between calling conventions during filtering. 1575 1576 If you know you'll be using only pure EABI user space then you 1577 can say N here. If this option is not selected and you attempt 1578 to execute a legacy ABI binary then the result will be 1579 UNPREDICTABLE (in fact it can be predicted that it won't work 1580 at all). If in doubt say N. 1581 1582config ARCH_HAS_HOLES_MEMORYMODEL 1583 bool 1584 1585config ARCH_SPARSEMEM_ENABLE 1586 bool 1587 1588config ARCH_SPARSEMEM_DEFAULT 1589 def_bool ARCH_SPARSEMEM_ENABLE 1590 1591config ARCH_SELECT_MEMORY_MODEL 1592 def_bool ARCH_SPARSEMEM_ENABLE 1593 1594config HAVE_ARCH_PFN_VALID 1595 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1596 1597config HAVE_GENERIC_RCU_GUP 1598 def_bool y 1599 depends on ARM_LPAE 1600 1601config HIGHMEM 1602 bool "High Memory Support" 1603 depends on MMU 1604 help 1605 The address space of ARM processors is only 4 Gigabytes large 1606 and it has to accommodate user address space, kernel address 1607 space as well as some memory mapped IO. That means that, if you 1608 have a large amount of physical memory and/or IO, not all of the 1609 memory can be "permanently mapped" by the kernel. The physical 1610 memory that is not permanently mapped is called "high memory". 1611 1612 Depending on the selected kernel/user memory split, minimum 1613 vmalloc space and actual amount of RAM, you may not need this 1614 option which should result in a slightly faster kernel. 1615 1616 If unsure, say n. 1617 1618config HIGHPTE 1619 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1620 depends on HIGHMEM 1621 default y 1622 help 1623 The VM uses one page of physical memory for each page table. 1624 For systems with a lot of processes, this can use a lot of 1625 precious low memory, eventually leading to low memory being 1626 consumed by page tables. Setting this option will allow 1627 user-space 2nd level page tables to reside in high memory. 1628 1629config CPU_SW_DOMAIN_PAN 1630 bool "Enable use of CPU domains to implement privileged no-access" 1631 depends on MMU && !ARM_LPAE 1632 default y 1633 help 1634 Increase kernel security by ensuring that normal kernel accesses 1635 are unable to access userspace addresses. This can help prevent 1636 use-after-free bugs becoming an exploitable privilege escalation 1637 by ensuring that magic values (such as LIST_POISON) will always 1638 fault when dereferenced. 1639 1640 CPUs with low-vector mappings use a best-efforts implementation. 1641 Their lower 1MB needs to remain accessible for the vectors, but 1642 the remainder of userspace will become appropriately inaccessible. 1643 1644config HW_PERF_EVENTS 1645 def_bool y 1646 depends on ARM_PMU 1647 1648config SYS_SUPPORTS_HUGETLBFS 1649 def_bool y 1650 depends on ARM_LPAE 1651 1652config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1653 def_bool y 1654 depends on ARM_LPAE 1655 1656config ARCH_WANT_GENERAL_HUGETLB 1657 def_bool y 1658 1659config ARM_MODULE_PLTS 1660 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1661 depends on MODULES 1662 help 1663 Allocate PLTs when loading modules so that jumps and calls whose 1664 targets are too far away for their relative offsets to be encoded 1665 in the instructions themselves can be bounced via veneers in the 1666 module's PLT. This allows modules to be allocated in the generic 1667 vmalloc area after the dedicated module memory area has been 1668 exhausted. The modules will use slightly more memory, but after 1669 rounding up to page size, the actual memory footprint is usually 1670 the same. 1671 1672 Say y if you are getting out of memory errors while loading modules 1673 1674source "mm/Kconfig" 1675 1676config FORCE_MAX_ZONEORDER 1677 int "Maximum zone order" 1678 default "12" if SOC_AM33XX 1679 default "9" if SA1111 || ARCH_EFM32 1680 default "11" 1681 help 1682 The kernel memory allocator divides physically contiguous memory 1683 blocks into "zones", where each zone is a power of two number of 1684 pages. This option selects the largest power of two that the kernel 1685 keeps in the memory allocator. If you need to allocate very large 1686 blocks of physically contiguous memory, then you may need to 1687 increase this value. 1688 1689 This config option is actually maximum order plus one. For example, 1690 a value of 11 means that the largest free memory block is 2^10 pages. 1691 1692config ALIGNMENT_TRAP 1693 bool 1694 depends on CPU_CP15_MMU 1695 default y if !ARCH_EBSA110 1696 select HAVE_PROC_CPU if PROC_FS 1697 help 1698 ARM processors cannot fetch/store information which is not 1699 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1700 address divisible by 4. On 32-bit ARM processors, these non-aligned 1701 fetch/store instructions will be emulated in software if you say 1702 here, which has a severe performance impact. This is necessary for 1703 correct operation of some network protocols. With an IP-only 1704 configuration it is safe to say N, otherwise say Y. 1705 1706config UACCESS_WITH_MEMCPY 1707 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1708 depends on MMU 1709 default y if CPU_FEROCEON 1710 help 1711 Implement faster copy_to_user and clear_user methods for CPU 1712 cores where a 8-word STM instruction give significantly higher 1713 memory write throughput than a sequence of individual 32bit stores. 1714 1715 A possible side effect is a slight increase in scheduling latency 1716 between threads sharing the same address space if they invoke 1717 such copy operations with large buffers. 1718 1719 However, if the CPU data cache is using a write-allocate mode, 1720 this option is unlikely to provide any performance gain. 1721 1722config SECCOMP 1723 bool 1724 prompt "Enable seccomp to safely compute untrusted bytecode" 1725 ---help--- 1726 This kernel feature is useful for number crunching applications 1727 that may need to compute untrusted bytecode during their 1728 execution. By using pipes or other transports made available to 1729 the process as file descriptors supporting the read/write 1730 syscalls, it's possible to isolate those applications in 1731 their own address space using seccomp. Once seccomp is 1732 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1733 and the task is only allowed to execute a few safe syscalls 1734 defined by each seccomp mode. 1735 1736config SWIOTLB 1737 def_bool y 1738 1739config IOMMU_HELPER 1740 def_bool SWIOTLB 1741 1742config PARAVIRT 1743 bool "Enable paravirtualization code" 1744 help 1745 This changes the kernel so it can modify itself when it is run 1746 under a hypervisor, potentially improving performance significantly 1747 over full virtualization. 1748 1749config PARAVIRT_TIME_ACCOUNTING 1750 bool "Paravirtual steal time accounting" 1751 select PARAVIRT 1752 default n 1753 help 1754 Select this option to enable fine granularity task steal time 1755 accounting. Time spent executing other tasks in parallel with 1756 the current vCPU is discounted from the vCPU power. To account for 1757 that, there can be a small performance impact. 1758 1759 If in doubt, say N here. 1760 1761config XEN_DOM0 1762 def_bool y 1763 depends on XEN 1764 1765config XEN 1766 bool "Xen guest support on ARM" 1767 depends on ARM && AEABI && OF 1768 depends on CPU_V7 && !CPU_V6 1769 depends on !GENERIC_ATOMIC64 1770 depends on MMU 1771 select ARCH_DMA_ADDR_T_64BIT 1772 select ARM_PSCI 1773 select SWIOTLB_XEN 1774 select PARAVIRT 1775 help 1776 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1777 1778endmenu 1779 1780menu "Boot options" 1781 1782config USE_OF 1783 bool "Flattened Device Tree support" 1784 select IRQ_DOMAIN 1785 select OF 1786 help 1787 Include support for flattened device tree machine descriptions. 1788 1789config ATAGS 1790 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1791 default y 1792 help 1793 This is the traditional way of passing data to the kernel at boot 1794 time. If you are solely relying on the flattened device tree (or 1795 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1796 to remove ATAGS support from your kernel binary. If unsure, 1797 leave this to y. 1798 1799config DEPRECATED_PARAM_STRUCT 1800 bool "Provide old way to pass kernel parameters" 1801 depends on ATAGS 1802 help 1803 This was deprecated in 2001 and announced to live on for 5 years. 1804 Some old boot loaders still use this way. 1805 1806# Compressed boot loader in ROM. Yes, we really want to ask about 1807# TEXT and BSS so we preserve their values in the config files. 1808config ZBOOT_ROM_TEXT 1809 hex "Compressed ROM boot loader base address" 1810 default "0" 1811 help 1812 The physical address at which the ROM-able zImage is to be 1813 placed in the target. Platforms which normally make use of 1814 ROM-able zImage formats normally set this to a suitable 1815 value in their defconfig file. 1816 1817 If ZBOOT_ROM is not enabled, this has no effect. 1818 1819config ZBOOT_ROM_BSS 1820 hex "Compressed ROM boot loader BSS address" 1821 default "0" 1822 help 1823 The base address of an area of read/write memory in the target 1824 for the ROM-able zImage which must be available while the 1825 decompressor is running. It must be large enough to hold the 1826 entire decompressed kernel plus an additional 128 KiB. 1827 Platforms which normally make use of ROM-able zImage formats 1828 normally set this to a suitable value in their defconfig file. 1829 1830 If ZBOOT_ROM is not enabled, this has no effect. 1831 1832config ZBOOT_ROM 1833 bool "Compressed boot loader in ROM/flash" 1834 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1835 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1836 help 1837 Say Y here if you intend to execute your compressed kernel image 1838 (zImage) directly from ROM or flash. If unsure, say N. 1839 1840config ARM_APPENDED_DTB 1841 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1842 depends on OF 1843 help 1844 With this option, the boot code will look for a device tree binary 1845 (DTB) appended to zImage 1846 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1847 1848 This is meant as a backward compatibility convenience for those 1849 systems with a bootloader that can't be upgraded to accommodate 1850 the documented boot protocol using a device tree. 1851 1852 Beware that there is very little in terms of protection against 1853 this option being confused by leftover garbage in memory that might 1854 look like a DTB header after a reboot if no actual DTB is appended 1855 to zImage. Do not leave this option active in a production kernel 1856 if you don't intend to always append a DTB. Proper passing of the 1857 location into r2 of a bootloader provided DTB is always preferable 1858 to this option. 1859 1860config ARM_ATAG_DTB_COMPAT 1861 bool "Supplement the appended DTB with traditional ATAG information" 1862 depends on ARM_APPENDED_DTB 1863 help 1864 Some old bootloaders can't be updated to a DTB capable one, yet 1865 they provide ATAGs with memory configuration, the ramdisk address, 1866 the kernel cmdline string, etc. Such information is dynamically 1867 provided by the bootloader and can't always be stored in a static 1868 DTB. To allow a device tree enabled kernel to be used with such 1869 bootloaders, this option allows zImage to extract the information 1870 from the ATAG list and store it at run time into the appended DTB. 1871 1872choice 1873 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1874 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1875 1876config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1877 bool "Use bootloader kernel arguments if available" 1878 help 1879 Uses the command-line options passed by the boot loader instead of 1880 the device tree bootargs property. If the boot loader doesn't provide 1881 any, the device tree bootargs property will be used. 1882 1883config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1884 bool "Extend with bootloader kernel arguments" 1885 help 1886 The command-line arguments provided by the boot loader will be 1887 appended to the the device tree bootargs property. 1888 1889endchoice 1890 1891config CMDLINE 1892 string "Default kernel command string" 1893 default "" 1894 help 1895 On some architectures (EBSA110 and CATS), there is currently no way 1896 for the boot loader to pass arguments to the kernel. For these 1897 architectures, you should supply some command-line options at build 1898 time by entering them here. As a minimum, you should specify the 1899 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1900 1901choice 1902 prompt "Kernel command line type" if CMDLINE != "" 1903 default CMDLINE_FROM_BOOTLOADER 1904 depends on ATAGS 1905 1906config CMDLINE_FROM_BOOTLOADER 1907 bool "Use bootloader kernel arguments if available" 1908 help 1909 Uses the command-line options passed by the boot loader. If 1910 the boot loader doesn't provide any, the default kernel command 1911 string provided in CMDLINE will be used. 1912 1913config CMDLINE_EXTEND 1914 bool "Extend bootloader kernel arguments" 1915 help 1916 The command-line arguments provided by the boot loader will be 1917 appended to the default kernel command string. 1918 1919config CMDLINE_FORCE 1920 bool "Always use the default kernel command string" 1921 help 1922 Always use the default kernel command string, even if the boot 1923 loader passes other arguments to the kernel. 1924 This is useful if you cannot or don't want to change the 1925 command-line options your boot loader passes to the kernel. 1926endchoice 1927 1928config XIP_KERNEL 1929 bool "Kernel Execute-In-Place from ROM" 1930 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1931 help 1932 Execute-In-Place allows the kernel to run from non-volatile storage 1933 directly addressable by the CPU, such as NOR flash. This saves RAM 1934 space since the text section of the kernel is not loaded from flash 1935 to RAM. Read-write sections, such as the data section and stack, 1936 are still copied to RAM. The XIP kernel is not compressed since 1937 it has to run directly from flash, so it will take more space to 1938 store it. The flash address used to link the kernel object files, 1939 and for storing it, is configuration dependent. Therefore, if you 1940 say Y here, you must know the proper physical address where to 1941 store the kernel image depending on your own flash memory usage. 1942 1943 Also note that the make target becomes "make xipImage" rather than 1944 "make zImage" or "make Image". The final kernel binary to put in 1945 ROM memory will be arch/arm/boot/xipImage. 1946 1947 If unsure, say N. 1948 1949config XIP_PHYS_ADDR 1950 hex "XIP Kernel Physical Location" 1951 depends on XIP_KERNEL 1952 default "0x00080000" 1953 help 1954 This is the physical address in your flash memory the kernel will 1955 be linked for and stored to. This address is dependent on your 1956 own flash usage. 1957 1958config KEXEC 1959 bool "Kexec system call (EXPERIMENTAL)" 1960 depends on (!SMP || PM_SLEEP_SMP) 1961 depends on !CPU_V7M 1962 select KEXEC_CORE 1963 help 1964 kexec is a system call that implements the ability to shutdown your 1965 current kernel, and to start another kernel. It is like a reboot 1966 but it is independent of the system firmware. And like a reboot 1967 you can start any kernel with it, not just Linux. 1968 1969 It is an ongoing process to be certain the hardware in a machine 1970 is properly shutdown, so do not be surprised if this code does not 1971 initially work for you. 1972 1973config ATAGS_PROC 1974 bool "Export atags in procfs" 1975 depends on ATAGS && KEXEC 1976 default y 1977 help 1978 Should the atags used to boot the kernel be exported in an "atags" 1979 file in procfs. Useful with kexec. 1980 1981config CRASH_DUMP 1982 bool "Build kdump crash kernel (EXPERIMENTAL)" 1983 help 1984 Generate crash dump after being started by kexec. This should 1985 be normally only set in special crash dump kernels which are 1986 loaded in the main kernel with kexec-tools into a specially 1987 reserved region and then later executed after a crash by 1988 kdump/kexec. The crash dump kernel must be compiled to a 1989 memory address not used by the main kernel 1990 1991 For more details see Documentation/kdump/kdump.txt 1992 1993config AUTO_ZRELADDR 1994 bool "Auto calculation of the decompressed kernel image address" 1995 help 1996 ZRELADDR is the physical address where the decompressed kernel 1997 image will be placed. If AUTO_ZRELADDR is selected, the address 1998 will be determined at run-time by masking the current IP with 1999 0xf8000000. This assumes the zImage being placed in the first 128MB 2000 from start of memory. 2001 2002config EFI_STUB 2003 bool 2004 2005config EFI 2006 bool "UEFI runtime support" 2007 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2008 select UCS2_STRING 2009 select EFI_PARAMS_FROM_FDT 2010 select EFI_STUB 2011 select EFI_ARMSTUB 2012 select EFI_RUNTIME_WRAPPERS 2013 ---help--- 2014 This option provides support for runtime services provided 2015 by UEFI firmware (such as non-volatile variables, realtime 2016 clock, and platform reset). A UEFI stub is also provided to 2017 allow the kernel to be booted as an EFI application. This 2018 is only useful for kernels that may run on systems that have 2019 UEFI firmware. 2020 2021endmenu 2022 2023menu "CPU Power Management" 2024 2025source "drivers/cpufreq/Kconfig" 2026 2027source "drivers/cpuidle/Kconfig" 2028 2029endmenu 2030 2031menu "Floating point emulation" 2032 2033comment "At least one emulation must be selected" 2034 2035config FPE_NWFPE 2036 bool "NWFPE math emulation" 2037 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2038 ---help--- 2039 Say Y to include the NWFPE floating point emulator in the kernel. 2040 This is necessary to run most binaries. Linux does not currently 2041 support floating point hardware so you need to say Y here even if 2042 your machine has an FPA or floating point co-processor podule. 2043 2044 You may say N here if you are going to load the Acorn FPEmulator 2045 early in the bootup. 2046 2047config FPE_NWFPE_XP 2048 bool "Support extended precision" 2049 depends on FPE_NWFPE 2050 help 2051 Say Y to include 80-bit support in the kernel floating-point 2052 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2053 Note that gcc does not generate 80-bit operations by default, 2054 so in most cases this option only enlarges the size of the 2055 floating point emulator without any good reason. 2056 2057 You almost surely want to say N here. 2058 2059config FPE_FASTFPE 2060 bool "FastFPE math emulation (EXPERIMENTAL)" 2061 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2062 ---help--- 2063 Say Y here to include the FAST floating point emulator in the kernel. 2064 This is an experimental much faster emulator which now also has full 2065 precision for the mantissa. It does not support any exceptions. 2066 It is very simple, and approximately 3-6 times faster than NWFPE. 2067 2068 It should be sufficient for most programs. It may be not suitable 2069 for scientific calculations, but you have to check this for yourself. 2070 If you do not feel you need a faster FP emulation you should better 2071 choose NWFPE. 2072 2073config VFP 2074 bool "VFP-format floating point maths" 2075 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2076 help 2077 Say Y to include VFP support code in the kernel. This is needed 2078 if your hardware includes a VFP unit. 2079 2080 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2081 release notes and additional status information. 2082 2083 Say N if your target does not have VFP hardware. 2084 2085config VFPv3 2086 bool 2087 depends on VFP 2088 default y if CPU_V7 2089 2090config NEON 2091 bool "Advanced SIMD (NEON) Extension support" 2092 depends on VFPv3 && CPU_V7 2093 help 2094 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2095 Extension. 2096 2097config KERNEL_MODE_NEON 2098 bool "Support for NEON in kernel mode" 2099 depends on NEON && AEABI 2100 help 2101 Say Y to include support for NEON in kernel mode. 2102 2103endmenu 2104 2105menu "Userspace binary formats" 2106 2107source "fs/Kconfig.binfmt" 2108 2109endmenu 2110 2111menu "Power management options" 2112 2113source "kernel/power/Kconfig" 2114 2115config ARCH_SUSPEND_POSSIBLE 2116 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2117 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2118 def_bool y 2119 2120config ARM_CPU_SUSPEND 2121 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2122 depends on ARCH_SUSPEND_POSSIBLE 2123 2124config ARCH_HIBERNATION_POSSIBLE 2125 bool 2126 depends on MMU 2127 default y if ARCH_SUSPEND_POSSIBLE 2128 2129endmenu 2130 2131source "net/Kconfig" 2132 2133source "drivers/Kconfig" 2134 2135source "drivers/firmware/Kconfig" 2136 2137source "fs/Kconfig" 2138 2139source "arch/arm/Kconfig.debug" 2140 2141source "security/Kconfig" 2142 2143source "crypto/Kconfig" 2144if CRYPTO 2145source "arch/arm/crypto/Kconfig" 2146endif 2147 2148source "lib/Kconfig" 2149 2150source "arch/arm/kvm/Kconfig" 2151