1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_PHYS_TO_DMA 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select CLONE_BACKWARDS 47 select CPU_PM if SUSPEND || CPU_IDLE 48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 49 select DMA_DECLARE_COHERENT 50 select DMA_GLOBAL_POOL if !MMU 51 select DMA_OPS 52 select DMA_NONCOHERENT_MMAP if MMU 53 select EDAC_SUPPORT 54 select EDAC_ATOMIC_SCRUB 55 select GENERIC_ALLOCATOR 56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 59 select GENERIC_IRQ_IPI if SMP 60 select GENERIC_CPU_AUTOPROBE 61 select GENERIC_EARLY_IOREMAP 62 select GENERIC_IDLE_POLL_SETUP 63 select GENERIC_IRQ_MULTI_HANDLER 64 select GENERIC_IRQ_PROBE 65 select GENERIC_IRQ_SHOW 66 select GENERIC_IRQ_SHOW_LEVEL 67 select GENERIC_LIB_DEVMEM_IS_ALLOWED 68 select GENERIC_PCI_IOMAP 69 select GENERIC_SCHED_CLOCK 70 select GENERIC_SMP_IDLE_THREAD 71 select HARDIRQS_SW_RESEND 72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 78 select HAVE_ARCH_MMAP_RND_BITS if MMU 79 select HAVE_ARCH_PFN_VALID 80 select HAVE_ARCH_SECCOMP 81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 83 select HAVE_ARCH_TRACEHOOK 84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 85 select HAVE_ARM_SMCCC if CPU_V7 86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 87 select HAVE_CONTEXT_TRACKING 88 select HAVE_C_RECORDMCOUNT 89 select HAVE_BUILDTIME_MCOUNT_SORT 90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 91 select HAVE_DMA_CONTIGUOUS if MMU 92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 95 select HAVE_EXIT_THREAD 96 select HAVE_FAST_GUP if ARM_LPAE 97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 98 select HAVE_FUNCTION_GRAPH_TRACER 99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 100 select HAVE_GCC_PLUGINS 101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 102 select HAVE_IRQ_TIME_ACCOUNTING 103 select HAVE_KERNEL_GZIP 104 select HAVE_KERNEL_LZ4 105 select HAVE_KERNEL_LZMA 106 select HAVE_KERNEL_LZO 107 select HAVE_KERNEL_XZ 108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 109 select HAVE_KRETPROBES if HAVE_KPROBES 110 select HAVE_MOD_ARCH_SPECIFIC 111 select HAVE_NMI 112 select HAVE_OPTPROBES if !THUMB2_KERNEL 113 select HAVE_PERF_EVENTS 114 select HAVE_PERF_REGS 115 select HAVE_PERF_USER_STACK_DUMP 116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 117 select HAVE_REGS_AND_STACK_ACCESS_API 118 select HAVE_RSEQ 119 select HAVE_STACKPROTECTOR 120 select HAVE_SYSCALL_TRACEPOINTS 121 select HAVE_UID16 122 select HAVE_VIRT_CPU_ACCOUNTING_GEN 123 select IRQ_FORCED_THREADING 124 select MODULES_USE_ELF_REL 125 select NEED_DMA_MAP_STATE 126 select OF_EARLY_FLATTREE if OF 127 select OLD_SIGACTION 128 select OLD_SIGSUSPEND3 129 select PCI_SYSCALL if PCI 130 select PERF_USE_VMALLOC 131 select RTC_LIB 132 select SYS_SUPPORTS_APM_EMULATION 133 select THREAD_INFO_IN_TASK 134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 136 # Above selects are sorted alphabetically; please add new ones 137 # according to that. Thanks. 138 help 139 The ARM series is a line of low-power-consumption RISC chip designs 140 licensed by ARM Ltd and targeted at embedded applications and 141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 142 manufactured, but legacy ARM-based PC hardware remains popular in 143 Europe. There is an ARM Linux project with a web page at 144 <http://www.arm.linux.org.uk/>. 145 146config ARM_HAS_GROUP_RELOCS 147 def_bool y 148 depends on !LD_IS_LLD || LLD_VERSION >= 140000 149 depends on !COMPILE_TEST 150 help 151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 152 relocations, which have been around for a long time, but were not 153 supported in LLD until version 14. The combined range is -/+ 256 MiB, 154 which is usually sufficient, but not for allyesconfig, so we disable 155 this feature when doing compile testing. 156 157config ARM_HAS_SG_CHAIN 158 bool 159 160config ARM_DMA_USE_IOMMU 161 bool 162 select ARM_HAS_SG_CHAIN 163 select NEED_SG_DMA_LENGTH 164 165if ARM_DMA_USE_IOMMU 166 167config ARM_DMA_IOMMU_ALIGNMENT 168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 169 range 4 9 170 default 8 171 help 172 DMA mapping framework by default aligns all buffers to the smallest 173 PAGE_SIZE order which is greater than or equal to the requested buffer 174 size. This works well for buffers up to a few hundreds kilobytes, but 175 for larger buffers it just a waste of address space. Drivers which has 176 relatively small addressing window (like 64Mib) might run out of 177 virtual space with just a few allocations. 178 179 With this parameter you can specify the maximum PAGE_SIZE order for 180 DMA IOMMU buffers. Larger buffers will be aligned only to this 181 specified order. The order is expressed as a power of two multiplied 182 by the PAGE_SIZE. 183 184endif 185 186config SYS_SUPPORTS_APM_EMULATION 187 bool 188 189config HAVE_TCM 190 bool 191 select GENERIC_ALLOCATOR 192 193config HAVE_PROC_CPU 194 bool 195 196config NO_IOPORT_MAP 197 bool 198 199config SBUS 200 bool 201 202config STACKTRACE_SUPPORT 203 bool 204 default y 205 206config LOCKDEP_SUPPORT 207 bool 208 default y 209 210config ARCH_HAS_ILOG2_U32 211 bool 212 213config ARCH_HAS_ILOG2_U64 214 bool 215 216config ARCH_HAS_BANDGAP 217 bool 218 219config FIX_EARLYCON_MEM 220 def_bool y if MMU 221 222config GENERIC_HWEIGHT 223 bool 224 default y 225 226config GENERIC_CALIBRATE_DELAY 227 bool 228 default y 229 230config ARCH_MAY_HAVE_PC_FDC 231 bool 232 233config ARCH_SUPPORTS_UPROBES 234 def_bool y 235 236config GENERIC_ISA_DMA 237 bool 238 239config FIQ 240 bool 241 242config ARCH_MTD_XIP 243 bool 244 245config ARM_PATCH_PHYS_VIRT 246 bool "Patch physical to virtual translations at runtime" if EMBEDDED 247 default y 248 depends on !XIP_KERNEL && MMU 249 help 250 Patch phys-to-virt and virt-to-phys translation functions at 251 boot and module load time according to the position of the 252 kernel in system memory. 253 254 This can only be used with non-XIP MMU kernels where the base 255 of physical memory is at a 2 MiB boundary. 256 257 Only disable this option if you know that you do not require 258 this feature (eg, building a kernel for a single machine) and 259 you need to shrink the kernel to the minimal size. 260 261config NEED_MACH_IO_H 262 bool 263 help 264 Select this when mach/io.h is required to provide special 265 definitions for this platform. The need for mach/io.h should 266 be avoided when possible. 267 268config NEED_MACH_MEMORY_H 269 bool 270 help 271 Select this when mach/memory.h is required to provide special 272 definitions for this platform. The need for mach/memory.h should 273 be avoided when possible. 274 275config PHYS_OFFSET 276 hex "Physical address of main memory" if MMU 277 depends on !ARM_PATCH_PHYS_VIRT 278 default DRAM_BASE if !MMU 279 default 0x00000000 if ARCH_FOOTBRIDGE 280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 281 default 0x30000000 if ARCH_S3C24XX 282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 284 default 0 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298menu "System Type" 299 300config MMU 301 bool "MMU-based Paged Memory Management Support" 302 default y 303 help 304 Select if you want MMU-based virtualised addressing space 305 support by paged memory management. If unsure, say 'Y'. 306 307config ARM_SINGLE_ARMV7M 308 def_bool !MMU 309 select ARM_NVIC 310 select AUTO_ZRELADDR 311 select TIMER_OF 312 select COMMON_CLK 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 select SPARSE_IRQ 316 select USE_OF 317 318config ARCH_MMAP_RND_BITS_MIN 319 default 8 320 321config ARCH_MMAP_RND_BITS_MAX 322 default 14 if PAGE_OFFSET=0x40000000 323 default 15 if PAGE_OFFSET=0x80000000 324 default 16 325 326# 327# The "ARM system type" choice list is ordered alphabetically by option 328# text. Please add new entries in the option alphabetic order. 329# 330choice 331 prompt "ARM system type" 332 depends on MMU 333 default ARCH_MULTIPLATFORM 334 335config ARCH_MULTIPLATFORM 336 bool "Allow multiple platforms to be selected" 337 select ARCH_FLATMEM_ENABLE 338 select ARCH_SPARSEMEM_ENABLE 339 select ARCH_SELECT_MEMORY_MODEL 340 select ARM_HAS_SG_CHAIN 341 select ARM_PATCH_PHYS_VIRT 342 select AUTO_ZRELADDR 343 select TIMER_OF 344 select COMMON_CLK 345 select HAVE_PCI 346 select PCI_DOMAINS_GENERIC if PCI 347 select SPARSE_IRQ 348 select USE_OF 349 350config ARCH_FOOTBRIDGE 351 bool "FootBridge" 352 depends on CPU_LITTLE_ENDIAN 353 select CPU_SA110 354 select FOOTBRIDGE 355 select NEED_MACH_MEMORY_H 356 help 357 Support for systems based on the DC21285 companion chip 358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 359 360config ARCH_PXA 361 bool "PXA2xx/PXA3xx-based" 362 depends on CPU_LITTLE_ENDIAN 363 select ARCH_MTD_XIP 364 select ARM_CPU_SUSPEND if PM 365 select AUTO_ZRELADDR 366 select COMMON_CLK 367 select CLKSRC_PXA 368 select CLKSRC_MMIO 369 select TIMER_OF 370 select CPU_XSCALE if !CPU_XSC3 371 select GPIO_PXA 372 select GPIOLIB 373 select IRQ_DOMAIN 374 select PLAT_PXA 375 select SPARSE_IRQ 376 help 377 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 378 379config ARCH_RPC 380 bool "RiscPC" 381 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 382 depends on CPU_LITTLE_ENDIAN 383 select ARCH_ACORN 384 select ARCH_MAY_HAVE_PC_FDC 385 select ARCH_SPARSEMEM_ENABLE 386 select ARM_HAS_SG_CHAIN 387 select CPU_SA110 388 select FIQ 389 select HAVE_PATA_PLATFORM 390 select ISA_DMA_API 391 select LEGACY_TIMER_TICK 392 select NEED_MACH_IO_H 393 select NEED_MACH_MEMORY_H 394 select NO_IOPORT_MAP 395 help 396 On the Acorn Risc-PC, Linux can support the internal IDE disk and 397 CD-ROM interface, serial and parallel port, and the floppy drive. 398 399config ARCH_SA1100 400 bool "SA1100-based" 401 depends on CPU_LITTLE_ENDIAN 402 select ARCH_MTD_XIP 403 select ARCH_SPARSEMEM_ENABLE 404 select CLKSRC_MMIO 405 select CLKSRC_PXA 406 select TIMER_OF if OF 407 select COMMON_CLK 408 select CPU_FREQ 409 select CPU_SA1100 410 select GPIOLIB 411 select IRQ_DOMAIN 412 select ISA 413 select NEED_MACH_MEMORY_H 414 select SPARSE_IRQ 415 help 416 Support for StrongARM 11x0 based boards. 417 418config ARCH_OMAP1 419 bool "TI OMAP1" 420 depends on CPU_LITTLE_ENDIAN 421 select CLKSRC_MMIO 422 select FORCE_PCI if PCCARD 423 select GENERIC_IRQ_CHIP 424 select GPIOLIB 425 select HAVE_LEGACY_CLK 426 select IRQ_DOMAIN 427 select SPARSE_IRQ 428 help 429 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 430 431endchoice 432 433menu "Multiple platform selection" 434 depends on ARCH_MULTIPLATFORM 435 436comment "CPU Core family selection" 437 438config ARCH_MULTI_V4 439 bool "ARMv4 based platforms (FA526)" 440 depends on !ARCH_MULTI_V6_V7 441 select ARCH_MULTI_V4_V5 442 select CPU_FA526 443 444config ARCH_MULTI_V4T 445 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 446 depends on !ARCH_MULTI_V6_V7 447 select ARCH_MULTI_V4_V5 448 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 449 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 450 CPU_ARM925T || CPU_ARM940T) 451 452config ARCH_MULTI_V5 453 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 454 depends on !ARCH_MULTI_V6_V7 455 select ARCH_MULTI_V4_V5 456 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 457 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 458 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 459 460config ARCH_MULTI_V4_V5 461 bool 462 463config ARCH_MULTI_V6 464 bool "ARMv6 based platforms (ARM11)" 465 select ARCH_MULTI_V6_V7 466 select CPU_V6K 467 468config ARCH_MULTI_V7 469 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 470 default y 471 select ARCH_MULTI_V6_V7 472 select CPU_V7 473 select HAVE_SMP 474 475config ARCH_MULTI_V6_V7 476 bool 477 select MIGHT_HAVE_CACHE_L2X0 478 479config ARCH_MULTI_CPU_AUTO 480 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 481 select ARCH_MULTI_V5 482 483endmenu 484 485config ARCH_VIRT 486 bool "Dummy Virtual Machine" 487 depends on ARCH_MULTI_V7 488 select ARM_AMBA 489 select ARM_GIC 490 select ARM_GIC_V2M if PCI 491 select ARM_GIC_V3 492 select ARM_GIC_V3_ITS if PCI 493 select ARM_PSCI 494 select HAVE_ARM_ARCH_TIMER 495 496config ARCH_AIROHA 497 bool "Airoha SoC Support" 498 depends on ARCH_MULTI_V7 499 select ARM_AMBA 500 select ARM_GIC 501 select ARM_GIC_V3 502 select ARM_PSCI 503 select HAVE_ARM_ARCH_TIMER 504 select COMMON_CLK 505 help 506 Support for Airoha EN7523 SoCs 507 508# 509# This is sorted alphabetically by mach-* pathname. However, plat-* 510# Kconfigs may be included either alphabetically (according to the 511# plat- suffix) or along side the corresponding mach-* source. 512# 513source "arch/arm/mach-actions/Kconfig" 514 515source "arch/arm/mach-alpine/Kconfig" 516 517source "arch/arm/mach-artpec/Kconfig" 518 519source "arch/arm/mach-asm9260/Kconfig" 520 521source "arch/arm/mach-aspeed/Kconfig" 522 523source "arch/arm/mach-at91/Kconfig" 524 525source "arch/arm/mach-axxia/Kconfig" 526 527source "arch/arm/mach-bcm/Kconfig" 528 529source "arch/arm/mach-berlin/Kconfig" 530 531source "arch/arm/mach-clps711x/Kconfig" 532 533source "arch/arm/mach-cns3xxx/Kconfig" 534 535source "arch/arm/mach-davinci/Kconfig" 536 537source "arch/arm/mach-digicolor/Kconfig" 538 539source "arch/arm/mach-dove/Kconfig" 540 541source "arch/arm/mach-ep93xx/Kconfig" 542 543source "arch/arm/mach-exynos/Kconfig" 544 545source "arch/arm/mach-footbridge/Kconfig" 546 547source "arch/arm/mach-gemini/Kconfig" 548 549source "arch/arm/mach-highbank/Kconfig" 550 551source "arch/arm/mach-hisi/Kconfig" 552 553source "arch/arm/mach-imx/Kconfig" 554 555source "arch/arm/mach-iop32x/Kconfig" 556 557source "arch/arm/mach-ixp4xx/Kconfig" 558 559source "arch/arm/mach-keystone/Kconfig" 560 561source "arch/arm/mach-lpc32xx/Kconfig" 562 563source "arch/arm/mach-mediatek/Kconfig" 564 565source "arch/arm/mach-meson/Kconfig" 566 567source "arch/arm/mach-milbeaut/Kconfig" 568 569source "arch/arm/mach-mmp/Kconfig" 570 571source "arch/arm/mach-moxart/Kconfig" 572 573source "arch/arm/mach-mstar/Kconfig" 574 575source "arch/arm/mach-mv78xx0/Kconfig" 576 577source "arch/arm/mach-mvebu/Kconfig" 578 579source "arch/arm/mach-mxs/Kconfig" 580 581source "arch/arm/mach-nomadik/Kconfig" 582 583source "arch/arm/mach-npcm/Kconfig" 584 585source "arch/arm/mach-nspire/Kconfig" 586 587source "arch/arm/mach-omap1/Kconfig" 588 589source "arch/arm/mach-omap2/Kconfig" 590 591source "arch/arm/mach-orion5x/Kconfig" 592 593source "arch/arm/mach-oxnas/Kconfig" 594 595source "arch/arm/mach-pxa/Kconfig" 596source "arch/arm/plat-pxa/Kconfig" 597 598source "arch/arm/mach-qcom/Kconfig" 599 600source "arch/arm/mach-rda/Kconfig" 601 602source "arch/arm/mach-realtek/Kconfig" 603 604source "arch/arm/mach-rockchip/Kconfig" 605 606source "arch/arm/mach-s3c/Kconfig" 607 608source "arch/arm/mach-s5pv210/Kconfig" 609 610source "arch/arm/mach-sa1100/Kconfig" 611 612source "arch/arm/mach-shmobile/Kconfig" 613 614source "arch/arm/mach-socfpga/Kconfig" 615 616source "arch/arm/mach-spear/Kconfig" 617 618source "arch/arm/mach-sti/Kconfig" 619 620source "arch/arm/mach-stm32/Kconfig" 621 622source "arch/arm/mach-sunxi/Kconfig" 623 624source "arch/arm/mach-tegra/Kconfig" 625 626source "arch/arm/mach-uniphier/Kconfig" 627 628source "arch/arm/mach-ux500/Kconfig" 629 630source "arch/arm/mach-versatile/Kconfig" 631 632source "arch/arm/mach-vt8500/Kconfig" 633 634source "arch/arm/mach-zynq/Kconfig" 635 636# ARMv7-M architecture 637config ARCH_LPC18XX 638 bool "NXP LPC18xx/LPC43xx" 639 depends on ARM_SINGLE_ARMV7M 640 select ARCH_HAS_RESET_CONTROLLER 641 select ARM_AMBA 642 select CLKSRC_LPC32XX 643 select PINCTRL 644 help 645 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 646 high performance microcontrollers. 647 648config ARCH_MPS2 649 bool "ARM MPS2 platform" 650 depends on ARM_SINGLE_ARMV7M 651 select ARM_AMBA 652 select CLKSRC_MPS2 653 help 654 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 655 with a range of available cores like Cortex-M3/M4/M7. 656 657 Please, note that depends which Application Note is used memory map 658 for the platform may vary, so adjustment of RAM base might be needed. 659 660# Definitions to make life easier 661config ARCH_ACORN 662 bool 663 664config PLAT_ORION 665 bool 666 select CLKSRC_MMIO 667 select COMMON_CLK 668 select GENERIC_IRQ_CHIP 669 select IRQ_DOMAIN 670 671config PLAT_ORION_LEGACY 672 bool 673 select PLAT_ORION 674 675config PLAT_PXA 676 bool 677 678config PLAT_VERSATILE 679 bool 680 681source "arch/arm/mm/Kconfig" 682 683config IWMMXT 684 bool "Enable iWMMXt support" 685 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 686 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 687 help 688 Enable support for iWMMXt context switching at run time if 689 running on a CPU that supports it. 690 691if !MMU 692source "arch/arm/Kconfig-nommu" 693endif 694 695config PJ4B_ERRATA_4742 696 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 697 depends on CPU_PJ4B && MACH_ARMADA_370 698 default y 699 help 700 When coming out of either a Wait for Interrupt (WFI) or a Wait for 701 Event (WFE) IDLE states, a specific timing sensitivity exists between 702 the retiring WFI/WFE instructions and the newly issued subsequent 703 instructions. This sensitivity can result in a CPU hang scenario. 704 Workaround: 705 The software must insert either a Data Synchronization Barrier (DSB) 706 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 707 instruction 708 709config ARM_ERRATA_326103 710 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 711 depends on CPU_V6 712 help 713 Executing a SWP instruction to read-only memory does not set bit 11 714 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 715 treat the access as a read, preventing a COW from occurring and 716 causing the faulting task to livelock. 717 718config ARM_ERRATA_411920 719 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 720 depends on CPU_V6 || CPU_V6K 721 help 722 Invalidation of the Instruction Cache operation can 723 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 724 It does not affect the MPCore. This option enables the ARM Ltd. 725 recommended workaround. 726 727config ARM_ERRATA_430973 728 bool "ARM errata: Stale prediction on replaced interworking branch" 729 depends on CPU_V7 730 help 731 This option enables the workaround for the 430973 Cortex-A8 732 r1p* erratum. If a code sequence containing an ARM/Thumb 733 interworking branch is replaced with another code sequence at the 734 same virtual address, whether due to self-modifying code or virtual 735 to physical address re-mapping, Cortex-A8 does not recover from the 736 stale interworking branch prediction. This results in Cortex-A8 737 executing the new code sequence in the incorrect ARM or Thumb state. 738 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 739 and also flushes the branch target cache at every context switch. 740 Note that setting specific bits in the ACTLR register may not be 741 available in non-secure mode. 742 743config ARM_ERRATA_458693 744 bool "ARM errata: Processor deadlock when a false hazard is created" 745 depends on CPU_V7 746 depends on !ARCH_MULTIPLATFORM 747 help 748 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 749 erratum. For very specific sequences of memory operations, it is 750 possible for a hazard condition intended for a cache line to instead 751 be incorrectly associated with a different cache line. This false 752 hazard might then cause a processor deadlock. The workaround enables 753 the L1 caching of the NEON accesses and disables the PLD instruction 754 in the ACTLR register. Note that setting specific bits in the ACTLR 755 register may not be available in non-secure mode. 756 757config ARM_ERRATA_460075 758 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 759 depends on CPU_V7 760 depends on !ARCH_MULTIPLATFORM 761 help 762 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 763 erratum. Any asynchronous access to the L2 cache may encounter a 764 situation in which recent store transactions to the L2 cache are lost 765 and overwritten with stale memory contents from external memory. The 766 workaround disables the write-allocate mode for the L2 cache via the 767 ACTLR register. Note that setting specific bits in the ACTLR register 768 may not be available in non-secure mode. 769 770config ARM_ERRATA_742230 771 bool "ARM errata: DMB operation may be faulty" 772 depends on CPU_V7 && SMP 773 depends on !ARCH_MULTIPLATFORM 774 help 775 This option enables the workaround for the 742230 Cortex-A9 776 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 777 between two write operations may not ensure the correct visibility 778 ordering of the two writes. This workaround sets a specific bit in 779 the diagnostic register of the Cortex-A9 which causes the DMB 780 instruction to behave as a DSB, ensuring the correct behaviour of 781 the two writes. 782 783config ARM_ERRATA_742231 784 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 785 depends on CPU_V7 && SMP 786 depends on !ARCH_MULTIPLATFORM 787 help 788 This option enables the workaround for the 742231 Cortex-A9 789 (r2p0..r2p2) erratum. Under certain conditions, specific to the 790 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 791 accessing some data located in the same cache line, may get corrupted 792 data due to bad handling of the address hazard when the line gets 793 replaced from one of the CPUs at the same time as another CPU is 794 accessing it. This workaround sets specific bits in the diagnostic 795 register of the Cortex-A9 which reduces the linefill issuing 796 capabilities of the processor. 797 798config ARM_ERRATA_643719 799 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 800 depends on CPU_V7 && SMP 801 default y 802 help 803 This option enables the workaround for the 643719 Cortex-A9 (prior to 804 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 805 register returns zero when it should return one. The workaround 806 corrects this value, ensuring cache maintenance operations which use 807 it behave as intended and avoiding data corruption. 808 809config ARM_ERRATA_720789 810 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 811 depends on CPU_V7 812 help 813 This option enables the workaround for the 720789 Cortex-A9 (prior to 814 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 815 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 816 As a consequence of this erratum, some TLB entries which should be 817 invalidated are not, resulting in an incoherency in the system page 818 tables. The workaround changes the TLB flushing routines to invalidate 819 entries regardless of the ASID. 820 821config ARM_ERRATA_743622 822 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 823 depends on CPU_V7 824 depends on !ARCH_MULTIPLATFORM 825 help 826 This option enables the workaround for the 743622 Cortex-A9 827 (r2p*) erratum. Under very rare conditions, a faulty 828 optimisation in the Cortex-A9 Store Buffer may lead to data 829 corruption. This workaround sets a specific bit in the diagnostic 830 register of the Cortex-A9 which disables the Store Buffer 831 optimisation, preventing the defect from occurring. This has no 832 visible impact on the overall performance or power consumption of the 833 processor. 834 835config ARM_ERRATA_751472 836 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 837 depends on CPU_V7 838 depends on !ARCH_MULTIPLATFORM 839 help 840 This option enables the workaround for the 751472 Cortex-A9 (prior 841 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 842 completion of a following broadcasted operation if the second 843 operation is received by a CPU before the ICIALLUIS has completed, 844 potentially leading to corrupted entries in the cache or TLB. 845 846config ARM_ERRATA_754322 847 bool "ARM errata: possible faulty MMU translations following an ASID switch" 848 depends on CPU_V7 849 help 850 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 851 r3p*) erratum. A speculative memory access may cause a page table walk 852 which starts prior to an ASID switch but completes afterwards. This 853 can populate the micro-TLB with a stale entry which may be hit with 854 the new ASID. This workaround places two dsb instructions in the mm 855 switching code so that no page table walks can cross the ASID switch. 856 857config ARM_ERRATA_754327 858 bool "ARM errata: no automatic Store Buffer drain" 859 depends on CPU_V7 && SMP 860 help 861 This option enables the workaround for the 754327 Cortex-A9 (prior to 862 r2p0) erratum. The Store Buffer does not have any automatic draining 863 mechanism and therefore a livelock may occur if an external agent 864 continuously polls a memory location waiting to observe an update. 865 This workaround defines cpu_relax() as smp_mb(), preventing correctly 866 written polling loops from denying visibility of updates to memory. 867 868config ARM_ERRATA_364296 869 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 870 depends on CPU_V6 871 help 872 This options enables the workaround for the 364296 ARM1136 873 r0p2 erratum (possible cache data corruption with 874 hit-under-miss enabled). It sets the undocumented bit 31 in 875 the auxiliary control register and the FI bit in the control 876 register, thus disabling hit-under-miss without putting the 877 processor into full low interrupt latency mode. ARM11MPCore 878 is not affected. 879 880config ARM_ERRATA_764369 881 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 882 depends on CPU_V7 && SMP 883 help 884 This option enables the workaround for erratum 764369 885 affecting Cortex-A9 MPCore with two or more processors (all 886 current revisions). Under certain timing circumstances, a data 887 cache line maintenance operation by MVA targeting an Inner 888 Shareable memory region may fail to proceed up to either the 889 Point of Coherency or to the Point of Unification of the 890 system. This workaround adds a DSB instruction before the 891 relevant cache maintenance functions and sets a specific bit 892 in the diagnostic control register of the SCU. 893 894config ARM_ERRATA_764319 895 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 896 depends on CPU_V7 897 help 898 This option enables the workaround for the 764319 Cortex A-9 erratum. 899 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 900 unexpected Undefined Instruction exception when the DBGSWENABLE 901 external pin is set to 0, even when the CP14 accesses are performed 902 from a privileged mode. This work around catches the exception in a 903 way the kernel does not stop execution. 904 905config ARM_ERRATA_775420 906 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 907 depends on CPU_V7 908 help 909 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 910 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 911 operation aborts with MMU exception, it might cause the processor 912 to deadlock. This workaround puts DSB before executing ISB if 913 an abort may occur on cache maintenance. 914 915config ARM_ERRATA_798181 916 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 917 depends on CPU_V7 && SMP 918 help 919 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 920 adequately shooting down all use of the old entries. This 921 option enables the Linux kernel workaround for this erratum 922 which sends an IPI to the CPUs that are running the same ASID 923 as the one being invalidated. 924 925config ARM_ERRATA_773022 926 bool "ARM errata: incorrect instructions may be executed from loop buffer" 927 depends on CPU_V7 928 help 929 This option enables the workaround for the 773022 Cortex-A15 930 (up to r0p4) erratum. In certain rare sequences of code, the 931 loop buffer may deliver incorrect instructions. This 932 workaround disables the loop buffer to avoid the erratum. 933 934config ARM_ERRATA_818325_852422 935 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 936 depends on CPU_V7 937 help 938 This option enables the workaround for: 939 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 940 instruction might deadlock. Fixed in r0p1. 941 - Cortex-A12 852422: Execution of a sequence of instructions might 942 lead to either a data corruption or a CPU deadlock. Not fixed in 943 any Cortex-A12 cores yet. 944 This workaround for all both errata involves setting bit[12] of the 945 Feature Register. This bit disables an optimisation applied to a 946 sequence of 2 instructions that use opposing condition codes. 947 948config ARM_ERRATA_821420 949 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 950 depends on CPU_V7 951 help 952 This option enables the workaround for the 821420 Cortex-A12 953 (all revs) erratum. In very rare timing conditions, a sequence 954 of VMOV to Core registers instructions, for which the second 955 one is in the shadow of a branch or abort, can lead to a 956 deadlock when the VMOV instructions are issued out-of-order. 957 958config ARM_ERRATA_825619 959 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 960 depends on CPU_V7 961 help 962 This option enables the workaround for the 825619 Cortex-A12 963 (all revs) erratum. Within rare timing constraints, executing a 964 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 965 and Device/Strongly-Ordered loads and stores might cause deadlock 966 967config ARM_ERRATA_857271 968 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 969 depends on CPU_V7 970 help 971 This option enables the workaround for the 857271 Cortex-A12 972 (all revs) erratum. Under very rare timing conditions, the CPU might 973 hang. The workaround is expected to have a < 1% performance impact. 974 975config ARM_ERRATA_852421 976 bool "ARM errata: A17: DMB ST might fail to create order between stores" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 852421 Cortex-A17 980 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 981 execution of a DMB ST instruction might fail to properly order 982 stores from GroupA and stores from GroupB. 983 984config ARM_ERRATA_852423 985 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 986 depends on CPU_V7 987 help 988 This option enables the workaround for: 989 - Cortex-A17 852423: Execution of a sequence of instructions might 990 lead to either a data corruption or a CPU deadlock. Not fixed in 991 any Cortex-A17 cores yet. 992 This is identical to Cortex-A12 erratum 852422. It is a separate 993 config option from the A12 erratum due to the way errata are checked 994 for and handled. 995 996config ARM_ERRATA_857272 997 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 998 depends on CPU_V7 999 help 1000 This option enables the workaround for the 857272 Cortex-A17 erratum. 1001 This erratum is not known to be fixed in any A17 revision. 1002 This is identical to Cortex-A12 erratum 857271. It is a separate 1003 config option from the A12 erratum due to the way errata are checked 1004 for and handled. 1005 1006endmenu 1007 1008source "arch/arm/common/Kconfig" 1009 1010menu "Bus support" 1011 1012config ISA 1013 bool 1014 help 1015 Find out whether you have ISA slots on your motherboard. ISA is the 1016 name of a bus system, i.e. the way the CPU talks to the other stuff 1017 inside your box. Other bus systems are PCI, EISA, MicroChannel 1018 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1019 newer boards don't support it. If you have ISA, say Y, otherwise N. 1020 1021# Select ISA DMA controller support 1022config ISA_DMA 1023 bool 1024 select ISA_DMA_API 1025 1026# Select ISA DMA interface 1027config ISA_DMA_API 1028 bool 1029 1030config PCI_NANOENGINE 1031 bool "BSE nanoEngine PCI support" 1032 depends on SA1100_NANOENGINE 1033 help 1034 Enable PCI on the BSE nanoEngine board. 1035 1036config ARM_ERRATA_814220 1037 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1038 depends on CPU_V7 1039 help 1040 The v7 ARM states that all cache and branch predictor maintenance 1041 operations that do not specify an address execute, relative to 1042 each other, in program order. 1043 However, because of this erratum, an L2 set/way cache maintenance 1044 operation can overtake an L1 set/way cache maintenance operation. 1045 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1046 r0p4, r0p5. 1047 1048endmenu 1049 1050menu "Kernel Features" 1051 1052config HAVE_SMP 1053 bool 1054 help 1055 This option should be selected by machines which have an SMP- 1056 capable CPU. 1057 1058 The only effect of this option is to make the SMP-related 1059 options available to the user for configuration. 1060 1061config SMP 1062 bool "Symmetric Multi-Processing" 1063 depends on CPU_V6K || CPU_V7 1064 depends on HAVE_SMP 1065 depends on MMU || ARM_MPU 1066 select IRQ_WORK 1067 help 1068 This enables support for systems with more than one CPU. If you have 1069 a system with only one CPU, say N. If you have a system with more 1070 than one CPU, say Y. 1071 1072 If you say N here, the kernel will run on uni- and multiprocessor 1073 machines, but will use only one CPU of a multiprocessor machine. If 1074 you say Y here, the kernel will run on many, but not all, 1075 uniprocessor machines. On a uniprocessor machine, the kernel 1076 will run faster if you say N here. 1077 1078 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1079 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1080 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1081 1082 If you don't know what to do here, say N. 1083 1084config SMP_ON_UP 1085 bool "Allow booting SMP kernel on uniprocessor systems" 1086 depends on SMP && !XIP_KERNEL && MMU 1087 default y 1088 help 1089 SMP kernels contain instructions which fail on non-SMP processors. 1090 Enabling this option allows the kernel to modify itself to make 1091 these instructions safe. Disabling it allows about 1K of space 1092 savings. 1093 1094 If you don't know what to do here, say Y. 1095 1096 1097config CURRENT_POINTER_IN_TPIDRURO 1098 def_bool y 1099 depends on CPU_32v6K && !CPU_V6 1100 1101config IRQSTACKS 1102 def_bool y 1103 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1104 select HAVE_SOFTIRQ_ON_OWN_STACK 1105 1106config ARM_CPU_TOPOLOGY 1107 bool "Support cpu topology definition" 1108 depends on SMP && CPU_V7 1109 default y 1110 help 1111 Support ARM cpu topology definition. The MPIDR register defines 1112 affinity between processors which is then used to describe the cpu 1113 topology of an ARM System. 1114 1115config SCHED_MC 1116 bool "Multi-core scheduler support" 1117 depends on ARM_CPU_TOPOLOGY 1118 help 1119 Multi-core scheduler support improves the CPU scheduler's decision 1120 making when dealing with multi-core CPU chips at a cost of slightly 1121 increased overhead in some places. If unsure say N here. 1122 1123config SCHED_SMT 1124 bool "SMT scheduler support" 1125 depends on ARM_CPU_TOPOLOGY 1126 help 1127 Improves the CPU scheduler's decision making when dealing with 1128 MultiThreading at a cost of slightly increased overhead in some 1129 places. If unsure say N here. 1130 1131config HAVE_ARM_SCU 1132 bool 1133 help 1134 This option enables support for the ARM snoop control unit 1135 1136config HAVE_ARM_ARCH_TIMER 1137 bool "Architected timer support" 1138 depends on CPU_V7 1139 select ARM_ARCH_TIMER 1140 help 1141 This option enables support for the ARM architected timer 1142 1143config HAVE_ARM_TWD 1144 bool 1145 help 1146 This options enables support for the ARM timer and watchdog unit 1147 1148config MCPM 1149 bool "Multi-Cluster Power Management" 1150 depends on CPU_V7 && SMP 1151 help 1152 This option provides the common power management infrastructure 1153 for (multi-)cluster based systems, such as big.LITTLE based 1154 systems. 1155 1156config MCPM_QUAD_CLUSTER 1157 bool 1158 depends on MCPM 1159 help 1160 To avoid wasting resources unnecessarily, MCPM only supports up 1161 to 2 clusters by default. 1162 Platforms with 3 or 4 clusters that use MCPM must select this 1163 option to allow the additional clusters to be managed. 1164 1165config BIG_LITTLE 1166 bool "big.LITTLE support (Experimental)" 1167 depends on CPU_V7 && SMP 1168 select MCPM 1169 help 1170 This option enables support selections for the big.LITTLE 1171 system architecture. 1172 1173config BL_SWITCHER 1174 bool "big.LITTLE switcher support" 1175 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1176 select CPU_PM 1177 help 1178 The big.LITTLE "switcher" provides the core functionality to 1179 transparently handle transition between a cluster of A15's 1180 and a cluster of A7's in a big.LITTLE system. 1181 1182config BL_SWITCHER_DUMMY_IF 1183 tristate "Simple big.LITTLE switcher user interface" 1184 depends on BL_SWITCHER && DEBUG_KERNEL 1185 help 1186 This is a simple and dummy char dev interface to control 1187 the big.LITTLE switcher core code. It is meant for 1188 debugging purposes only. 1189 1190choice 1191 prompt "Memory split" 1192 depends on MMU 1193 default VMSPLIT_3G 1194 help 1195 Select the desired split between kernel and user memory. 1196 1197 If you are not absolutely sure what you are doing, leave this 1198 option alone! 1199 1200 config VMSPLIT_3G 1201 bool "3G/1G user/kernel split" 1202 config VMSPLIT_3G_OPT 1203 depends on !ARM_LPAE 1204 bool "3G/1G user/kernel split (for full 1G low memory)" 1205 config VMSPLIT_2G 1206 bool "2G/2G user/kernel split" 1207 config VMSPLIT_1G 1208 bool "1G/3G user/kernel split" 1209endchoice 1210 1211config PAGE_OFFSET 1212 hex 1213 default PHYS_OFFSET if !MMU 1214 default 0x40000000 if VMSPLIT_1G 1215 default 0x80000000 if VMSPLIT_2G 1216 default 0xB0000000 if VMSPLIT_3G_OPT 1217 default 0xC0000000 1218 1219config KASAN_SHADOW_OFFSET 1220 hex 1221 depends on KASAN 1222 default 0x1f000000 if PAGE_OFFSET=0x40000000 1223 default 0x5f000000 if PAGE_OFFSET=0x80000000 1224 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1225 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1226 default 0xffffffff 1227 1228config NR_CPUS 1229 int "Maximum number of CPUs (2-32)" 1230 range 2 16 if DEBUG_KMAP_LOCAL 1231 range 2 32 if !DEBUG_KMAP_LOCAL 1232 depends on SMP 1233 default "4" 1234 help 1235 The maximum number of CPUs that the kernel can support. 1236 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1237 debugging is enabled, which uses half of the per-CPU fixmap 1238 slots as guard regions. 1239 1240config HOTPLUG_CPU 1241 bool "Support for hot-pluggable CPUs" 1242 depends on SMP 1243 select GENERIC_IRQ_MIGRATION 1244 help 1245 Say Y here to experiment with turning CPUs off and on. CPUs 1246 can be controlled through /sys/devices/system/cpu. 1247 1248config ARM_PSCI 1249 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1250 depends on HAVE_ARM_SMCCC 1251 select ARM_PSCI_FW 1252 help 1253 Say Y here if you want Linux to communicate with system firmware 1254 implementing the PSCI specification for CPU-centric power 1255 management operations described in ARM document number ARM DEN 1256 0022A ("Power State Coordination Interface System Software on 1257 ARM processors"). 1258 1259# The GPIO number here must be sorted by descending number. In case of 1260# a multiplatform kernel, we just want the highest value required by the 1261# selected platforms. 1262config ARCH_NR_GPIO 1263 int 1264 default 2048 if ARCH_INTEL_SOCFPGA 1265 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1266 ARCH_ZYNQ || ARCH_ASPEED 1267 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1268 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1269 default 416 if ARCH_SUNXI 1270 default 392 if ARCH_U8500 1271 default 352 if ARCH_VT8500 1272 default 288 if ARCH_ROCKCHIP 1273 default 264 if MACH_H4700 1274 default 0 1275 help 1276 Maximum number of GPIOs in the system. 1277 1278 If unsure, leave the default value. 1279 1280config HZ_FIXED 1281 int 1282 default 128 if SOC_AT91RM9200 1283 default 0 1284 1285choice 1286 depends on HZ_FIXED = 0 1287 prompt "Timer frequency" 1288 1289config HZ_100 1290 bool "100 Hz" 1291 1292config HZ_200 1293 bool "200 Hz" 1294 1295config HZ_250 1296 bool "250 Hz" 1297 1298config HZ_300 1299 bool "300 Hz" 1300 1301config HZ_500 1302 bool "500 Hz" 1303 1304config HZ_1000 1305 bool "1000 Hz" 1306 1307endchoice 1308 1309config HZ 1310 int 1311 default HZ_FIXED if HZ_FIXED != 0 1312 default 100 if HZ_100 1313 default 200 if HZ_200 1314 default 250 if HZ_250 1315 default 300 if HZ_300 1316 default 500 if HZ_500 1317 default 1000 1318 1319config SCHED_HRTICK 1320 def_bool HIGH_RES_TIMERS 1321 1322config THUMB2_KERNEL 1323 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1324 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1325 default y if CPU_THUMBONLY 1326 select ARM_UNWIND 1327 help 1328 By enabling this option, the kernel will be compiled in 1329 Thumb-2 mode. 1330 1331 If unsure, say N. 1332 1333config ARM_PATCH_IDIV 1334 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1335 depends on CPU_32v7 && !XIP_KERNEL 1336 default y 1337 help 1338 The ARM compiler inserts calls to __aeabi_idiv() and 1339 __aeabi_uidiv() when it needs to perform division on signed 1340 and unsigned integers. Some v7 CPUs have support for the sdiv 1341 and udiv instructions that can be used to implement those 1342 functions. 1343 1344 Enabling this option allows the kernel to modify itself to 1345 replace the first two instructions of these library functions 1346 with the sdiv or udiv plus "bx lr" instructions when the CPU 1347 it is running on supports them. Typically this will be faster 1348 and less power intensive than running the original library 1349 code to do integer division. 1350 1351config AEABI 1352 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1353 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1354 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1355 help 1356 This option allows for the kernel to be compiled using the latest 1357 ARM ABI (aka EABI). This is only useful if you are using a user 1358 space environment that is also compiled with EABI. 1359 1360 Since there are major incompatibilities between the legacy ABI and 1361 EABI, especially with regard to structure member alignment, this 1362 option also changes the kernel syscall calling convention to 1363 disambiguate both ABIs and allow for backward compatibility support 1364 (selected with CONFIG_OABI_COMPAT). 1365 1366 To use this you need GCC version 4.0.0 or later. 1367 1368config OABI_COMPAT 1369 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1370 depends on AEABI && !THUMB2_KERNEL 1371 help 1372 This option preserves the old syscall interface along with the 1373 new (ARM EABI) one. It also provides a compatibility layer to 1374 intercept syscalls that have structure arguments which layout 1375 in memory differs between the legacy ABI and the new ARM EABI 1376 (only for non "thumb" binaries). This option adds a tiny 1377 overhead to all syscalls and produces a slightly larger kernel. 1378 1379 The seccomp filter system will not be available when this is 1380 selected, since there is no way yet to sensibly distinguish 1381 between calling conventions during filtering. 1382 1383 If you know you'll be using only pure EABI user space then you 1384 can say N here. If this option is not selected and you attempt 1385 to execute a legacy ABI binary then the result will be 1386 UNPREDICTABLE (in fact it can be predicted that it won't work 1387 at all). If in doubt say N. 1388 1389config ARCH_SELECT_MEMORY_MODEL 1390 bool 1391 1392config ARCH_FLATMEM_ENABLE 1393 bool 1394 1395config ARCH_SPARSEMEM_ENABLE 1396 bool 1397 select SPARSEMEM_STATIC if SPARSEMEM 1398 1399config HIGHMEM 1400 bool "High Memory Support" 1401 depends on MMU 1402 select KMAP_LOCAL 1403 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1404 help 1405 The address space of ARM processors is only 4 Gigabytes large 1406 and it has to accommodate user address space, kernel address 1407 space as well as some memory mapped IO. That means that, if you 1408 have a large amount of physical memory and/or IO, not all of the 1409 memory can be "permanently mapped" by the kernel. The physical 1410 memory that is not permanently mapped is called "high memory". 1411 1412 Depending on the selected kernel/user memory split, minimum 1413 vmalloc space and actual amount of RAM, you may not need this 1414 option which should result in a slightly faster kernel. 1415 1416 If unsure, say n. 1417 1418config HIGHPTE 1419 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1420 depends on HIGHMEM 1421 default y 1422 help 1423 The VM uses one page of physical memory for each page table. 1424 For systems with a lot of processes, this can use a lot of 1425 precious low memory, eventually leading to low memory being 1426 consumed by page tables. Setting this option will allow 1427 user-space 2nd level page tables to reside in high memory. 1428 1429config CPU_SW_DOMAIN_PAN 1430 bool "Enable use of CPU domains to implement privileged no-access" 1431 depends on MMU && !ARM_LPAE 1432 default y 1433 help 1434 Increase kernel security by ensuring that normal kernel accesses 1435 are unable to access userspace addresses. This can help prevent 1436 use-after-free bugs becoming an exploitable privilege escalation 1437 by ensuring that magic values (such as LIST_POISON) will always 1438 fault when dereferenced. 1439 1440 CPUs with low-vector mappings use a best-efforts implementation. 1441 Their lower 1MB needs to remain accessible for the vectors, but 1442 the remainder of userspace will become appropriately inaccessible. 1443 1444config HW_PERF_EVENTS 1445 def_bool y 1446 depends on ARM_PMU 1447 1448config ARM_MODULE_PLTS 1449 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1450 depends on MODULES 1451 default y 1452 help 1453 Allocate PLTs when loading modules so that jumps and calls whose 1454 targets are too far away for their relative offsets to be encoded 1455 in the instructions themselves can be bounced via veneers in the 1456 module's PLT. This allows modules to be allocated in the generic 1457 vmalloc area after the dedicated module memory area has been 1458 exhausted. The modules will use slightly more memory, but after 1459 rounding up to page size, the actual memory footprint is usually 1460 the same. 1461 1462 Disabling this is usually safe for small single-platform 1463 configurations. If unsure, say y. 1464 1465config FORCE_MAX_ZONEORDER 1466 int "Maximum zone order" 1467 default "12" if SOC_AM33XX 1468 default "9" if SA1111 1469 default "11" 1470 help 1471 The kernel memory allocator divides physically contiguous memory 1472 blocks into "zones", where each zone is a power of two number of 1473 pages. This option selects the largest power of two that the kernel 1474 keeps in the memory allocator. If you need to allocate very large 1475 blocks of physically contiguous memory, then you may need to 1476 increase this value. 1477 1478 This config option is actually maximum order plus one. For example, 1479 a value of 11 means that the largest free memory block is 2^10 pages. 1480 1481config ALIGNMENT_TRAP 1482 def_bool CPU_CP15_MMU 1483 select HAVE_PROC_CPU if PROC_FS 1484 help 1485 ARM processors cannot fetch/store information which is not 1486 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1487 address divisible by 4. On 32-bit ARM processors, these non-aligned 1488 fetch/store instructions will be emulated in software if you say 1489 here, which has a severe performance impact. This is necessary for 1490 correct operation of some network protocols. With an IP-only 1491 configuration it is safe to say N, otherwise say Y. 1492 1493config UACCESS_WITH_MEMCPY 1494 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1495 depends on MMU 1496 default y if CPU_FEROCEON 1497 help 1498 Implement faster copy_to_user and clear_user methods for CPU 1499 cores where a 8-word STM instruction give significantly higher 1500 memory write throughput than a sequence of individual 32bit stores. 1501 1502 A possible side effect is a slight increase in scheduling latency 1503 between threads sharing the same address space if they invoke 1504 such copy operations with large buffers. 1505 1506 However, if the CPU data cache is using a write-allocate mode, 1507 this option is unlikely to provide any performance gain. 1508 1509config PARAVIRT 1510 bool "Enable paravirtualization code" 1511 help 1512 This changes the kernel so it can modify itself when it is run 1513 under a hypervisor, potentially improving performance significantly 1514 over full virtualization. 1515 1516config PARAVIRT_TIME_ACCOUNTING 1517 bool "Paravirtual steal time accounting" 1518 select PARAVIRT 1519 help 1520 Select this option to enable fine granularity task steal time 1521 accounting. Time spent executing other tasks in parallel with 1522 the current vCPU is discounted from the vCPU power. To account for 1523 that, there can be a small performance impact. 1524 1525 If in doubt, say N here. 1526 1527config XEN_DOM0 1528 def_bool y 1529 depends on XEN 1530 1531config XEN 1532 bool "Xen guest support on ARM" 1533 depends on ARM && AEABI && OF 1534 depends on CPU_V7 && !CPU_V6 1535 depends on !GENERIC_ATOMIC64 1536 depends on MMU 1537 select ARCH_DMA_ADDR_T_64BIT 1538 select ARM_PSCI 1539 select SWIOTLB 1540 select SWIOTLB_XEN 1541 select PARAVIRT 1542 help 1543 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1544 1545config CC_HAVE_STACKPROTECTOR_TLS 1546 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1547 1548config STACKPROTECTOR_PER_TASK 1549 bool "Use a unique stack canary value for each task" 1550 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1551 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1552 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1553 default y 1554 help 1555 Due to the fact that GCC uses an ordinary symbol reference from 1556 which to load the value of the stack canary, this value can only 1557 change at reboot time on SMP systems, and all tasks running in the 1558 kernel's address space are forced to use the same canary value for 1559 the entire duration that the system is up. 1560 1561 Enable this option to switch to a different method that uses a 1562 different canary value for each task. 1563 1564endmenu 1565 1566menu "Boot options" 1567 1568config USE_OF 1569 bool "Flattened Device Tree support" 1570 select IRQ_DOMAIN 1571 select OF 1572 help 1573 Include support for flattened device tree machine descriptions. 1574 1575config ATAGS 1576 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1577 default y 1578 help 1579 This is the traditional way of passing data to the kernel at boot 1580 time. If you are solely relying on the flattened device tree (or 1581 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1582 to remove ATAGS support from your kernel binary. If unsure, 1583 leave this to y. 1584 1585config DEPRECATED_PARAM_STRUCT 1586 bool "Provide old way to pass kernel parameters" 1587 depends on ATAGS 1588 help 1589 This was deprecated in 2001 and announced to live on for 5 years. 1590 Some old boot loaders still use this way. 1591 1592# Compressed boot loader in ROM. Yes, we really want to ask about 1593# TEXT and BSS so we preserve their values in the config files. 1594config ZBOOT_ROM_TEXT 1595 hex "Compressed ROM boot loader base address" 1596 default 0x0 1597 help 1598 The physical address at which the ROM-able zImage is to be 1599 placed in the target. Platforms which normally make use of 1600 ROM-able zImage formats normally set this to a suitable 1601 value in their defconfig file. 1602 1603 If ZBOOT_ROM is not enabled, this has no effect. 1604 1605config ZBOOT_ROM_BSS 1606 hex "Compressed ROM boot loader BSS address" 1607 default 0x0 1608 help 1609 The base address of an area of read/write memory in the target 1610 for the ROM-able zImage which must be available while the 1611 decompressor is running. It must be large enough to hold the 1612 entire decompressed kernel plus an additional 128 KiB. 1613 Platforms which normally make use of ROM-able zImage formats 1614 normally set this to a suitable value in their defconfig file. 1615 1616 If ZBOOT_ROM is not enabled, this has no effect. 1617 1618config ZBOOT_ROM 1619 bool "Compressed boot loader in ROM/flash" 1620 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1621 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1622 help 1623 Say Y here if you intend to execute your compressed kernel image 1624 (zImage) directly from ROM or flash. If unsure, say N. 1625 1626config ARM_APPENDED_DTB 1627 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1628 depends on OF 1629 help 1630 With this option, the boot code will look for a device tree binary 1631 (DTB) appended to zImage 1632 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1633 1634 This is meant as a backward compatibility convenience for those 1635 systems with a bootloader that can't be upgraded to accommodate 1636 the documented boot protocol using a device tree. 1637 1638 Beware that there is very little in terms of protection against 1639 this option being confused by leftover garbage in memory that might 1640 look like a DTB header after a reboot if no actual DTB is appended 1641 to zImage. Do not leave this option active in a production kernel 1642 if you don't intend to always append a DTB. Proper passing of the 1643 location into r2 of a bootloader provided DTB is always preferable 1644 to this option. 1645 1646config ARM_ATAG_DTB_COMPAT 1647 bool "Supplement the appended DTB with traditional ATAG information" 1648 depends on ARM_APPENDED_DTB 1649 help 1650 Some old bootloaders can't be updated to a DTB capable one, yet 1651 they provide ATAGs with memory configuration, the ramdisk address, 1652 the kernel cmdline string, etc. Such information is dynamically 1653 provided by the bootloader and can't always be stored in a static 1654 DTB. To allow a device tree enabled kernel to be used with such 1655 bootloaders, this option allows zImage to extract the information 1656 from the ATAG list and store it at run time into the appended DTB. 1657 1658choice 1659 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1660 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1661 1662config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1663 bool "Use bootloader kernel arguments if available" 1664 help 1665 Uses the command-line options passed by the boot loader instead of 1666 the device tree bootargs property. If the boot loader doesn't provide 1667 any, the device tree bootargs property will be used. 1668 1669config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1670 bool "Extend with bootloader kernel arguments" 1671 help 1672 The command-line arguments provided by the boot loader will be 1673 appended to the the device tree bootargs property. 1674 1675endchoice 1676 1677config CMDLINE 1678 string "Default kernel command string" 1679 default "" 1680 help 1681 On some architectures (e.g. CATS), there is currently no way 1682 for the boot loader to pass arguments to the kernel. For these 1683 architectures, you should supply some command-line options at build 1684 time by entering them here. As a minimum, you should specify the 1685 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1686 1687choice 1688 prompt "Kernel command line type" if CMDLINE != "" 1689 default CMDLINE_FROM_BOOTLOADER 1690 depends on ATAGS 1691 1692config CMDLINE_FROM_BOOTLOADER 1693 bool "Use bootloader kernel arguments if available" 1694 help 1695 Uses the command-line options passed by the boot loader. If 1696 the boot loader doesn't provide any, the default kernel command 1697 string provided in CMDLINE will be used. 1698 1699config CMDLINE_EXTEND 1700 bool "Extend bootloader kernel arguments" 1701 help 1702 The command-line arguments provided by the boot loader will be 1703 appended to the default kernel command string. 1704 1705config CMDLINE_FORCE 1706 bool "Always use the default kernel command string" 1707 help 1708 Always use the default kernel command string, even if the boot 1709 loader passes other arguments to the kernel. 1710 This is useful if you cannot or don't want to change the 1711 command-line options your boot loader passes to the kernel. 1712endchoice 1713 1714config XIP_KERNEL 1715 bool "Kernel Execute-In-Place from ROM" 1716 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1717 help 1718 Execute-In-Place allows the kernel to run from non-volatile storage 1719 directly addressable by the CPU, such as NOR flash. This saves RAM 1720 space since the text section of the kernel is not loaded from flash 1721 to RAM. Read-write sections, such as the data section and stack, 1722 are still copied to RAM. The XIP kernel is not compressed since 1723 it has to run directly from flash, so it will take more space to 1724 store it. The flash address used to link the kernel object files, 1725 and for storing it, is configuration dependent. Therefore, if you 1726 say Y here, you must know the proper physical address where to 1727 store the kernel image depending on your own flash memory usage. 1728 1729 Also note that the make target becomes "make xipImage" rather than 1730 "make zImage" or "make Image". The final kernel binary to put in 1731 ROM memory will be arch/arm/boot/xipImage. 1732 1733 If unsure, say N. 1734 1735config XIP_PHYS_ADDR 1736 hex "XIP Kernel Physical Location" 1737 depends on XIP_KERNEL 1738 default "0x00080000" 1739 help 1740 This is the physical address in your flash memory the kernel will 1741 be linked for and stored to. This address is dependent on your 1742 own flash usage. 1743 1744config XIP_DEFLATED_DATA 1745 bool "Store kernel .data section compressed in ROM" 1746 depends on XIP_KERNEL 1747 select ZLIB_INFLATE 1748 help 1749 Before the kernel is actually executed, its .data section has to be 1750 copied to RAM from ROM. This option allows for storing that data 1751 in compressed form and decompressed to RAM rather than merely being 1752 copied, saving some precious ROM space. A possible drawback is a 1753 slightly longer boot delay. 1754 1755config KEXEC 1756 bool "Kexec system call (EXPERIMENTAL)" 1757 depends on (!SMP || PM_SLEEP_SMP) 1758 depends on MMU 1759 select KEXEC_CORE 1760 help 1761 kexec is a system call that implements the ability to shutdown your 1762 current kernel, and to start another kernel. It is like a reboot 1763 but it is independent of the system firmware. And like a reboot 1764 you can start any kernel with it, not just Linux. 1765 1766 It is an ongoing process to be certain the hardware in a machine 1767 is properly shutdown, so do not be surprised if this code does not 1768 initially work for you. 1769 1770config ATAGS_PROC 1771 bool "Export atags in procfs" 1772 depends on ATAGS && KEXEC 1773 default y 1774 help 1775 Should the atags used to boot the kernel be exported in an "atags" 1776 file in procfs. Useful with kexec. 1777 1778config CRASH_DUMP 1779 bool "Build kdump crash kernel (EXPERIMENTAL)" 1780 help 1781 Generate crash dump after being started by kexec. This should 1782 be normally only set in special crash dump kernels which are 1783 loaded in the main kernel with kexec-tools into a specially 1784 reserved region and then later executed after a crash by 1785 kdump/kexec. The crash dump kernel must be compiled to a 1786 memory address not used by the main kernel 1787 1788 For more details see Documentation/admin-guide/kdump/kdump.rst 1789 1790config AUTO_ZRELADDR 1791 bool "Auto calculation of the decompressed kernel image address" 1792 help 1793 ZRELADDR is the physical address where the decompressed kernel 1794 image will be placed. If AUTO_ZRELADDR is selected, the address 1795 will be determined at run-time, either by masking the current IP 1796 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1797 This assumes the zImage being placed in the first 128MB from 1798 start of memory. 1799 1800config EFI_STUB 1801 bool 1802 1803config EFI 1804 bool "UEFI runtime support" 1805 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1806 select UCS2_STRING 1807 select EFI_PARAMS_FROM_FDT 1808 select EFI_STUB 1809 select EFI_GENERIC_STUB 1810 select EFI_RUNTIME_WRAPPERS 1811 help 1812 This option provides support for runtime services provided 1813 by UEFI firmware (such as non-volatile variables, realtime 1814 clock, and platform reset). A UEFI stub is also provided to 1815 allow the kernel to be booted as an EFI application. This 1816 is only useful for kernels that may run on systems that have 1817 UEFI firmware. 1818 1819config DMI 1820 bool "Enable support for SMBIOS (DMI) tables" 1821 depends on EFI 1822 default y 1823 help 1824 This enables SMBIOS/DMI feature for systems. 1825 1826 This option is only useful on systems that have UEFI firmware. 1827 However, even with this option, the resultant kernel should 1828 continue to boot on existing non-UEFI platforms. 1829 1830 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1831 i.e., the the practice of identifying the platform via DMI to 1832 decide whether certain workarounds for buggy hardware and/or 1833 firmware need to be enabled. This would require the DMI subsystem 1834 to be enabled much earlier than we do on ARM, which is non-trivial. 1835 1836endmenu 1837 1838menu "CPU Power Management" 1839 1840source "drivers/cpufreq/Kconfig" 1841 1842source "drivers/cpuidle/Kconfig" 1843 1844endmenu 1845 1846menu "Floating point emulation" 1847 1848comment "At least one emulation must be selected" 1849 1850config FPE_NWFPE 1851 bool "NWFPE math emulation" 1852 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1853 help 1854 Say Y to include the NWFPE floating point emulator in the kernel. 1855 This is necessary to run most binaries. Linux does not currently 1856 support floating point hardware so you need to say Y here even if 1857 your machine has an FPA or floating point co-processor podule. 1858 1859 You may say N here if you are going to load the Acorn FPEmulator 1860 early in the bootup. 1861 1862config FPE_NWFPE_XP 1863 bool "Support extended precision" 1864 depends on FPE_NWFPE 1865 help 1866 Say Y to include 80-bit support in the kernel floating-point 1867 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1868 Note that gcc does not generate 80-bit operations by default, 1869 so in most cases this option only enlarges the size of the 1870 floating point emulator without any good reason. 1871 1872 You almost surely want to say N here. 1873 1874config FPE_FASTFPE 1875 bool "FastFPE math emulation (EXPERIMENTAL)" 1876 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1877 help 1878 Say Y here to include the FAST floating point emulator in the kernel. 1879 This is an experimental much faster emulator which now also has full 1880 precision for the mantissa. It does not support any exceptions. 1881 It is very simple, and approximately 3-6 times faster than NWFPE. 1882 1883 It should be sufficient for most programs. It may be not suitable 1884 for scientific calculations, but you have to check this for yourself. 1885 If you do not feel you need a faster FP emulation you should better 1886 choose NWFPE. 1887 1888config VFP 1889 bool "VFP-format floating point maths" 1890 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1891 help 1892 Say Y to include VFP support code in the kernel. This is needed 1893 if your hardware includes a VFP unit. 1894 1895 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1896 release notes and additional status information. 1897 1898 Say N if your target does not have VFP hardware. 1899 1900config VFPv3 1901 bool 1902 depends on VFP 1903 default y if CPU_V7 1904 1905config NEON 1906 bool "Advanced SIMD (NEON) Extension support" 1907 depends on VFPv3 && CPU_V7 1908 help 1909 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1910 Extension. 1911 1912config KERNEL_MODE_NEON 1913 bool "Support for NEON in kernel mode" 1914 depends on NEON && AEABI 1915 help 1916 Say Y to include support for NEON in kernel mode. 1917 1918endmenu 1919 1920menu "Power management options" 1921 1922source "kernel/power/Kconfig" 1923 1924config ARCH_SUSPEND_POSSIBLE 1925 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1926 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1927 def_bool y 1928 1929config ARM_CPU_SUSPEND 1930 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1931 depends on ARCH_SUSPEND_POSSIBLE 1932 1933config ARCH_HIBERNATION_POSSIBLE 1934 bool 1935 depends on MMU 1936 default y if ARCH_SUSPEND_POSSIBLE 1937 1938endmenu 1939 1940if CRYPTO 1941source "arch/arm/crypto/Kconfig" 1942endif 1943 1944source "arch/arm/Kconfig.assembler" 1945