1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_REMAP if MMU 45 select EDAC_SUPPORT 46 select EDAC_ATOMIC_SCRUB 47 select GENERIC_ALLOCATOR 48 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 49 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 50 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 51 select GENERIC_CPU_AUTOPROBE 52 select GENERIC_EARLY_IOREMAP 53 select GENERIC_IDLE_POLL_SETUP 54 select GENERIC_IRQ_PROBE 55 select GENERIC_IRQ_SHOW 56 select GENERIC_IRQ_SHOW_LEVEL 57 select GENERIC_PCI_IOMAP 58 select GENERIC_SCHED_CLOCK 59 select GENERIC_SMP_IDLE_THREAD 60 select GENERIC_STRNCPY_FROM_USER 61 select GENERIC_STRNLEN_USER 62 select HANDLE_DOMAIN_IRQ 63 select HARDIRQS_SW_RESEND 64 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 65 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 66 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_MMAP_RND_BITS if MMU 69 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 71 select HAVE_ARCH_TRACEHOOK 72 select HAVE_ARM_SMCCC if CPU_V7 73 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 74 select HAVE_CONTEXT_TRACKING 75 select HAVE_COPY_THREAD_TLS 76 select HAVE_C_RECORDMCOUNT 77 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 78 select HAVE_DMA_CONTIGUOUS if MMU 79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 82 select HAVE_EXIT_THREAD 83 select HAVE_FAST_GUP if ARM_LPAE 84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 87 select HAVE_GCC_PLUGINS 88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 89 select HAVE_IDE if PCI || ISA || PCMCIA 90 select HAVE_IRQ_TIME_ACCOUNTING 91 select HAVE_KERNEL_GZIP 92 select HAVE_KERNEL_LZ4 93 select HAVE_KERNEL_LZMA 94 select HAVE_KERNEL_LZO 95 select HAVE_KERNEL_XZ 96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 97 select HAVE_KRETPROBES if HAVE_KPROBES 98 select HAVE_MOD_ARCH_SPECIFIC 99 select HAVE_NMI 100 select HAVE_OPROFILE if HAVE_PERF_EVENTS 101 select HAVE_OPTPROBES if !THUMB2_KERNEL 102 select HAVE_PERF_EVENTS 103 select HAVE_PERF_REGS 104 select HAVE_PERF_USER_STACK_DUMP 105 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 106 select HAVE_REGS_AND_STACK_ACCESS_API 107 select HAVE_RSEQ 108 select HAVE_STACKPROTECTOR 109 select HAVE_SYSCALL_TRACEPOINTS 110 select HAVE_UID16 111 select HAVE_VIRT_CPU_ACCOUNTING_GEN 112 select IRQ_FORCED_THREADING 113 select MODULES_USE_ELF_REL 114 select NEED_DMA_MAP_STATE 115 select OF_EARLY_FLATTREE if OF 116 select OLD_SIGACTION 117 select OLD_SIGSUSPEND3 118 select PCI_SYSCALL if PCI 119 select PERF_USE_VMALLOC 120 select RTC_LIB 121 select SYS_SUPPORTS_APM_EMULATION 122 # Above selects are sorted alphabetically; please add new ones 123 # according to that. Thanks. 124 help 125 The ARM series is a line of low-power-consumption RISC chip designs 126 licensed by ARM Ltd and targeted at embedded applications and 127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 128 manufactured, but legacy ARM-based PC hardware remains popular in 129 Europe. There is an ARM Linux project with a web page at 130 <http://www.arm.linux.org.uk/>. 131 132config ARM_HAS_SG_CHAIN 133 bool 134 135config ARM_DMA_USE_IOMMU 136 bool 137 select ARM_HAS_SG_CHAIN 138 select NEED_SG_DMA_LENGTH 139 140if ARM_DMA_USE_IOMMU 141 142config ARM_DMA_IOMMU_ALIGNMENT 143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 144 range 4 9 145 default 8 146 help 147 DMA mapping framework by default aligns all buffers to the smallest 148 PAGE_SIZE order which is greater than or equal to the requested buffer 149 size. This works well for buffers up to a few hundreds kilobytes, but 150 for larger buffers it just a waste of address space. Drivers which has 151 relatively small addressing window (like 64Mib) might run out of 152 virtual space with just a few allocations. 153 154 With this parameter you can specify the maximum PAGE_SIZE order for 155 DMA IOMMU buffers. Larger buffers will be aligned only to this 156 specified order. The order is expressed as a power of two multiplied 157 by the PAGE_SIZE. 158 159endif 160 161config SYS_SUPPORTS_APM_EMULATION 162 bool 163 164config HAVE_TCM 165 bool 166 select GENERIC_ALLOCATOR 167 168config HAVE_PROC_CPU 169 bool 170 171config NO_IOPORT_MAP 172 bool 173 174config SBUS 175 bool 176 177config STACKTRACE_SUPPORT 178 bool 179 default y 180 181config LOCKDEP_SUPPORT 182 bool 183 default y 184 185config TRACE_IRQFLAGS_SUPPORT 186 bool 187 default !CPU_V7M 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 16MB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_EBSA110 || \ 268 ARCH_FOOTBRIDGE || \ 269 ARCH_INTEGRATOR || \ 270 ARCH_REALVIEW 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x20000000 if ARCH_S5PV210 273 default 0xc0000000 if ARCH_SA1100 274 help 275 Please provide the physical address corresponding to the 276 location of main memory in your system. 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config PGTABLE_LEVELS 283 int 284 default 3 if ARM_LPAE 285 default 2 286 287menu "System Type" 288 289config MMU 290 bool "MMU-based Paged Memory Management Support" 291 default y 292 help 293 Select if you want MMU-based virtualised addressing space 294 support by paged memory management. If unsure, say 'Y'. 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 8 298 299config ARCH_MMAP_RND_BITS_MAX 300 default 14 if PAGE_OFFSET=0x40000000 301 default 15 if PAGE_OFFSET=0x80000000 302 default 16 303 304# 305# The "ARM system type" choice list is ordered alphabetically by option 306# text. Please add new entries in the option alphabetic order. 307# 308choice 309 prompt "ARM system type" 310 default ARM_SINGLE_ARMV7M if !MMU 311 default ARCH_MULTIPLATFORM if MMU 312 313config ARCH_MULTIPLATFORM 314 bool "Allow multiple platforms to be selected" 315 depends on MMU 316 select ARCH_FLATMEM_ENABLE 317 select ARCH_SPARSEMEM_ENABLE 318 select ARCH_SELECT_MEMORY_MODEL 319 select ARM_HAS_SG_CHAIN 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select TIMER_OF 323 select COMMON_CLK 324 select GENERIC_CLOCKEVENTS 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select GENERIC_CLOCKEVENTS 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EBSA110 345 bool "EBSA-110" 346 select ARCH_USES_GETTIMEOFFSET 347 select CPU_SA110 348 select ISA 349 select NEED_MACH_IO_H 350 select NEED_MACH_MEMORY_H 351 select NO_IOPORT_MAP 352 help 353 This is an evaluation board for the StrongARM processor available 354 from Digital. It has limited hardware on-board, including an 355 Ethernet interface, two PCMCIA sockets, two serial ports and a 356 parallel port. 357 358config ARCH_EP93XX 359 bool "EP93xx-based" 360 select ARCH_SPARSEMEM_ENABLE 361 select ARM_AMBA 362 imply ARM_PATCH_PHYS_VIRT 363 select ARM_VIC 364 select AUTO_ZRELADDR 365 select CLKDEV_LOOKUP 366 select CLKSRC_MMIO 367 select CPU_ARM920T 368 select GENERIC_CLOCKEVENTS 369 select GPIOLIB 370 help 371 This enables support for the Cirrus EP93xx series of CPUs. 372 373config ARCH_FOOTBRIDGE 374 bool "FootBridge" 375 select CPU_SA110 376 select FOOTBRIDGE 377 select GENERIC_CLOCKEVENTS 378 select HAVE_IDE 379 select NEED_MACH_IO_H if !MMU 380 select NEED_MACH_MEMORY_H 381 help 382 Support for systems based on the DC21285 companion chip 383 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 384 385config ARCH_IOP32X 386 bool "IOP32x-based" 387 depends on MMU 388 select CPU_XSCALE 389 select GPIO_IOP 390 select GPIOLIB 391 select NEED_RET_TO_USER 392 select FORCE_PCI 393 select PLAT_IOP 394 help 395 Support for Intel's 80219 and IOP32X (XScale) family of 396 processors. 397 398config ARCH_IXP4XX 399 bool "IXP4xx-based" 400 depends on MMU 401 select ARCH_HAS_DMA_SET_COHERENT_MASK 402 select ARCH_SUPPORTS_BIG_ENDIAN 403 select CPU_XSCALE 404 select DMABOUNCE if PCI 405 select GENERIC_CLOCKEVENTS 406 select GENERIC_IRQ_MULTI_HANDLER 407 select GPIO_IXP4XX 408 select GPIOLIB 409 select HAVE_PCI 410 select IXP4XX_IRQ 411 select IXP4XX_TIMER 412 select NEED_MACH_IO_H 413 select USB_EHCI_BIG_ENDIAN_DESC 414 select USB_EHCI_BIG_ENDIAN_MMIO 415 help 416 Support for Intel's IXP4XX (XScale) family of processors. 417 418config ARCH_DOVE 419 bool "Marvell Dove" 420 select CPU_PJ4 421 select GENERIC_CLOCKEVENTS 422 select GENERIC_IRQ_MULTI_HANDLER 423 select GPIOLIB 424 select HAVE_PCI 425 select MVEBU_MBUS 426 select PINCTRL 427 select PINCTRL_DOVE 428 select PLAT_ORION_LEGACY 429 select SPARSE_IRQ 430 select PM_GENERIC_DOMAINS if PM 431 help 432 Support for the Marvell Dove SoC 88AP510 433 434config ARCH_PXA 435 bool "PXA2xx/PXA3xx-based" 436 depends on MMU 437 select ARCH_MTD_XIP 438 select ARM_CPU_SUSPEND if PM 439 select AUTO_ZRELADDR 440 select COMMON_CLK 441 select CLKDEV_LOOKUP 442 select CLKSRC_PXA 443 select CLKSRC_MMIO 444 select TIMER_OF 445 select CPU_XSCALE if !CPU_XSC3 446 select GENERIC_CLOCKEVENTS 447 select GENERIC_IRQ_MULTI_HANDLER 448 select GPIO_PXA 449 select GPIOLIB 450 select HAVE_IDE 451 select IRQ_DOMAIN 452 select PLAT_PXA 453 select SPARSE_IRQ 454 help 455 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 456 457config ARCH_RPC 458 bool "RiscPC" 459 depends on MMU 460 select ARCH_ACORN 461 select ARCH_MAY_HAVE_PC_FDC 462 select ARCH_SPARSEMEM_ENABLE 463 select ARM_HAS_SG_CHAIN 464 select CPU_SA110 465 select FIQ 466 select HAVE_IDE 467 select HAVE_PATA_PLATFORM 468 select ISA_DMA_API 469 select NEED_MACH_IO_H 470 select NEED_MACH_MEMORY_H 471 select NO_IOPORT_MAP 472 help 473 On the Acorn Risc-PC, Linux can support the internal IDE disk and 474 CD-ROM interface, serial and parallel port, and the floppy drive. 475 476config ARCH_SA1100 477 bool "SA1100-based" 478 select ARCH_MTD_XIP 479 select ARCH_SPARSEMEM_ENABLE 480 select CLKDEV_LOOKUP 481 select CLKSRC_MMIO 482 select CLKSRC_PXA 483 select TIMER_OF if OF 484 select COMMON_CLK 485 select CPU_FREQ 486 select CPU_SA1100 487 select GENERIC_CLOCKEVENTS 488 select GENERIC_IRQ_MULTI_HANDLER 489 select GPIOLIB 490 select HAVE_IDE 491 select IRQ_DOMAIN 492 select ISA 493 select NEED_MACH_MEMORY_H 494 select SPARSE_IRQ 495 help 496 Support for StrongARM 11x0 based boards. 497 498config ARCH_S3C24XX 499 bool "Samsung S3C24XX SoCs" 500 select ATAGS 501 select CLKDEV_LOOKUP 502 select CLKSRC_SAMSUNG_PWM 503 select GENERIC_CLOCKEVENTS 504 select GPIO_SAMSUNG 505 select GPIOLIB 506 select GENERIC_IRQ_MULTI_HANDLER 507 select HAVE_S3C2410_I2C if I2C 508 select HAVE_S3C2410_WATCHDOG if WATCHDOG 509 select HAVE_S3C_RTC if RTC_CLASS 510 select NEED_MACH_IO_H 511 select SAMSUNG_ATAGS 512 select USE_OF 513 help 514 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 515 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 516 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 517 Samsung SMDK2410 development board (and derivatives). 518 519config ARCH_OMAP1 520 bool "TI OMAP1" 521 depends on MMU 522 select ARCH_HAS_HOLES_MEMORYMODEL 523 select ARCH_OMAP 524 select CLKDEV_LOOKUP 525 select CLKSRC_MMIO 526 select GENERIC_CLOCKEVENTS 527 select GENERIC_IRQ_CHIP 528 select GENERIC_IRQ_MULTI_HANDLER 529 select GPIOLIB 530 select HAVE_IDE 531 select IRQ_DOMAIN 532 select NEED_MACH_IO_H if PCCARD 533 select NEED_MACH_MEMORY_H 534 select SPARSE_IRQ 535 help 536 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 537 538endchoice 539 540menu "Multiple platform selection" 541 depends on ARCH_MULTIPLATFORM 542 543comment "CPU Core family selection" 544 545config ARCH_MULTI_V4 546 bool "ARMv4 based platforms (FA526)" 547 depends on !ARCH_MULTI_V6_V7 548 select ARCH_MULTI_V4_V5 549 select CPU_FA526 550 551config ARCH_MULTI_V4T 552 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 553 depends on !ARCH_MULTI_V6_V7 554 select ARCH_MULTI_V4_V5 555 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 556 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 557 CPU_ARM925T || CPU_ARM940T) 558 559config ARCH_MULTI_V5 560 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 561 depends on !ARCH_MULTI_V6_V7 562 select ARCH_MULTI_V4_V5 563 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 564 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 565 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 566 567config ARCH_MULTI_V4_V5 568 bool 569 570config ARCH_MULTI_V6 571 bool "ARMv6 based platforms (ARM11)" 572 select ARCH_MULTI_V6_V7 573 select CPU_V6K 574 575config ARCH_MULTI_V7 576 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 577 default y 578 select ARCH_MULTI_V6_V7 579 select CPU_V7 580 select HAVE_SMP 581 582config ARCH_MULTI_V6_V7 583 bool 584 select MIGHT_HAVE_CACHE_L2X0 585 586config ARCH_MULTI_CPU_AUTO 587 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 588 select ARCH_MULTI_V5 589 590endmenu 591 592config ARCH_VIRT 593 bool "Dummy Virtual Machine" 594 depends on ARCH_MULTI_V7 595 select ARM_AMBA 596 select ARM_GIC 597 select ARM_GIC_V2M if PCI 598 select ARM_GIC_V3 599 select ARM_GIC_V3_ITS if PCI 600 select ARM_PSCI 601 select HAVE_ARM_ARCH_TIMER 602 select ARCH_SUPPORTS_BIG_ENDIAN 603 604# 605# This is sorted alphabetically by mach-* pathname. However, plat-* 606# Kconfigs may be included either alphabetically (according to the 607# plat- suffix) or along side the corresponding mach-* source. 608# 609source "arch/arm/mach-actions/Kconfig" 610 611source "arch/arm/mach-alpine/Kconfig" 612 613source "arch/arm/mach-artpec/Kconfig" 614 615source "arch/arm/mach-asm9260/Kconfig" 616 617source "arch/arm/mach-aspeed/Kconfig" 618 619source "arch/arm/mach-at91/Kconfig" 620 621source "arch/arm/mach-axxia/Kconfig" 622 623source "arch/arm/mach-bcm/Kconfig" 624 625source "arch/arm/mach-berlin/Kconfig" 626 627source "arch/arm/mach-clps711x/Kconfig" 628 629source "arch/arm/mach-cns3xxx/Kconfig" 630 631source "arch/arm/mach-davinci/Kconfig" 632 633source "arch/arm/mach-digicolor/Kconfig" 634 635source "arch/arm/mach-dove/Kconfig" 636 637source "arch/arm/mach-ep93xx/Kconfig" 638 639source "arch/arm/mach-exynos/Kconfig" 640source "arch/arm/plat-samsung/Kconfig" 641 642source "arch/arm/mach-footbridge/Kconfig" 643 644source "arch/arm/mach-gemini/Kconfig" 645 646source "arch/arm/mach-highbank/Kconfig" 647 648source "arch/arm/mach-hisi/Kconfig" 649 650source "arch/arm/mach-imx/Kconfig" 651 652source "arch/arm/mach-integrator/Kconfig" 653 654source "arch/arm/mach-iop32x/Kconfig" 655 656source "arch/arm/mach-ixp4xx/Kconfig" 657 658source "arch/arm/mach-keystone/Kconfig" 659 660source "arch/arm/mach-lpc32xx/Kconfig" 661 662source "arch/arm/mach-mediatek/Kconfig" 663 664source "arch/arm/mach-meson/Kconfig" 665 666source "arch/arm/mach-milbeaut/Kconfig" 667 668source "arch/arm/mach-mmp/Kconfig" 669 670source "arch/arm/mach-moxart/Kconfig" 671 672source "arch/arm/mach-mv78xx0/Kconfig" 673 674source "arch/arm/mach-mvebu/Kconfig" 675 676source "arch/arm/mach-mxs/Kconfig" 677 678source "arch/arm/mach-nomadik/Kconfig" 679 680source "arch/arm/mach-npcm/Kconfig" 681 682source "arch/arm/mach-nspire/Kconfig" 683 684source "arch/arm/plat-omap/Kconfig" 685 686source "arch/arm/mach-omap1/Kconfig" 687 688source "arch/arm/mach-omap2/Kconfig" 689 690source "arch/arm/mach-orion5x/Kconfig" 691 692source "arch/arm/mach-oxnas/Kconfig" 693 694source "arch/arm/mach-picoxcell/Kconfig" 695 696source "arch/arm/mach-prima2/Kconfig" 697 698source "arch/arm/mach-pxa/Kconfig" 699source "arch/arm/plat-pxa/Kconfig" 700 701source "arch/arm/mach-qcom/Kconfig" 702 703source "arch/arm/mach-rda/Kconfig" 704 705source "arch/arm/mach-realview/Kconfig" 706 707source "arch/arm/mach-rockchip/Kconfig" 708 709source "arch/arm/mach-s3c24xx/Kconfig" 710 711source "arch/arm/mach-s3c64xx/Kconfig" 712 713source "arch/arm/mach-s5pv210/Kconfig" 714 715source "arch/arm/mach-sa1100/Kconfig" 716 717source "arch/arm/mach-shmobile/Kconfig" 718 719source "arch/arm/mach-socfpga/Kconfig" 720 721source "arch/arm/mach-spear/Kconfig" 722 723source "arch/arm/mach-sti/Kconfig" 724 725source "arch/arm/mach-stm32/Kconfig" 726 727source "arch/arm/mach-sunxi/Kconfig" 728 729source "arch/arm/mach-tango/Kconfig" 730 731source "arch/arm/mach-tegra/Kconfig" 732 733source "arch/arm/mach-u300/Kconfig" 734 735source "arch/arm/mach-uniphier/Kconfig" 736 737source "arch/arm/mach-ux500/Kconfig" 738 739source "arch/arm/mach-versatile/Kconfig" 740 741source "arch/arm/mach-vexpress/Kconfig" 742source "arch/arm/plat-versatile/Kconfig" 743 744source "arch/arm/mach-vt8500/Kconfig" 745 746source "arch/arm/mach-zx/Kconfig" 747 748source "arch/arm/mach-zynq/Kconfig" 749 750# ARMv7-M architecture 751config ARCH_EFM32 752 bool "Energy Micro efm32" 753 depends on ARM_SINGLE_ARMV7M 754 select GPIOLIB 755 help 756 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 757 processors. 758 759config ARCH_LPC18XX 760 bool "NXP LPC18xx/LPC43xx" 761 depends on ARM_SINGLE_ARMV7M 762 select ARCH_HAS_RESET_CONTROLLER 763 select ARM_AMBA 764 select CLKSRC_LPC32XX 765 select PINCTRL 766 help 767 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 768 high performance microcontrollers. 769 770config ARCH_MPS2 771 bool "ARM MPS2 platform" 772 depends on ARM_SINGLE_ARMV7M 773 select ARM_AMBA 774 select CLKSRC_MPS2 775 help 776 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 777 with a range of available cores like Cortex-M3/M4/M7. 778 779 Please, note that depends which Application Note is used memory map 780 for the platform may vary, so adjustment of RAM base might be needed. 781 782# Definitions to make life easier 783config ARCH_ACORN 784 bool 785 786config PLAT_IOP 787 bool 788 select GENERIC_CLOCKEVENTS 789 790config PLAT_ORION 791 bool 792 select CLKSRC_MMIO 793 select COMMON_CLK 794 select GENERIC_IRQ_CHIP 795 select IRQ_DOMAIN 796 797config PLAT_ORION_LEGACY 798 bool 799 select PLAT_ORION 800 801config PLAT_PXA 802 bool 803 804config PLAT_VERSATILE 805 bool 806 807source "arch/arm/mm/Kconfig" 808 809config IWMMXT 810 bool "Enable iWMMXt support" 811 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 812 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 813 help 814 Enable support for iWMMXt context switching at run time if 815 running on a CPU that supports it. 816 817if !MMU 818source "arch/arm/Kconfig-nommu" 819endif 820 821config PJ4B_ERRATA_4742 822 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 823 depends on CPU_PJ4B && MACH_ARMADA_370 824 default y 825 help 826 When coming out of either a Wait for Interrupt (WFI) or a Wait for 827 Event (WFE) IDLE states, a specific timing sensitivity exists between 828 the retiring WFI/WFE instructions and the newly issued subsequent 829 instructions. This sensitivity can result in a CPU hang scenario. 830 Workaround: 831 The software must insert either a Data Synchronization Barrier (DSB) 832 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 833 instruction 834 835config ARM_ERRATA_326103 836 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 837 depends on CPU_V6 838 help 839 Executing a SWP instruction to read-only memory does not set bit 11 840 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 841 treat the access as a read, preventing a COW from occurring and 842 causing the faulting task to livelock. 843 844config ARM_ERRATA_411920 845 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 846 depends on CPU_V6 || CPU_V6K 847 help 848 Invalidation of the Instruction Cache operation can 849 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 850 It does not affect the MPCore. This option enables the ARM Ltd. 851 recommended workaround. 852 853config ARM_ERRATA_430973 854 bool "ARM errata: Stale prediction on replaced interworking branch" 855 depends on CPU_V7 856 help 857 This option enables the workaround for the 430973 Cortex-A8 858 r1p* erratum. If a code sequence containing an ARM/Thumb 859 interworking branch is replaced with another code sequence at the 860 same virtual address, whether due to self-modifying code or virtual 861 to physical address re-mapping, Cortex-A8 does not recover from the 862 stale interworking branch prediction. This results in Cortex-A8 863 executing the new code sequence in the incorrect ARM or Thumb state. 864 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 865 and also flushes the branch target cache at every context switch. 866 Note that setting specific bits in the ACTLR register may not be 867 available in non-secure mode. 868 869config ARM_ERRATA_458693 870 bool "ARM errata: Processor deadlock when a false hazard is created" 871 depends on CPU_V7 872 depends on !ARCH_MULTIPLATFORM 873 help 874 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 875 erratum. For very specific sequences of memory operations, it is 876 possible for a hazard condition intended for a cache line to instead 877 be incorrectly associated with a different cache line. This false 878 hazard might then cause a processor deadlock. The workaround enables 879 the L1 caching of the NEON accesses and disables the PLD instruction 880 in the ACTLR register. Note that setting specific bits in the ACTLR 881 register may not be available in non-secure mode. 882 883config ARM_ERRATA_460075 884 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 885 depends on CPU_V7 886 depends on !ARCH_MULTIPLATFORM 887 help 888 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 889 erratum. Any asynchronous access to the L2 cache may encounter a 890 situation in which recent store transactions to the L2 cache are lost 891 and overwritten with stale memory contents from external memory. The 892 workaround disables the write-allocate mode for the L2 cache via the 893 ACTLR register. Note that setting specific bits in the ACTLR register 894 may not be available in non-secure mode. 895 896config ARM_ERRATA_742230 897 bool "ARM errata: DMB operation may be faulty" 898 depends on CPU_V7 && SMP 899 depends on !ARCH_MULTIPLATFORM 900 help 901 This option enables the workaround for the 742230 Cortex-A9 902 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 903 between two write operations may not ensure the correct visibility 904 ordering of the two writes. This workaround sets a specific bit in 905 the diagnostic register of the Cortex-A9 which causes the DMB 906 instruction to behave as a DSB, ensuring the correct behaviour of 907 the two writes. 908 909config ARM_ERRATA_742231 910 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 911 depends on CPU_V7 && SMP 912 depends on !ARCH_MULTIPLATFORM 913 help 914 This option enables the workaround for the 742231 Cortex-A9 915 (r2p0..r2p2) erratum. Under certain conditions, specific to the 916 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 917 accessing some data located in the same cache line, may get corrupted 918 data due to bad handling of the address hazard when the line gets 919 replaced from one of the CPUs at the same time as another CPU is 920 accessing it. This workaround sets specific bits in the diagnostic 921 register of the Cortex-A9 which reduces the linefill issuing 922 capabilities of the processor. 923 924config ARM_ERRATA_643719 925 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 926 depends on CPU_V7 && SMP 927 default y 928 help 929 This option enables the workaround for the 643719 Cortex-A9 (prior to 930 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 931 register returns zero when it should return one. The workaround 932 corrects this value, ensuring cache maintenance operations which use 933 it behave as intended and avoiding data corruption. 934 935config ARM_ERRATA_720789 936 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 937 depends on CPU_V7 938 help 939 This option enables the workaround for the 720789 Cortex-A9 (prior to 940 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 941 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 942 As a consequence of this erratum, some TLB entries which should be 943 invalidated are not, resulting in an incoherency in the system page 944 tables. The workaround changes the TLB flushing routines to invalidate 945 entries regardless of the ASID. 946 947config ARM_ERRATA_743622 948 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 949 depends on CPU_V7 950 depends on !ARCH_MULTIPLATFORM 951 help 952 This option enables the workaround for the 743622 Cortex-A9 953 (r2p*) erratum. Under very rare conditions, a faulty 954 optimisation in the Cortex-A9 Store Buffer may lead to data 955 corruption. This workaround sets a specific bit in the diagnostic 956 register of the Cortex-A9 which disables the Store Buffer 957 optimisation, preventing the defect from occurring. This has no 958 visible impact on the overall performance or power consumption of the 959 processor. 960 961config ARM_ERRATA_751472 962 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 963 depends on CPU_V7 964 depends on !ARCH_MULTIPLATFORM 965 help 966 This option enables the workaround for the 751472 Cortex-A9 (prior 967 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 968 completion of a following broadcasted operation if the second 969 operation is received by a CPU before the ICIALLUIS has completed, 970 potentially leading to corrupted entries in the cache or TLB. 971 972config ARM_ERRATA_754322 973 bool "ARM errata: possible faulty MMU translations following an ASID switch" 974 depends on CPU_V7 975 help 976 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 977 r3p*) erratum. A speculative memory access may cause a page table walk 978 which starts prior to an ASID switch but completes afterwards. This 979 can populate the micro-TLB with a stale entry which may be hit with 980 the new ASID. This workaround places two dsb instructions in the mm 981 switching code so that no page table walks can cross the ASID switch. 982 983config ARM_ERRATA_754327 984 bool "ARM errata: no automatic Store Buffer drain" 985 depends on CPU_V7 && SMP 986 help 987 This option enables the workaround for the 754327 Cortex-A9 (prior to 988 r2p0) erratum. The Store Buffer does not have any automatic draining 989 mechanism and therefore a livelock may occur if an external agent 990 continuously polls a memory location waiting to observe an update. 991 This workaround defines cpu_relax() as smp_mb(), preventing correctly 992 written polling loops from denying visibility of updates to memory. 993 994config ARM_ERRATA_364296 995 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 996 depends on CPU_V6 997 help 998 This options enables the workaround for the 364296 ARM1136 999 r0p2 erratum (possible cache data corruption with 1000 hit-under-miss enabled). It sets the undocumented bit 31 in 1001 the auxiliary control register and the FI bit in the control 1002 register, thus disabling hit-under-miss without putting the 1003 processor into full low interrupt latency mode. ARM11MPCore 1004 is not affected. 1005 1006config ARM_ERRATA_764369 1007 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1008 depends on CPU_V7 && SMP 1009 help 1010 This option enables the workaround for erratum 764369 1011 affecting Cortex-A9 MPCore with two or more processors (all 1012 current revisions). Under certain timing circumstances, a data 1013 cache line maintenance operation by MVA targeting an Inner 1014 Shareable memory region may fail to proceed up to either the 1015 Point of Coherency or to the Point of Unification of the 1016 system. This workaround adds a DSB instruction before the 1017 relevant cache maintenance functions and sets a specific bit 1018 in the diagnostic control register of the SCU. 1019 1020config ARM_ERRATA_775420 1021 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1022 depends on CPU_V7 1023 help 1024 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1025 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1026 operation aborts with MMU exception, it might cause the processor 1027 to deadlock. This workaround puts DSB before executing ISB if 1028 an abort may occur on cache maintenance. 1029 1030config ARM_ERRATA_798181 1031 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1032 depends on CPU_V7 && SMP 1033 help 1034 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1035 adequately shooting down all use of the old entries. This 1036 option enables the Linux kernel workaround for this erratum 1037 which sends an IPI to the CPUs that are running the same ASID 1038 as the one being invalidated. 1039 1040config ARM_ERRATA_773022 1041 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1042 depends on CPU_V7 1043 help 1044 This option enables the workaround for the 773022 Cortex-A15 1045 (up to r0p4) erratum. In certain rare sequences of code, the 1046 loop buffer may deliver incorrect instructions. This 1047 workaround disables the loop buffer to avoid the erratum. 1048 1049config ARM_ERRATA_818325_852422 1050 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1051 depends on CPU_V7 1052 help 1053 This option enables the workaround for: 1054 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1055 instruction might deadlock. Fixed in r0p1. 1056 - Cortex-A12 852422: Execution of a sequence of instructions might 1057 lead to either a data corruption or a CPU deadlock. Not fixed in 1058 any Cortex-A12 cores yet. 1059 This workaround for all both errata involves setting bit[12] of the 1060 Feature Register. This bit disables an optimisation applied to a 1061 sequence of 2 instructions that use opposing condition codes. 1062 1063config ARM_ERRATA_821420 1064 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1065 depends on CPU_V7 1066 help 1067 This option enables the workaround for the 821420 Cortex-A12 1068 (all revs) erratum. In very rare timing conditions, a sequence 1069 of VMOV to Core registers instructions, for which the second 1070 one is in the shadow of a branch or abort, can lead to a 1071 deadlock when the VMOV instructions are issued out-of-order. 1072 1073config ARM_ERRATA_825619 1074 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1075 depends on CPU_V7 1076 help 1077 This option enables the workaround for the 825619 Cortex-A12 1078 (all revs) erratum. Within rare timing constraints, executing a 1079 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1080 and Device/Strongly-Ordered loads and stores might cause deadlock 1081 1082config ARM_ERRATA_857271 1083 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1084 depends on CPU_V7 1085 help 1086 This option enables the workaround for the 857271 Cortex-A12 1087 (all revs) erratum. Under very rare timing conditions, the CPU might 1088 hang. The workaround is expected to have a < 1% performance impact. 1089 1090config ARM_ERRATA_852421 1091 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1092 depends on CPU_V7 1093 help 1094 This option enables the workaround for the 852421 Cortex-A17 1095 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1096 execution of a DMB ST instruction might fail to properly order 1097 stores from GroupA and stores from GroupB. 1098 1099config ARM_ERRATA_852423 1100 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1101 depends on CPU_V7 1102 help 1103 This option enables the workaround for: 1104 - Cortex-A17 852423: Execution of a sequence of instructions might 1105 lead to either a data corruption or a CPU deadlock. Not fixed in 1106 any Cortex-A17 cores yet. 1107 This is identical to Cortex-A12 erratum 852422. It is a separate 1108 config option from the A12 erratum due to the way errata are checked 1109 for and handled. 1110 1111config ARM_ERRATA_857272 1112 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1113 depends on CPU_V7 1114 help 1115 This option enables the workaround for the 857272 Cortex-A17 erratum. 1116 This erratum is not known to be fixed in any A17 revision. 1117 This is identical to Cortex-A12 erratum 857271. It is a separate 1118 config option from the A12 erratum due to the way errata are checked 1119 for and handled. 1120 1121endmenu 1122 1123source "arch/arm/common/Kconfig" 1124 1125menu "Bus support" 1126 1127config ISA 1128 bool 1129 help 1130 Find out whether you have ISA slots on your motherboard. ISA is the 1131 name of a bus system, i.e. the way the CPU talks to the other stuff 1132 inside your box. Other bus systems are PCI, EISA, MicroChannel 1133 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1134 newer boards don't support it. If you have ISA, say Y, otherwise N. 1135 1136# Select ISA DMA controller support 1137config ISA_DMA 1138 bool 1139 select ISA_DMA_API 1140 1141# Select ISA DMA interface 1142config ISA_DMA_API 1143 bool 1144 1145config PCI_NANOENGINE 1146 bool "BSE nanoEngine PCI support" 1147 depends on SA1100_NANOENGINE 1148 help 1149 Enable PCI on the BSE nanoEngine board. 1150 1151config PCI_HOST_ITE8152 1152 bool 1153 depends on PCI && MACH_ARMCORE 1154 default y 1155 select DMABOUNCE 1156 1157config ARM_ERRATA_814220 1158 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1159 depends on CPU_V7 1160 help 1161 The v7 ARM states that all cache and branch predictor maintenance 1162 operations that do not specify an address execute, relative to 1163 each other, in program order. 1164 However, because of this erratum, an L2 set/way cache maintenance 1165 operation can overtake an L1 set/way cache maintenance operation. 1166 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1167 r0p4, r0p5. 1168 1169endmenu 1170 1171menu "Kernel Features" 1172 1173config HAVE_SMP 1174 bool 1175 help 1176 This option should be selected by machines which have an SMP- 1177 capable CPU. 1178 1179 The only effect of this option is to make the SMP-related 1180 options available to the user for configuration. 1181 1182config SMP 1183 bool "Symmetric Multi-Processing" 1184 depends on CPU_V6K || CPU_V7 1185 depends on GENERIC_CLOCKEVENTS 1186 depends on HAVE_SMP 1187 depends on MMU || ARM_MPU 1188 select IRQ_WORK 1189 help 1190 This enables support for systems with more than one CPU. If you have 1191 a system with only one CPU, say N. If you have a system with more 1192 than one CPU, say Y. 1193 1194 If you say N here, the kernel will run on uni- and multiprocessor 1195 machines, but will use only one CPU of a multiprocessor machine. If 1196 you say Y here, the kernel will run on many, but not all, 1197 uniprocessor machines. On a uniprocessor machine, the kernel 1198 will run faster if you say N here. 1199 1200 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1201 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1202 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1203 1204 If you don't know what to do here, say N. 1205 1206config SMP_ON_UP 1207 bool "Allow booting SMP kernel on uniprocessor systems" 1208 depends on SMP && !XIP_KERNEL && MMU 1209 default y 1210 help 1211 SMP kernels contain instructions which fail on non-SMP processors. 1212 Enabling this option allows the kernel to modify itself to make 1213 these instructions safe. Disabling it allows about 1K of space 1214 savings. 1215 1216 If you don't know what to do here, say Y. 1217 1218config ARM_CPU_TOPOLOGY 1219 bool "Support cpu topology definition" 1220 depends on SMP && CPU_V7 1221 default y 1222 help 1223 Support ARM cpu topology definition. The MPIDR register defines 1224 affinity between processors which is then used to describe the cpu 1225 topology of an ARM System. 1226 1227config SCHED_MC 1228 bool "Multi-core scheduler support" 1229 depends on ARM_CPU_TOPOLOGY 1230 help 1231 Multi-core scheduler support improves the CPU scheduler's decision 1232 making when dealing with multi-core CPU chips at a cost of slightly 1233 increased overhead in some places. If unsure say N here. 1234 1235config SCHED_SMT 1236 bool "SMT scheduler support" 1237 depends on ARM_CPU_TOPOLOGY 1238 help 1239 Improves the CPU scheduler's decision making when dealing with 1240 MultiThreading at a cost of slightly increased overhead in some 1241 places. If unsure say N here. 1242 1243config HAVE_ARM_SCU 1244 bool 1245 help 1246 This option enables support for the ARM snoop control unit 1247 1248config HAVE_ARM_ARCH_TIMER 1249 bool "Architected timer support" 1250 depends on CPU_V7 1251 select ARM_ARCH_TIMER 1252 select GENERIC_CLOCKEVENTS 1253 help 1254 This option enables support for the ARM architected timer 1255 1256config HAVE_ARM_TWD 1257 bool 1258 help 1259 This options enables support for the ARM timer and watchdog unit 1260 1261config MCPM 1262 bool "Multi-Cluster Power Management" 1263 depends on CPU_V7 && SMP 1264 help 1265 This option provides the common power management infrastructure 1266 for (multi-)cluster based systems, such as big.LITTLE based 1267 systems. 1268 1269config MCPM_QUAD_CLUSTER 1270 bool 1271 depends on MCPM 1272 help 1273 To avoid wasting resources unnecessarily, MCPM only supports up 1274 to 2 clusters by default. 1275 Platforms with 3 or 4 clusters that use MCPM must select this 1276 option to allow the additional clusters to be managed. 1277 1278config BIG_LITTLE 1279 bool "big.LITTLE support (Experimental)" 1280 depends on CPU_V7 && SMP 1281 select MCPM 1282 help 1283 This option enables support selections for the big.LITTLE 1284 system architecture. 1285 1286config BL_SWITCHER 1287 bool "big.LITTLE switcher support" 1288 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1289 select CPU_PM 1290 help 1291 The big.LITTLE "switcher" provides the core functionality to 1292 transparently handle transition between a cluster of A15's 1293 and a cluster of A7's in a big.LITTLE system. 1294 1295config BL_SWITCHER_DUMMY_IF 1296 tristate "Simple big.LITTLE switcher user interface" 1297 depends on BL_SWITCHER && DEBUG_KERNEL 1298 help 1299 This is a simple and dummy char dev interface to control 1300 the big.LITTLE switcher core code. It is meant for 1301 debugging purposes only. 1302 1303choice 1304 prompt "Memory split" 1305 depends on MMU 1306 default VMSPLIT_3G 1307 help 1308 Select the desired split between kernel and user memory. 1309 1310 If you are not absolutely sure what you are doing, leave this 1311 option alone! 1312 1313 config VMSPLIT_3G 1314 bool "3G/1G user/kernel split" 1315 config VMSPLIT_3G_OPT 1316 depends on !ARM_LPAE 1317 bool "3G/1G user/kernel split (for full 1G low memory)" 1318 config VMSPLIT_2G 1319 bool "2G/2G user/kernel split" 1320 config VMSPLIT_1G 1321 bool "1G/3G user/kernel split" 1322endchoice 1323 1324config PAGE_OFFSET 1325 hex 1326 default PHYS_OFFSET if !MMU 1327 default 0x40000000 if VMSPLIT_1G 1328 default 0x80000000 if VMSPLIT_2G 1329 default 0xB0000000 if VMSPLIT_3G_OPT 1330 default 0xC0000000 1331 1332config NR_CPUS 1333 int "Maximum number of CPUs (2-32)" 1334 range 2 32 1335 depends on SMP 1336 default "4" 1337 1338config HOTPLUG_CPU 1339 bool "Support for hot-pluggable CPUs" 1340 depends on SMP 1341 select GENERIC_IRQ_MIGRATION 1342 help 1343 Say Y here to experiment with turning CPUs off and on. CPUs 1344 can be controlled through /sys/devices/system/cpu. 1345 1346config ARM_PSCI 1347 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1348 depends on HAVE_ARM_SMCCC 1349 select ARM_PSCI_FW 1350 help 1351 Say Y here if you want Linux to communicate with system firmware 1352 implementing the PSCI specification for CPU-centric power 1353 management operations described in ARM document number ARM DEN 1354 0022A ("Power State Coordination Interface System Software on 1355 ARM processors"). 1356 1357# The GPIO number here must be sorted by descending number. In case of 1358# a multiplatform kernel, we just want the highest value required by the 1359# selected platforms. 1360config ARCH_NR_GPIO 1361 int 1362 default 2048 if ARCH_SOCFPGA 1363 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1364 ARCH_ZYNQ || ARCH_ASPEED 1365 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1366 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1367 default 416 if ARCH_SUNXI 1368 default 392 if ARCH_U8500 1369 default 352 if ARCH_VT8500 1370 default 288 if ARCH_ROCKCHIP 1371 default 264 if MACH_H4700 1372 default 0 1373 help 1374 Maximum number of GPIOs in the system. 1375 1376 If unsure, leave the default value. 1377 1378config HZ_FIXED 1379 int 1380 default 200 if ARCH_EBSA110 1381 default 128 if SOC_AT91RM9200 1382 default 0 1383 1384choice 1385 depends on HZ_FIXED = 0 1386 prompt "Timer frequency" 1387 1388config HZ_100 1389 bool "100 Hz" 1390 1391config HZ_200 1392 bool "200 Hz" 1393 1394config HZ_250 1395 bool "250 Hz" 1396 1397config HZ_300 1398 bool "300 Hz" 1399 1400config HZ_500 1401 bool "500 Hz" 1402 1403config HZ_1000 1404 bool "1000 Hz" 1405 1406endchoice 1407 1408config HZ 1409 int 1410 default HZ_FIXED if HZ_FIXED != 0 1411 default 100 if HZ_100 1412 default 200 if HZ_200 1413 default 250 if HZ_250 1414 default 300 if HZ_300 1415 default 500 if HZ_500 1416 default 1000 1417 1418config SCHED_HRTICK 1419 def_bool HIGH_RES_TIMERS 1420 1421config THUMB2_KERNEL 1422 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1423 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1424 default y if CPU_THUMBONLY 1425 select ARM_UNWIND 1426 help 1427 By enabling this option, the kernel will be compiled in 1428 Thumb-2 mode. 1429 1430 If unsure, say N. 1431 1432config THUMB2_AVOID_R_ARM_THM_JUMP11 1433 bool "Work around buggy Thumb-2 short branch relocations in gas" 1434 depends on THUMB2_KERNEL && MODULES 1435 default y 1436 help 1437 Various binutils versions can resolve Thumb-2 branches to 1438 locally-defined, preemptible global symbols as short-range "b.n" 1439 branch instructions. 1440 1441 This is a problem, because there's no guarantee the final 1442 destination of the symbol, or any candidate locations for a 1443 trampoline, are within range of the branch. For this reason, the 1444 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1445 relocation in modules at all, and it makes little sense to add 1446 support. 1447 1448 The symptom is that the kernel fails with an "unsupported 1449 relocation" error when loading some modules. 1450 1451 Until fixed tools are available, passing 1452 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1453 code which hits this problem, at the cost of a bit of extra runtime 1454 stack usage in some cases. 1455 1456 The problem is described in more detail at: 1457 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1458 1459 Only Thumb-2 kernels are affected. 1460 1461 Unless you are sure your tools don't have this problem, say Y. 1462 1463config ARM_PATCH_IDIV 1464 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1465 depends on CPU_32v7 && !XIP_KERNEL 1466 default y 1467 help 1468 The ARM compiler inserts calls to __aeabi_idiv() and 1469 __aeabi_uidiv() when it needs to perform division on signed 1470 and unsigned integers. Some v7 CPUs have support for the sdiv 1471 and udiv instructions that can be used to implement those 1472 functions. 1473 1474 Enabling this option allows the kernel to modify itself to 1475 replace the first two instructions of these library functions 1476 with the sdiv or udiv plus "bx lr" instructions when the CPU 1477 it is running on supports them. Typically this will be faster 1478 and less power intensive than running the original library 1479 code to do integer division. 1480 1481config AEABI 1482 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1483 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1484 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1485 help 1486 This option allows for the kernel to be compiled using the latest 1487 ARM ABI (aka EABI). This is only useful if you are using a user 1488 space environment that is also compiled with EABI. 1489 1490 Since there are major incompatibilities between the legacy ABI and 1491 EABI, especially with regard to structure member alignment, this 1492 option also changes the kernel syscall calling convention to 1493 disambiguate both ABIs and allow for backward compatibility support 1494 (selected with CONFIG_OABI_COMPAT). 1495 1496 To use this you need GCC version 4.0.0 or later. 1497 1498config OABI_COMPAT 1499 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1500 depends on AEABI && !THUMB2_KERNEL 1501 help 1502 This option preserves the old syscall interface along with the 1503 new (ARM EABI) one. It also provides a compatibility layer to 1504 intercept syscalls that have structure arguments which layout 1505 in memory differs between the legacy ABI and the new ARM EABI 1506 (only for non "thumb" binaries). This option adds a tiny 1507 overhead to all syscalls and produces a slightly larger kernel. 1508 1509 The seccomp filter system will not be available when this is 1510 selected, since there is no way yet to sensibly distinguish 1511 between calling conventions during filtering. 1512 1513 If you know you'll be using only pure EABI user space then you 1514 can say N here. If this option is not selected and you attempt 1515 to execute a legacy ABI binary then the result will be 1516 UNPREDICTABLE (in fact it can be predicted that it won't work 1517 at all). If in doubt say N. 1518 1519config ARCH_HAS_HOLES_MEMORYMODEL 1520 bool 1521 1522config ARCH_SELECT_MEMORY_MODEL 1523 bool 1524 1525config ARCH_FLATMEM_ENABLE 1526 bool 1527 1528config ARCH_SPARSEMEM_ENABLE 1529 bool 1530 select SPARSEMEM_STATIC if SPARSEMEM 1531 1532config HAVE_ARCH_PFN_VALID 1533 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1534 1535config HIGHMEM 1536 bool "High Memory Support" 1537 depends on MMU 1538 help 1539 The address space of ARM processors is only 4 Gigabytes large 1540 and it has to accommodate user address space, kernel address 1541 space as well as some memory mapped IO. That means that, if you 1542 have a large amount of physical memory and/or IO, not all of the 1543 memory can be "permanently mapped" by the kernel. The physical 1544 memory that is not permanently mapped is called "high memory". 1545 1546 Depending on the selected kernel/user memory split, minimum 1547 vmalloc space and actual amount of RAM, you may not need this 1548 option which should result in a slightly faster kernel. 1549 1550 If unsure, say n. 1551 1552config HIGHPTE 1553 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1554 depends on HIGHMEM 1555 default y 1556 help 1557 The VM uses one page of physical memory for each page table. 1558 For systems with a lot of processes, this can use a lot of 1559 precious low memory, eventually leading to low memory being 1560 consumed by page tables. Setting this option will allow 1561 user-space 2nd level page tables to reside in high memory. 1562 1563config CPU_SW_DOMAIN_PAN 1564 bool "Enable use of CPU domains to implement privileged no-access" 1565 depends on MMU && !ARM_LPAE 1566 default y 1567 help 1568 Increase kernel security by ensuring that normal kernel accesses 1569 are unable to access userspace addresses. This can help prevent 1570 use-after-free bugs becoming an exploitable privilege escalation 1571 by ensuring that magic values (such as LIST_POISON) will always 1572 fault when dereferenced. 1573 1574 CPUs with low-vector mappings use a best-efforts implementation. 1575 Their lower 1MB needs to remain accessible for the vectors, but 1576 the remainder of userspace will become appropriately inaccessible. 1577 1578config HW_PERF_EVENTS 1579 def_bool y 1580 depends on ARM_PMU 1581 1582config SYS_SUPPORTS_HUGETLBFS 1583 def_bool y 1584 depends on ARM_LPAE 1585 1586config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1587 def_bool y 1588 depends on ARM_LPAE 1589 1590config ARCH_WANT_GENERAL_HUGETLB 1591 def_bool y 1592 1593config ARM_MODULE_PLTS 1594 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1595 depends on MODULES 1596 default y 1597 help 1598 Allocate PLTs when loading modules so that jumps and calls whose 1599 targets are too far away for their relative offsets to be encoded 1600 in the instructions themselves can be bounced via veneers in the 1601 module's PLT. This allows modules to be allocated in the generic 1602 vmalloc area after the dedicated module memory area has been 1603 exhausted. The modules will use slightly more memory, but after 1604 rounding up to page size, the actual memory footprint is usually 1605 the same. 1606 1607 Disabling this is usually safe for small single-platform 1608 configurations. If unsure, say y. 1609 1610config FORCE_MAX_ZONEORDER 1611 int "Maximum zone order" 1612 default "12" if SOC_AM33XX 1613 default "9" if SA1111 || ARCH_EFM32 1614 default "11" 1615 help 1616 The kernel memory allocator divides physically contiguous memory 1617 blocks into "zones", where each zone is a power of two number of 1618 pages. This option selects the largest power of two that the kernel 1619 keeps in the memory allocator. If you need to allocate very large 1620 blocks of physically contiguous memory, then you may need to 1621 increase this value. 1622 1623 This config option is actually maximum order plus one. For example, 1624 a value of 11 means that the largest free memory block is 2^10 pages. 1625 1626config ALIGNMENT_TRAP 1627 bool 1628 depends on CPU_CP15_MMU 1629 default y if !ARCH_EBSA110 1630 select HAVE_PROC_CPU if PROC_FS 1631 help 1632 ARM processors cannot fetch/store information which is not 1633 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1634 address divisible by 4. On 32-bit ARM processors, these non-aligned 1635 fetch/store instructions will be emulated in software if you say 1636 here, which has a severe performance impact. This is necessary for 1637 correct operation of some network protocols. With an IP-only 1638 configuration it is safe to say N, otherwise say Y. 1639 1640config UACCESS_WITH_MEMCPY 1641 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1642 depends on MMU 1643 default y if CPU_FEROCEON 1644 help 1645 Implement faster copy_to_user and clear_user methods for CPU 1646 cores where a 8-word STM instruction give significantly higher 1647 memory write throughput than a sequence of individual 32bit stores. 1648 1649 A possible side effect is a slight increase in scheduling latency 1650 between threads sharing the same address space if they invoke 1651 such copy operations with large buffers. 1652 1653 However, if the CPU data cache is using a write-allocate mode, 1654 this option is unlikely to provide any performance gain. 1655 1656config SECCOMP 1657 bool 1658 prompt "Enable seccomp to safely compute untrusted bytecode" 1659 ---help--- 1660 This kernel feature is useful for number crunching applications 1661 that may need to compute untrusted bytecode during their 1662 execution. By using pipes or other transports made available to 1663 the process as file descriptors supporting the read/write 1664 syscalls, it's possible to isolate those applications in 1665 their own address space using seccomp. Once seccomp is 1666 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1667 and the task is only allowed to execute a few safe syscalls 1668 defined by each seccomp mode. 1669 1670config PARAVIRT 1671 bool "Enable paravirtualization code" 1672 help 1673 This changes the kernel so it can modify itself when it is run 1674 under a hypervisor, potentially improving performance significantly 1675 over full virtualization. 1676 1677config PARAVIRT_TIME_ACCOUNTING 1678 bool "Paravirtual steal time accounting" 1679 select PARAVIRT 1680 help 1681 Select this option to enable fine granularity task steal time 1682 accounting. Time spent executing other tasks in parallel with 1683 the current vCPU is discounted from the vCPU power. To account for 1684 that, there can be a small performance impact. 1685 1686 If in doubt, say N here. 1687 1688config XEN_DOM0 1689 def_bool y 1690 depends on XEN 1691 1692config XEN 1693 bool "Xen guest support on ARM" 1694 depends on ARM && AEABI && OF 1695 depends on CPU_V7 && !CPU_V6 1696 depends on !GENERIC_ATOMIC64 1697 depends on MMU 1698 select ARCH_DMA_ADDR_T_64BIT 1699 select ARM_PSCI 1700 select SWIOTLB 1701 select SWIOTLB_XEN 1702 select PARAVIRT 1703 help 1704 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1705 1706config STACKPROTECTOR_PER_TASK 1707 bool "Use a unique stack canary value for each task" 1708 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1709 select GCC_PLUGIN_ARM_SSP_PER_TASK 1710 default y 1711 help 1712 Due to the fact that GCC uses an ordinary symbol reference from 1713 which to load the value of the stack canary, this value can only 1714 change at reboot time on SMP systems, and all tasks running in the 1715 kernel's address space are forced to use the same canary value for 1716 the entire duration that the system is up. 1717 1718 Enable this option to switch to a different method that uses a 1719 different canary value for each task. 1720 1721endmenu 1722 1723menu "Boot options" 1724 1725config USE_OF 1726 bool "Flattened Device Tree support" 1727 select IRQ_DOMAIN 1728 select OF 1729 help 1730 Include support for flattened device tree machine descriptions. 1731 1732config ATAGS 1733 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1734 default y 1735 help 1736 This is the traditional way of passing data to the kernel at boot 1737 time. If you are solely relying on the flattened device tree (or 1738 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1739 to remove ATAGS support from your kernel binary. If unsure, 1740 leave this to y. 1741 1742config DEPRECATED_PARAM_STRUCT 1743 bool "Provide old way to pass kernel parameters" 1744 depends on ATAGS 1745 help 1746 This was deprecated in 2001 and announced to live on for 5 years. 1747 Some old boot loaders still use this way. 1748 1749# Compressed boot loader in ROM. Yes, we really want to ask about 1750# TEXT and BSS so we preserve their values in the config files. 1751config ZBOOT_ROM_TEXT 1752 hex "Compressed ROM boot loader base address" 1753 default "0" 1754 help 1755 The physical address at which the ROM-able zImage is to be 1756 placed in the target. Platforms which normally make use of 1757 ROM-able zImage formats normally set this to a suitable 1758 value in their defconfig file. 1759 1760 If ZBOOT_ROM is not enabled, this has no effect. 1761 1762config ZBOOT_ROM_BSS 1763 hex "Compressed ROM boot loader BSS address" 1764 default "0" 1765 help 1766 The base address of an area of read/write memory in the target 1767 for the ROM-able zImage which must be available while the 1768 decompressor is running. It must be large enough to hold the 1769 entire decompressed kernel plus an additional 128 KiB. 1770 Platforms which normally make use of ROM-able zImage formats 1771 normally set this to a suitable value in their defconfig file. 1772 1773 If ZBOOT_ROM is not enabled, this has no effect. 1774 1775config ZBOOT_ROM 1776 bool "Compressed boot loader in ROM/flash" 1777 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1778 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1779 help 1780 Say Y here if you intend to execute your compressed kernel image 1781 (zImage) directly from ROM or flash. If unsure, say N. 1782 1783config ARM_APPENDED_DTB 1784 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1785 depends on OF 1786 help 1787 With this option, the boot code will look for a device tree binary 1788 (DTB) appended to zImage 1789 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1790 1791 This is meant as a backward compatibility convenience for those 1792 systems with a bootloader that can't be upgraded to accommodate 1793 the documented boot protocol using a device tree. 1794 1795 Beware that there is very little in terms of protection against 1796 this option being confused by leftover garbage in memory that might 1797 look like a DTB header after a reboot if no actual DTB is appended 1798 to zImage. Do not leave this option active in a production kernel 1799 if you don't intend to always append a DTB. Proper passing of the 1800 location into r2 of a bootloader provided DTB is always preferable 1801 to this option. 1802 1803config ARM_ATAG_DTB_COMPAT 1804 bool "Supplement the appended DTB with traditional ATAG information" 1805 depends on ARM_APPENDED_DTB 1806 help 1807 Some old bootloaders can't be updated to a DTB capable one, yet 1808 they provide ATAGs with memory configuration, the ramdisk address, 1809 the kernel cmdline string, etc. Such information is dynamically 1810 provided by the bootloader and can't always be stored in a static 1811 DTB. To allow a device tree enabled kernel to be used with such 1812 bootloaders, this option allows zImage to extract the information 1813 from the ATAG list and store it at run time into the appended DTB. 1814 1815choice 1816 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1817 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1818 1819config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1820 bool "Use bootloader kernel arguments if available" 1821 help 1822 Uses the command-line options passed by the boot loader instead of 1823 the device tree bootargs property. If the boot loader doesn't provide 1824 any, the device tree bootargs property will be used. 1825 1826config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1827 bool "Extend with bootloader kernel arguments" 1828 help 1829 The command-line arguments provided by the boot loader will be 1830 appended to the the device tree bootargs property. 1831 1832endchoice 1833 1834config CMDLINE 1835 string "Default kernel command string" 1836 default "" 1837 help 1838 On some architectures (EBSA110 and CATS), there is currently no way 1839 for the boot loader to pass arguments to the kernel. For these 1840 architectures, you should supply some command-line options at build 1841 time by entering them here. As a minimum, you should specify the 1842 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1843 1844choice 1845 prompt "Kernel command line type" if CMDLINE != "" 1846 default CMDLINE_FROM_BOOTLOADER 1847 depends on ATAGS 1848 1849config CMDLINE_FROM_BOOTLOADER 1850 bool "Use bootloader kernel arguments if available" 1851 help 1852 Uses the command-line options passed by the boot loader. If 1853 the boot loader doesn't provide any, the default kernel command 1854 string provided in CMDLINE will be used. 1855 1856config CMDLINE_EXTEND 1857 bool "Extend bootloader kernel arguments" 1858 help 1859 The command-line arguments provided by the boot loader will be 1860 appended to the default kernel command string. 1861 1862config CMDLINE_FORCE 1863 bool "Always use the default kernel command string" 1864 help 1865 Always use the default kernel command string, even if the boot 1866 loader passes other arguments to the kernel. 1867 This is useful if you cannot or don't want to change the 1868 command-line options your boot loader passes to the kernel. 1869endchoice 1870 1871config XIP_KERNEL 1872 bool "Kernel Execute-In-Place from ROM" 1873 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1874 help 1875 Execute-In-Place allows the kernel to run from non-volatile storage 1876 directly addressable by the CPU, such as NOR flash. This saves RAM 1877 space since the text section of the kernel is not loaded from flash 1878 to RAM. Read-write sections, such as the data section and stack, 1879 are still copied to RAM. The XIP kernel is not compressed since 1880 it has to run directly from flash, so it will take more space to 1881 store it. The flash address used to link the kernel object files, 1882 and for storing it, is configuration dependent. Therefore, if you 1883 say Y here, you must know the proper physical address where to 1884 store the kernel image depending on your own flash memory usage. 1885 1886 Also note that the make target becomes "make xipImage" rather than 1887 "make zImage" or "make Image". The final kernel binary to put in 1888 ROM memory will be arch/arm/boot/xipImage. 1889 1890 If unsure, say N. 1891 1892config XIP_PHYS_ADDR 1893 hex "XIP Kernel Physical Location" 1894 depends on XIP_KERNEL 1895 default "0x00080000" 1896 help 1897 This is the physical address in your flash memory the kernel will 1898 be linked for and stored to. This address is dependent on your 1899 own flash usage. 1900 1901config XIP_DEFLATED_DATA 1902 bool "Store kernel .data section compressed in ROM" 1903 depends on XIP_KERNEL 1904 select ZLIB_INFLATE 1905 help 1906 Before the kernel is actually executed, its .data section has to be 1907 copied to RAM from ROM. This option allows for storing that data 1908 in compressed form and decompressed to RAM rather than merely being 1909 copied, saving some precious ROM space. A possible drawback is a 1910 slightly longer boot delay. 1911 1912config KEXEC 1913 bool "Kexec system call (EXPERIMENTAL)" 1914 depends on (!SMP || PM_SLEEP_SMP) 1915 depends on MMU 1916 select KEXEC_CORE 1917 help 1918 kexec is a system call that implements the ability to shutdown your 1919 current kernel, and to start another kernel. It is like a reboot 1920 but it is independent of the system firmware. And like a reboot 1921 you can start any kernel with it, not just Linux. 1922 1923 It is an ongoing process to be certain the hardware in a machine 1924 is properly shutdown, so do not be surprised if this code does not 1925 initially work for you. 1926 1927config ATAGS_PROC 1928 bool "Export atags in procfs" 1929 depends on ATAGS && KEXEC 1930 default y 1931 help 1932 Should the atags used to boot the kernel be exported in an "atags" 1933 file in procfs. Useful with kexec. 1934 1935config CRASH_DUMP 1936 bool "Build kdump crash kernel (EXPERIMENTAL)" 1937 help 1938 Generate crash dump after being started by kexec. This should 1939 be normally only set in special crash dump kernels which are 1940 loaded in the main kernel with kexec-tools into a specially 1941 reserved region and then later executed after a crash by 1942 kdump/kexec. The crash dump kernel must be compiled to a 1943 memory address not used by the main kernel 1944 1945 For more details see Documentation/admin-guide/kdump/kdump.rst 1946 1947config AUTO_ZRELADDR 1948 bool "Auto calculation of the decompressed kernel image address" 1949 help 1950 ZRELADDR is the physical address where the decompressed kernel 1951 image will be placed. If AUTO_ZRELADDR is selected, the address 1952 will be determined at run-time by masking the current IP with 1953 0xf8000000. This assumes the zImage being placed in the first 128MB 1954 from start of memory. 1955 1956config EFI_STUB 1957 bool 1958 1959config EFI 1960 bool "UEFI runtime support" 1961 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1962 select UCS2_STRING 1963 select EFI_PARAMS_FROM_FDT 1964 select EFI_STUB 1965 select EFI_GENERIC_STUB 1966 select EFI_RUNTIME_WRAPPERS 1967 ---help--- 1968 This option provides support for runtime services provided 1969 by UEFI firmware (such as non-volatile variables, realtime 1970 clock, and platform reset). A UEFI stub is also provided to 1971 allow the kernel to be booted as an EFI application. This 1972 is only useful for kernels that may run on systems that have 1973 UEFI firmware. 1974 1975config DMI 1976 bool "Enable support for SMBIOS (DMI) tables" 1977 depends on EFI 1978 default y 1979 help 1980 This enables SMBIOS/DMI feature for systems. 1981 1982 This option is only useful on systems that have UEFI firmware. 1983 However, even with this option, the resultant kernel should 1984 continue to boot on existing non-UEFI platforms. 1985 1986 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1987 i.e., the the practice of identifying the platform via DMI to 1988 decide whether certain workarounds for buggy hardware and/or 1989 firmware need to be enabled. This would require the DMI subsystem 1990 to be enabled much earlier than we do on ARM, which is non-trivial. 1991 1992endmenu 1993 1994menu "CPU Power Management" 1995 1996source "drivers/cpufreq/Kconfig" 1997 1998source "drivers/cpuidle/Kconfig" 1999 2000endmenu 2001 2002menu "Floating point emulation" 2003 2004comment "At least one emulation must be selected" 2005 2006config FPE_NWFPE 2007 bool "NWFPE math emulation" 2008 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2009 ---help--- 2010 Say Y to include the NWFPE floating point emulator in the kernel. 2011 This is necessary to run most binaries. Linux does not currently 2012 support floating point hardware so you need to say Y here even if 2013 your machine has an FPA or floating point co-processor podule. 2014 2015 You may say N here if you are going to load the Acorn FPEmulator 2016 early in the bootup. 2017 2018config FPE_NWFPE_XP 2019 bool "Support extended precision" 2020 depends on FPE_NWFPE 2021 help 2022 Say Y to include 80-bit support in the kernel floating-point 2023 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2024 Note that gcc does not generate 80-bit operations by default, 2025 so in most cases this option only enlarges the size of the 2026 floating point emulator without any good reason. 2027 2028 You almost surely want to say N here. 2029 2030config FPE_FASTFPE 2031 bool "FastFPE math emulation (EXPERIMENTAL)" 2032 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2033 ---help--- 2034 Say Y here to include the FAST floating point emulator in the kernel. 2035 This is an experimental much faster emulator which now also has full 2036 precision for the mantissa. It does not support any exceptions. 2037 It is very simple, and approximately 3-6 times faster than NWFPE. 2038 2039 It should be sufficient for most programs. It may be not suitable 2040 for scientific calculations, but you have to check this for yourself. 2041 If you do not feel you need a faster FP emulation you should better 2042 choose NWFPE. 2043 2044config VFP 2045 bool "VFP-format floating point maths" 2046 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2047 help 2048 Say Y to include VFP support code in the kernel. This is needed 2049 if your hardware includes a VFP unit. 2050 2051 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2052 release notes and additional status information. 2053 2054 Say N if your target does not have VFP hardware. 2055 2056config VFPv3 2057 bool 2058 depends on VFP 2059 default y if CPU_V7 2060 2061config NEON 2062 bool "Advanced SIMD (NEON) Extension support" 2063 depends on VFPv3 && CPU_V7 2064 help 2065 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2066 Extension. 2067 2068config KERNEL_MODE_NEON 2069 bool "Support for NEON in kernel mode" 2070 depends on NEON && AEABI 2071 help 2072 Say Y to include support for NEON in kernel mode. 2073 2074endmenu 2075 2076menu "Power management options" 2077 2078source "kernel/power/Kconfig" 2079 2080config ARCH_SUSPEND_POSSIBLE 2081 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2082 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2083 def_bool y 2084 2085config ARM_CPU_SUSPEND 2086 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2087 depends on ARCH_SUSPEND_POSSIBLE 2088 2089config ARCH_HIBERNATION_POSSIBLE 2090 bool 2091 depends on MMU 2092 default y if ARCH_SUSPEND_POSSIBLE 2093 2094endmenu 2095 2096source "drivers/firmware/Kconfig" 2097 2098if CRYPTO 2099source "arch/arm/crypto/Kconfig" 2100endif 2101