1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_USE_MEMTEST 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_IPC_PARSE_VERSION 40 select ARCH_WANT_LD_ORPHAN_WARN 41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 42 select BUILDTIME_TABLE_SORT if MMU 43 select CLONE_BACKWARDS 44 select CPU_PM if SUSPEND || CPU_IDLE 45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 46 select DMA_DECLARE_COHERENT 47 select DMA_OPS 48 select DMA_REMAP if MMU 49 select EDAC_SUPPORT 50 select EDAC_ATOMIC_SCRUB 51 select GENERIC_ALLOCATOR 52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 55 select GENERIC_IRQ_IPI if SMP 56 select GENERIC_CPU_AUTOPROBE 57 select GENERIC_EARLY_IOREMAP 58 select GENERIC_IDLE_POLL_SETUP 59 select GENERIC_IRQ_PROBE 60 select GENERIC_IRQ_SHOW 61 select GENERIC_IRQ_SHOW_LEVEL 62 select GENERIC_LIB_DEVMEM_IS_ALLOWED 63 select GENERIC_PCI_IOMAP 64 select GENERIC_SCHED_CLOCK 65 select GENERIC_SMP_IDLE_THREAD 66 select GENERIC_STRNCPY_FROM_USER 67 select GENERIC_STRNLEN_USER 68 select HANDLE_DOMAIN_IRQ 69 select HARDIRQS_SW_RESEND 70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 87 select HAVE_DMA_CONTIGUOUS if MMU 88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 91 select HAVE_EXIT_THREAD 92 select HAVE_FAST_GUP if ARM_LPAE 93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IDE if PCI || ISA || PCMCIA 99 select HAVE_IRQ_TIME_ACCOUNTING 100 select HAVE_KERNEL_GZIP 101 select HAVE_KERNEL_LZ4 102 select HAVE_KERNEL_LZMA 103 select HAVE_KERNEL_LZO 104 select HAVE_KERNEL_XZ 105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 106 select HAVE_KRETPROBES if HAVE_KPROBES 107 select HAVE_MOD_ARCH_SPECIFIC 108 select HAVE_NMI 109 select HAVE_OPTPROBES if !THUMB2_KERNEL 110 select HAVE_PERF_EVENTS 111 select HAVE_PERF_REGS 112 select HAVE_PERF_USER_STACK_DUMP 113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 114 select HAVE_REGS_AND_STACK_ACCESS_API 115 select HAVE_RSEQ 116 select HAVE_STACKPROTECTOR 117 select HAVE_SYSCALL_TRACEPOINTS 118 select HAVE_UID16 119 select HAVE_VIRT_CPU_ACCOUNTING_GEN 120 select IRQ_FORCED_THREADING 121 select MODULES_USE_ELF_REL 122 select NEED_DMA_MAP_STATE 123 select OF_EARLY_FLATTREE if OF 124 select OLD_SIGACTION 125 select OLD_SIGSUSPEND3 126 select PCI_SYSCALL if PCI 127 select PERF_USE_VMALLOC 128 select RTC_LIB 129 select SET_FS 130 select SYS_SUPPORTS_APM_EMULATION 131 # Above selects are sorted alphabetically; please add new ones 132 # according to that. Thanks. 133 help 134 The ARM series is a line of low-power-consumption RISC chip designs 135 licensed by ARM Ltd and targeted at embedded applications and 136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 137 manufactured, but legacy ARM-based PC hardware remains popular in 138 Europe. There is an ARM Linux project with a web page at 139 <http://www.arm.linux.org.uk/>. 140 141config ARM_HAS_SG_CHAIN 142 bool 143 144config ARM_DMA_USE_IOMMU 145 bool 146 select ARM_HAS_SG_CHAIN 147 select NEED_SG_DMA_LENGTH 148 149if ARM_DMA_USE_IOMMU 150 151config ARM_DMA_IOMMU_ALIGNMENT 152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 153 range 4 9 154 default 8 155 help 156 DMA mapping framework by default aligns all buffers to the smallest 157 PAGE_SIZE order which is greater than or equal to the requested buffer 158 size. This works well for buffers up to a few hundreds kilobytes, but 159 for larger buffers it just a waste of address space. Drivers which has 160 relatively small addressing window (like 64Mib) might run out of 161 virtual space with just a few allocations. 162 163 With this parameter you can specify the maximum PAGE_SIZE order for 164 DMA IOMMU buffers. Larger buffers will be aligned only to this 165 specified order. The order is expressed as a power of two multiplied 166 by the PAGE_SIZE. 167 168endif 169 170config SYS_SUPPORTS_APM_EMULATION 171 bool 172 173config HAVE_TCM 174 bool 175 select GENERIC_ALLOCATOR 176 177config HAVE_PROC_CPU 178 bool 179 180config NO_IOPORT_MAP 181 bool 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config ARCH_HAS_ILOG2_U32 199 bool 200 201config ARCH_HAS_ILOG2_U64 202 bool 203 204config ARCH_HAS_BANDGAP 205 bool 206 207config FIX_EARLYCON_MEM 208 def_bool y if MMU 209 210config GENERIC_HWEIGHT 211 bool 212 default y 213 214config GENERIC_CALIBRATE_DELAY 215 bool 216 default y 217 218config ARCH_MAY_HAVE_PC_FDC 219 bool 220 221config ARCH_SUPPORTS_UPROBES 222 def_bool y 223 224config ARCH_HAS_DMA_SET_COHERENT_MASK 225 bool 226 227config GENERIC_ISA_DMA 228 bool 229 230config FIQ 231 bool 232 233config NEED_RET_TO_USER 234 bool 235 236config ARCH_MTD_XIP 237 bool 238 239config ARM_PATCH_PHYS_VIRT 240 bool "Patch physical to virtual translations at runtime" if EMBEDDED 241 default y 242 depends on !XIP_KERNEL && MMU 243 help 244 Patch phys-to-virt and virt-to-phys translation functions at 245 boot and module load time according to the position of the 246 kernel in system memory. 247 248 This can only be used with non-XIP MMU kernels where the base 249 of physical memory is at a 2 MiB boundary. 250 251 Only disable this option if you know that you do not require 252 this feature (eg, building a kernel for a single machine) and 253 you need to shrink the kernel to the minimal size. 254 255config NEED_MACH_IO_H 256 bool 257 help 258 Select this when mach/io.h is required to provide special 259 definitions for this platform. The need for mach/io.h should 260 be avoided when possible. 261 262config NEED_MACH_MEMORY_H 263 bool 264 help 265 Select this when mach/memory.h is required to provide special 266 definitions for this platform. The need for mach/memory.h should 267 be avoided when possible. 268 269config PHYS_OFFSET 270 hex "Physical address of main memory" if MMU 271 depends on !ARM_PATCH_PHYS_VIRT 272 default DRAM_BASE if !MMU 273 default 0x00000000 if ARCH_FOOTBRIDGE 274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 275 default 0x20000000 if ARCH_S5PV210 276 default 0xc0000000 if ARCH_SA1100 277 help 278 Please provide the physical address corresponding to the 279 location of main memory in your system. 280 281config GENERIC_BUG 282 def_bool y 283 depends on BUG 284 285config PGTABLE_LEVELS 286 int 287 default 3 if ARM_LPAE 288 default 2 289 290menu "System Type" 291 292config MMU 293 bool "MMU-based Paged Memory Management Support" 294 default y 295 help 296 Select if you want MMU-based virtualised addressing space 297 support by paged memory management. If unsure, say 'Y'. 298 299config ARCH_MMAP_RND_BITS_MIN 300 default 8 301 302config ARCH_MMAP_RND_BITS_MAX 303 default 14 if PAGE_OFFSET=0x40000000 304 default 15 if PAGE_OFFSET=0x80000000 305 default 16 306 307# 308# The "ARM system type" choice list is ordered alphabetically by option 309# text. Please add new entries in the option alphabetic order. 310# 311choice 312 prompt "ARM system type" 313 default ARM_SINGLE_ARMV7M if !MMU 314 default ARCH_MULTIPLATFORM if MMU 315 316config ARCH_MULTIPLATFORM 317 bool "Allow multiple platforms to be selected" 318 depends on MMU 319 select ARCH_FLATMEM_ENABLE 320 select ARCH_SPARSEMEM_ENABLE 321 select ARCH_SELECT_MEMORY_MODEL 322 select ARM_HAS_SG_CHAIN 323 select ARM_PATCH_PHYS_VIRT 324 select AUTO_ZRELADDR 325 select TIMER_OF 326 select COMMON_CLK 327 select GENERIC_IRQ_MULTI_HANDLER 328 select HAVE_PCI 329 select PCI_DOMAINS_GENERIC if PCI 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARM_NVIC 337 select AUTO_ZRELADDR 338 select TIMER_OF 339 select COMMON_CLK 340 select CPU_V7M 341 select NO_IOPORT_MAP 342 select SPARSE_IRQ 343 select USE_OF 344 345config ARCH_EP93XX 346 bool "EP93xx-based" 347 select ARCH_SPARSEMEM_ENABLE 348 select ARM_AMBA 349 imply ARM_PATCH_PHYS_VIRT 350 select ARM_VIC 351 select GENERIC_IRQ_MULTI_HANDLER 352 select AUTO_ZRELADDR 353 select CLKSRC_MMIO 354 select CPU_ARM920T 355 select GPIOLIB 356 select HAVE_LEGACY_CLK 357 help 358 This enables support for the Cirrus EP93xx series of CPUs. 359 360config ARCH_FOOTBRIDGE 361 bool "FootBridge" 362 select CPU_SA110 363 select FOOTBRIDGE 364 select HAVE_IDE 365 select NEED_MACH_IO_H if !MMU 366 select NEED_MACH_MEMORY_H 367 help 368 Support for systems based on the DC21285 companion chip 369 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 370 371config ARCH_IOP32X 372 bool "IOP32x-based" 373 depends on MMU 374 select CPU_XSCALE 375 select GPIO_IOP 376 select GPIOLIB 377 select NEED_RET_TO_USER 378 select FORCE_PCI 379 select PLAT_IOP 380 help 381 Support for Intel's 80219 and IOP32X (XScale) family of 382 processors. 383 384config ARCH_IXP4XX 385 bool "IXP4xx-based" 386 depends on MMU 387 select ARCH_HAS_DMA_SET_COHERENT_MASK 388 select ARCH_SUPPORTS_BIG_ENDIAN 389 select CPU_XSCALE 390 select DMABOUNCE if PCI 391 select GENERIC_IRQ_MULTI_HANDLER 392 select GPIO_IXP4XX 393 select GPIOLIB 394 select HAVE_PCI 395 select IXP4XX_IRQ 396 select IXP4XX_TIMER 397 # With the new PCI driver this is not needed 398 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 399 select USB_EHCI_BIG_ENDIAN_DESC 400 select USB_EHCI_BIG_ENDIAN_MMIO 401 help 402 Support for Intel's IXP4XX (XScale) family of processors. 403 404config ARCH_DOVE 405 bool "Marvell Dove" 406 select CPU_PJ4 407 select GENERIC_IRQ_MULTI_HANDLER 408 select GPIOLIB 409 select HAVE_PCI 410 select MVEBU_MBUS 411 select PINCTRL 412 select PINCTRL_DOVE 413 select PLAT_ORION_LEGACY 414 select SPARSE_IRQ 415 select PM_GENERIC_DOMAINS if PM 416 help 417 Support for the Marvell Dove SoC 88AP510 418 419config ARCH_PXA 420 bool "PXA2xx/PXA3xx-based" 421 depends on MMU 422 select ARCH_MTD_XIP 423 select ARM_CPU_SUSPEND if PM 424 select AUTO_ZRELADDR 425 select COMMON_CLK 426 select CLKSRC_PXA 427 select CLKSRC_MMIO 428 select TIMER_OF 429 select CPU_XSCALE if !CPU_XSC3 430 select GENERIC_IRQ_MULTI_HANDLER 431 select GPIO_PXA 432 select GPIOLIB 433 select HAVE_IDE 434 select IRQ_DOMAIN 435 select PLAT_PXA 436 select SPARSE_IRQ 437 help 438 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 439 440config ARCH_RPC 441 bool "RiscPC" 442 depends on MMU 443 select ARCH_ACORN 444 select ARCH_MAY_HAVE_PC_FDC 445 select ARCH_SPARSEMEM_ENABLE 446 select ARM_HAS_SG_CHAIN 447 select CPU_SA110 448 select FIQ 449 select HAVE_IDE 450 select HAVE_PATA_PLATFORM 451 select ISA_DMA_API 452 select LEGACY_TIMER_TICK 453 select NEED_MACH_IO_H 454 select NEED_MACH_MEMORY_H 455 select NO_IOPORT_MAP 456 help 457 On the Acorn Risc-PC, Linux can support the internal IDE disk and 458 CD-ROM interface, serial and parallel port, and the floppy drive. 459 460config ARCH_SA1100 461 bool "SA1100-based" 462 select ARCH_MTD_XIP 463 select ARCH_SPARSEMEM_ENABLE 464 select CLKSRC_MMIO 465 select CLKSRC_PXA 466 select TIMER_OF if OF 467 select COMMON_CLK 468 select CPU_FREQ 469 select CPU_SA1100 470 select GENERIC_IRQ_MULTI_HANDLER 471 select GPIOLIB 472 select HAVE_IDE 473 select IRQ_DOMAIN 474 select ISA 475 select NEED_MACH_MEMORY_H 476 select SPARSE_IRQ 477 help 478 Support for StrongARM 11x0 based boards. 479 480config ARCH_S3C24XX 481 bool "Samsung S3C24XX SoCs" 482 select ATAGS 483 select CLKSRC_SAMSUNG_PWM 484 select GPIO_SAMSUNG 485 select GPIOLIB 486 select GENERIC_IRQ_MULTI_HANDLER 487 select HAVE_S3C2410_I2C if I2C 488 select HAVE_S3C_RTC if RTC_CLASS 489 select NEED_MACH_IO_H 490 select S3C2410_WATCHDOG 491 select SAMSUNG_ATAGS 492 select USE_OF 493 select WATCHDOG 494 help 495 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 496 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 497 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 498 Samsung SMDK2410 development board (and derivatives). 499 500config ARCH_OMAP1 501 bool "TI OMAP1" 502 depends on MMU 503 select ARCH_OMAP 504 select CLKSRC_MMIO 505 select GENERIC_IRQ_CHIP 506 select GENERIC_IRQ_MULTI_HANDLER 507 select GPIOLIB 508 select HAVE_IDE 509 select HAVE_LEGACY_CLK 510 select IRQ_DOMAIN 511 select NEED_MACH_IO_H if PCCARD 512 select NEED_MACH_MEMORY_H 513 select SPARSE_IRQ 514 help 515 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 516 517endchoice 518 519menu "Multiple platform selection" 520 depends on ARCH_MULTIPLATFORM 521 522comment "CPU Core family selection" 523 524config ARCH_MULTI_V4 525 bool "ARMv4 based platforms (FA526)" 526 depends on !ARCH_MULTI_V6_V7 527 select ARCH_MULTI_V4_V5 528 select CPU_FA526 529 530config ARCH_MULTI_V4T 531 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 532 depends on !ARCH_MULTI_V6_V7 533 select ARCH_MULTI_V4_V5 534 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 535 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 536 CPU_ARM925T || CPU_ARM940T) 537 538config ARCH_MULTI_V5 539 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 540 depends on !ARCH_MULTI_V6_V7 541 select ARCH_MULTI_V4_V5 542 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 543 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 544 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 545 546config ARCH_MULTI_V4_V5 547 bool 548 549config ARCH_MULTI_V6 550 bool "ARMv6 based platforms (ARM11)" 551 select ARCH_MULTI_V6_V7 552 select CPU_V6K 553 554config ARCH_MULTI_V7 555 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 556 default y 557 select ARCH_MULTI_V6_V7 558 select CPU_V7 559 select HAVE_SMP 560 561config ARCH_MULTI_V6_V7 562 bool 563 select MIGHT_HAVE_CACHE_L2X0 564 565config ARCH_MULTI_CPU_AUTO 566 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 567 select ARCH_MULTI_V5 568 569endmenu 570 571config ARCH_VIRT 572 bool "Dummy Virtual Machine" 573 depends on ARCH_MULTI_V7 574 select ARM_AMBA 575 select ARM_GIC 576 select ARM_GIC_V2M if PCI 577 select ARM_GIC_V3 578 select ARM_GIC_V3_ITS if PCI 579 select ARM_PSCI 580 select HAVE_ARM_ARCH_TIMER 581 select ARCH_SUPPORTS_BIG_ENDIAN 582 583# 584# This is sorted alphabetically by mach-* pathname. However, plat-* 585# Kconfigs may be included either alphabetically (according to the 586# plat- suffix) or along side the corresponding mach-* source. 587# 588source "arch/arm/mach-actions/Kconfig" 589 590source "arch/arm/mach-alpine/Kconfig" 591 592source "arch/arm/mach-artpec/Kconfig" 593 594source "arch/arm/mach-asm9260/Kconfig" 595 596source "arch/arm/mach-aspeed/Kconfig" 597 598source "arch/arm/mach-at91/Kconfig" 599 600source "arch/arm/mach-axxia/Kconfig" 601 602source "arch/arm/mach-bcm/Kconfig" 603 604source "arch/arm/mach-berlin/Kconfig" 605 606source "arch/arm/mach-clps711x/Kconfig" 607 608source "arch/arm/mach-cns3xxx/Kconfig" 609 610source "arch/arm/mach-davinci/Kconfig" 611 612source "arch/arm/mach-digicolor/Kconfig" 613 614source "arch/arm/mach-dove/Kconfig" 615 616source "arch/arm/mach-ep93xx/Kconfig" 617 618source "arch/arm/mach-exynos/Kconfig" 619 620source "arch/arm/mach-footbridge/Kconfig" 621 622source "arch/arm/mach-gemini/Kconfig" 623 624source "arch/arm/mach-highbank/Kconfig" 625 626source "arch/arm/mach-hisi/Kconfig" 627 628source "arch/arm/mach-imx/Kconfig" 629 630source "arch/arm/mach-integrator/Kconfig" 631 632source "arch/arm/mach-iop32x/Kconfig" 633 634source "arch/arm/mach-ixp4xx/Kconfig" 635 636source "arch/arm/mach-keystone/Kconfig" 637 638source "arch/arm/mach-lpc32xx/Kconfig" 639 640source "arch/arm/mach-mediatek/Kconfig" 641 642source "arch/arm/mach-meson/Kconfig" 643 644source "arch/arm/mach-milbeaut/Kconfig" 645 646source "arch/arm/mach-mmp/Kconfig" 647 648source "arch/arm/mach-moxart/Kconfig" 649 650source "arch/arm/mach-mstar/Kconfig" 651 652source "arch/arm/mach-mv78xx0/Kconfig" 653 654source "arch/arm/mach-mvebu/Kconfig" 655 656source "arch/arm/mach-mxs/Kconfig" 657 658source "arch/arm/mach-nomadik/Kconfig" 659 660source "arch/arm/mach-npcm/Kconfig" 661 662source "arch/arm/mach-nspire/Kconfig" 663 664source "arch/arm/plat-omap/Kconfig" 665 666source "arch/arm/mach-omap1/Kconfig" 667 668source "arch/arm/mach-omap2/Kconfig" 669 670source "arch/arm/mach-orion5x/Kconfig" 671 672source "arch/arm/mach-oxnas/Kconfig" 673 674source "arch/arm/mach-pxa/Kconfig" 675source "arch/arm/plat-pxa/Kconfig" 676 677source "arch/arm/mach-qcom/Kconfig" 678 679source "arch/arm/mach-rda/Kconfig" 680 681source "arch/arm/mach-realtek/Kconfig" 682 683source "arch/arm/mach-realview/Kconfig" 684 685source "arch/arm/mach-rockchip/Kconfig" 686 687source "arch/arm/mach-s3c/Kconfig" 688 689source "arch/arm/mach-s5pv210/Kconfig" 690 691source "arch/arm/mach-sa1100/Kconfig" 692 693source "arch/arm/mach-shmobile/Kconfig" 694 695source "arch/arm/mach-socfpga/Kconfig" 696 697source "arch/arm/mach-spear/Kconfig" 698 699source "arch/arm/mach-sti/Kconfig" 700 701source "arch/arm/mach-stm32/Kconfig" 702 703source "arch/arm/mach-sunxi/Kconfig" 704 705source "arch/arm/mach-tegra/Kconfig" 706 707source "arch/arm/mach-uniphier/Kconfig" 708 709source "arch/arm/mach-ux500/Kconfig" 710 711source "arch/arm/mach-versatile/Kconfig" 712 713source "arch/arm/mach-vexpress/Kconfig" 714 715source "arch/arm/mach-vt8500/Kconfig" 716 717source "arch/arm/mach-zynq/Kconfig" 718 719# ARMv7-M architecture 720config ARCH_LPC18XX 721 bool "NXP LPC18xx/LPC43xx" 722 depends on ARM_SINGLE_ARMV7M 723 select ARCH_HAS_RESET_CONTROLLER 724 select ARM_AMBA 725 select CLKSRC_LPC32XX 726 select PINCTRL 727 help 728 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 729 high performance microcontrollers. 730 731config ARCH_MPS2 732 bool "ARM MPS2 platform" 733 depends on ARM_SINGLE_ARMV7M 734 select ARM_AMBA 735 select CLKSRC_MPS2 736 help 737 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 738 with a range of available cores like Cortex-M3/M4/M7. 739 740 Please, note that depends which Application Note is used memory map 741 for the platform may vary, so adjustment of RAM base might be needed. 742 743# Definitions to make life easier 744config ARCH_ACORN 745 bool 746 747config PLAT_IOP 748 bool 749 750config PLAT_ORION 751 bool 752 select CLKSRC_MMIO 753 select COMMON_CLK 754 select GENERIC_IRQ_CHIP 755 select IRQ_DOMAIN 756 757config PLAT_ORION_LEGACY 758 bool 759 select PLAT_ORION 760 761config PLAT_PXA 762 bool 763 764config PLAT_VERSATILE 765 bool 766 767source "arch/arm/mm/Kconfig" 768 769config IWMMXT 770 bool "Enable iWMMXt support" 771 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 772 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 773 help 774 Enable support for iWMMXt context switching at run time if 775 running on a CPU that supports it. 776 777if !MMU 778source "arch/arm/Kconfig-nommu" 779endif 780 781config PJ4B_ERRATA_4742 782 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 783 depends on CPU_PJ4B && MACH_ARMADA_370 784 default y 785 help 786 When coming out of either a Wait for Interrupt (WFI) or a Wait for 787 Event (WFE) IDLE states, a specific timing sensitivity exists between 788 the retiring WFI/WFE instructions and the newly issued subsequent 789 instructions. This sensitivity can result in a CPU hang scenario. 790 Workaround: 791 The software must insert either a Data Synchronization Barrier (DSB) 792 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 793 instruction 794 795config ARM_ERRATA_326103 796 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 797 depends on CPU_V6 798 help 799 Executing a SWP instruction to read-only memory does not set bit 11 800 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 801 treat the access as a read, preventing a COW from occurring and 802 causing the faulting task to livelock. 803 804config ARM_ERRATA_411920 805 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 806 depends on CPU_V6 || CPU_V6K 807 help 808 Invalidation of the Instruction Cache operation can 809 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 810 It does not affect the MPCore. This option enables the ARM Ltd. 811 recommended workaround. 812 813config ARM_ERRATA_430973 814 bool "ARM errata: Stale prediction on replaced interworking branch" 815 depends on CPU_V7 816 help 817 This option enables the workaround for the 430973 Cortex-A8 818 r1p* erratum. If a code sequence containing an ARM/Thumb 819 interworking branch is replaced with another code sequence at the 820 same virtual address, whether due to self-modifying code or virtual 821 to physical address re-mapping, Cortex-A8 does not recover from the 822 stale interworking branch prediction. This results in Cortex-A8 823 executing the new code sequence in the incorrect ARM or Thumb state. 824 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 825 and also flushes the branch target cache at every context switch. 826 Note that setting specific bits in the ACTLR register may not be 827 available in non-secure mode. 828 829config ARM_ERRATA_458693 830 bool "ARM errata: Processor deadlock when a false hazard is created" 831 depends on CPU_V7 832 depends on !ARCH_MULTIPLATFORM 833 help 834 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 835 erratum. For very specific sequences of memory operations, it is 836 possible for a hazard condition intended for a cache line to instead 837 be incorrectly associated with a different cache line. This false 838 hazard might then cause a processor deadlock. The workaround enables 839 the L1 caching of the NEON accesses and disables the PLD instruction 840 in the ACTLR register. Note that setting specific bits in the ACTLR 841 register may not be available in non-secure mode. 842 843config ARM_ERRATA_460075 844 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 845 depends on CPU_V7 846 depends on !ARCH_MULTIPLATFORM 847 help 848 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 849 erratum. Any asynchronous access to the L2 cache may encounter a 850 situation in which recent store transactions to the L2 cache are lost 851 and overwritten with stale memory contents from external memory. The 852 workaround disables the write-allocate mode for the L2 cache via the 853 ACTLR register. Note that setting specific bits in the ACTLR register 854 may not be available in non-secure mode. 855 856config ARM_ERRATA_742230 857 bool "ARM errata: DMB operation may be faulty" 858 depends on CPU_V7 && SMP 859 depends on !ARCH_MULTIPLATFORM 860 help 861 This option enables the workaround for the 742230 Cortex-A9 862 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 863 between two write operations may not ensure the correct visibility 864 ordering of the two writes. This workaround sets a specific bit in 865 the diagnostic register of the Cortex-A9 which causes the DMB 866 instruction to behave as a DSB, ensuring the correct behaviour of 867 the two writes. 868 869config ARM_ERRATA_742231 870 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 871 depends on CPU_V7 && SMP 872 depends on !ARCH_MULTIPLATFORM 873 help 874 This option enables the workaround for the 742231 Cortex-A9 875 (r2p0..r2p2) erratum. Under certain conditions, specific to the 876 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 877 accessing some data located in the same cache line, may get corrupted 878 data due to bad handling of the address hazard when the line gets 879 replaced from one of the CPUs at the same time as another CPU is 880 accessing it. This workaround sets specific bits in the diagnostic 881 register of the Cortex-A9 which reduces the linefill issuing 882 capabilities of the processor. 883 884config ARM_ERRATA_643719 885 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 886 depends on CPU_V7 && SMP 887 default y 888 help 889 This option enables the workaround for the 643719 Cortex-A9 (prior to 890 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 891 register returns zero when it should return one. The workaround 892 corrects this value, ensuring cache maintenance operations which use 893 it behave as intended and avoiding data corruption. 894 895config ARM_ERRATA_720789 896 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 897 depends on CPU_V7 898 help 899 This option enables the workaround for the 720789 Cortex-A9 (prior to 900 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 901 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 902 As a consequence of this erratum, some TLB entries which should be 903 invalidated are not, resulting in an incoherency in the system page 904 tables. The workaround changes the TLB flushing routines to invalidate 905 entries regardless of the ASID. 906 907config ARM_ERRATA_743622 908 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 909 depends on CPU_V7 910 depends on !ARCH_MULTIPLATFORM 911 help 912 This option enables the workaround for the 743622 Cortex-A9 913 (r2p*) erratum. Under very rare conditions, a faulty 914 optimisation in the Cortex-A9 Store Buffer may lead to data 915 corruption. This workaround sets a specific bit in the diagnostic 916 register of the Cortex-A9 which disables the Store Buffer 917 optimisation, preventing the defect from occurring. This has no 918 visible impact on the overall performance or power consumption of the 919 processor. 920 921config ARM_ERRATA_751472 922 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 923 depends on CPU_V7 924 depends on !ARCH_MULTIPLATFORM 925 help 926 This option enables the workaround for the 751472 Cortex-A9 (prior 927 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 928 completion of a following broadcasted operation if the second 929 operation is received by a CPU before the ICIALLUIS has completed, 930 potentially leading to corrupted entries in the cache or TLB. 931 932config ARM_ERRATA_754322 933 bool "ARM errata: possible faulty MMU translations following an ASID switch" 934 depends on CPU_V7 935 help 936 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 937 r3p*) erratum. A speculative memory access may cause a page table walk 938 which starts prior to an ASID switch but completes afterwards. This 939 can populate the micro-TLB with a stale entry which may be hit with 940 the new ASID. This workaround places two dsb instructions in the mm 941 switching code so that no page table walks can cross the ASID switch. 942 943config ARM_ERRATA_754327 944 bool "ARM errata: no automatic Store Buffer drain" 945 depends on CPU_V7 && SMP 946 help 947 This option enables the workaround for the 754327 Cortex-A9 (prior to 948 r2p0) erratum. The Store Buffer does not have any automatic draining 949 mechanism and therefore a livelock may occur if an external agent 950 continuously polls a memory location waiting to observe an update. 951 This workaround defines cpu_relax() as smp_mb(), preventing correctly 952 written polling loops from denying visibility of updates to memory. 953 954config ARM_ERRATA_364296 955 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 956 depends on CPU_V6 957 help 958 This options enables the workaround for the 364296 ARM1136 959 r0p2 erratum (possible cache data corruption with 960 hit-under-miss enabled). It sets the undocumented bit 31 in 961 the auxiliary control register and the FI bit in the control 962 register, thus disabling hit-under-miss without putting the 963 processor into full low interrupt latency mode. ARM11MPCore 964 is not affected. 965 966config ARM_ERRATA_764369 967 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 968 depends on CPU_V7 && SMP 969 help 970 This option enables the workaround for erratum 764369 971 affecting Cortex-A9 MPCore with two or more processors (all 972 current revisions). Under certain timing circumstances, a data 973 cache line maintenance operation by MVA targeting an Inner 974 Shareable memory region may fail to proceed up to either the 975 Point of Coherency or to the Point of Unification of the 976 system. This workaround adds a DSB instruction before the 977 relevant cache maintenance functions and sets a specific bit 978 in the diagnostic control register of the SCU. 979 980config ARM_ERRATA_775420 981 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 982 depends on CPU_V7 983 help 984 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 985 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 986 operation aborts with MMU exception, it might cause the processor 987 to deadlock. This workaround puts DSB before executing ISB if 988 an abort may occur on cache maintenance. 989 990config ARM_ERRATA_798181 991 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 992 depends on CPU_V7 && SMP 993 help 994 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 995 adequately shooting down all use of the old entries. This 996 option enables the Linux kernel workaround for this erratum 997 which sends an IPI to the CPUs that are running the same ASID 998 as the one being invalidated. 999 1000config ARM_ERRATA_773022 1001 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1002 depends on CPU_V7 1003 help 1004 This option enables the workaround for the 773022 Cortex-A15 1005 (up to r0p4) erratum. In certain rare sequences of code, the 1006 loop buffer may deliver incorrect instructions. This 1007 workaround disables the loop buffer to avoid the erratum. 1008 1009config ARM_ERRATA_818325_852422 1010 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1011 depends on CPU_V7 1012 help 1013 This option enables the workaround for: 1014 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1015 instruction might deadlock. Fixed in r0p1. 1016 - Cortex-A12 852422: Execution of a sequence of instructions might 1017 lead to either a data corruption or a CPU deadlock. Not fixed in 1018 any Cortex-A12 cores yet. 1019 This workaround for all both errata involves setting bit[12] of the 1020 Feature Register. This bit disables an optimisation applied to a 1021 sequence of 2 instructions that use opposing condition codes. 1022 1023config ARM_ERRATA_821420 1024 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1025 depends on CPU_V7 1026 help 1027 This option enables the workaround for the 821420 Cortex-A12 1028 (all revs) erratum. In very rare timing conditions, a sequence 1029 of VMOV to Core registers instructions, for which the second 1030 one is in the shadow of a branch or abort, can lead to a 1031 deadlock when the VMOV instructions are issued out-of-order. 1032 1033config ARM_ERRATA_825619 1034 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1035 depends on CPU_V7 1036 help 1037 This option enables the workaround for the 825619 Cortex-A12 1038 (all revs) erratum. Within rare timing constraints, executing a 1039 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1040 and Device/Strongly-Ordered loads and stores might cause deadlock 1041 1042config ARM_ERRATA_857271 1043 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1044 depends on CPU_V7 1045 help 1046 This option enables the workaround for the 857271 Cortex-A12 1047 (all revs) erratum. Under very rare timing conditions, the CPU might 1048 hang. The workaround is expected to have a < 1% performance impact. 1049 1050config ARM_ERRATA_852421 1051 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for the 852421 Cortex-A17 1055 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1056 execution of a DMB ST instruction might fail to properly order 1057 stores from GroupA and stores from GroupB. 1058 1059config ARM_ERRATA_852423 1060 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1061 depends on CPU_V7 1062 help 1063 This option enables the workaround for: 1064 - Cortex-A17 852423: Execution of a sequence of instructions might 1065 lead to either a data corruption or a CPU deadlock. Not fixed in 1066 any Cortex-A17 cores yet. 1067 This is identical to Cortex-A12 erratum 852422. It is a separate 1068 config option from the A12 erratum due to the way errata are checked 1069 for and handled. 1070 1071config ARM_ERRATA_857272 1072 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1073 depends on CPU_V7 1074 help 1075 This option enables the workaround for the 857272 Cortex-A17 erratum. 1076 This erratum is not known to be fixed in any A17 revision. 1077 This is identical to Cortex-A12 erratum 857271. It is a separate 1078 config option from the A12 erratum due to the way errata are checked 1079 for and handled. 1080 1081endmenu 1082 1083source "arch/arm/common/Kconfig" 1084 1085menu "Bus support" 1086 1087config ISA 1088 bool 1089 help 1090 Find out whether you have ISA slots on your motherboard. ISA is the 1091 name of a bus system, i.e. the way the CPU talks to the other stuff 1092 inside your box. Other bus systems are PCI, EISA, MicroChannel 1093 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1094 newer boards don't support it. If you have ISA, say Y, otherwise N. 1095 1096# Select ISA DMA controller support 1097config ISA_DMA 1098 bool 1099 select ISA_DMA_API 1100 1101# Select ISA DMA interface 1102config ISA_DMA_API 1103 bool 1104 1105config PCI_NANOENGINE 1106 bool "BSE nanoEngine PCI support" 1107 depends on SA1100_NANOENGINE 1108 help 1109 Enable PCI on the BSE nanoEngine board. 1110 1111config ARM_ERRATA_814220 1112 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1113 depends on CPU_V7 1114 help 1115 The v7 ARM states that all cache and branch predictor maintenance 1116 operations that do not specify an address execute, relative to 1117 each other, in program order. 1118 However, because of this erratum, an L2 set/way cache maintenance 1119 operation can overtake an L1 set/way cache maintenance operation. 1120 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1121 r0p4, r0p5. 1122 1123endmenu 1124 1125menu "Kernel Features" 1126 1127config HAVE_SMP 1128 bool 1129 help 1130 This option should be selected by machines which have an SMP- 1131 capable CPU. 1132 1133 The only effect of this option is to make the SMP-related 1134 options available to the user for configuration. 1135 1136config SMP 1137 bool "Symmetric Multi-Processing" 1138 depends on CPU_V6K || CPU_V7 1139 depends on HAVE_SMP 1140 depends on MMU || ARM_MPU 1141 select IRQ_WORK 1142 help 1143 This enables support for systems with more than one CPU. If you have 1144 a system with only one CPU, say N. If you have a system with more 1145 than one CPU, say Y. 1146 1147 If you say N here, the kernel will run on uni- and multiprocessor 1148 machines, but will use only one CPU of a multiprocessor machine. If 1149 you say Y here, the kernel will run on many, but not all, 1150 uniprocessor machines. On a uniprocessor machine, the kernel 1151 will run faster if you say N here. 1152 1153 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1154 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1155 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1156 1157 If you don't know what to do here, say N. 1158 1159config SMP_ON_UP 1160 bool "Allow booting SMP kernel on uniprocessor systems" 1161 depends on SMP && !XIP_KERNEL && MMU 1162 default y 1163 help 1164 SMP kernels contain instructions which fail on non-SMP processors. 1165 Enabling this option allows the kernel to modify itself to make 1166 these instructions safe. Disabling it allows about 1K of space 1167 savings. 1168 1169 If you don't know what to do here, say Y. 1170 1171config ARM_CPU_TOPOLOGY 1172 bool "Support cpu topology definition" 1173 depends on SMP && CPU_V7 1174 default y 1175 help 1176 Support ARM cpu topology definition. The MPIDR register defines 1177 affinity between processors which is then used to describe the cpu 1178 topology of an ARM System. 1179 1180config SCHED_MC 1181 bool "Multi-core scheduler support" 1182 depends on ARM_CPU_TOPOLOGY 1183 help 1184 Multi-core scheduler support improves the CPU scheduler's decision 1185 making when dealing with multi-core CPU chips at a cost of slightly 1186 increased overhead in some places. If unsure say N here. 1187 1188config SCHED_SMT 1189 bool "SMT scheduler support" 1190 depends on ARM_CPU_TOPOLOGY 1191 help 1192 Improves the CPU scheduler's decision making when dealing with 1193 MultiThreading at a cost of slightly increased overhead in some 1194 places. If unsure say N here. 1195 1196config HAVE_ARM_SCU 1197 bool 1198 help 1199 This option enables support for the ARM snoop control unit 1200 1201config HAVE_ARM_ARCH_TIMER 1202 bool "Architected timer support" 1203 depends on CPU_V7 1204 select ARM_ARCH_TIMER 1205 help 1206 This option enables support for the ARM architected timer 1207 1208config HAVE_ARM_TWD 1209 bool 1210 help 1211 This options enables support for the ARM timer and watchdog unit 1212 1213config MCPM 1214 bool "Multi-Cluster Power Management" 1215 depends on CPU_V7 && SMP 1216 help 1217 This option provides the common power management infrastructure 1218 for (multi-)cluster based systems, such as big.LITTLE based 1219 systems. 1220 1221config MCPM_QUAD_CLUSTER 1222 bool 1223 depends on MCPM 1224 help 1225 To avoid wasting resources unnecessarily, MCPM only supports up 1226 to 2 clusters by default. 1227 Platforms with 3 or 4 clusters that use MCPM must select this 1228 option to allow the additional clusters to be managed. 1229 1230config BIG_LITTLE 1231 bool "big.LITTLE support (Experimental)" 1232 depends on CPU_V7 && SMP 1233 select MCPM 1234 help 1235 This option enables support selections for the big.LITTLE 1236 system architecture. 1237 1238config BL_SWITCHER 1239 bool "big.LITTLE switcher support" 1240 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1241 select CPU_PM 1242 help 1243 The big.LITTLE "switcher" provides the core functionality to 1244 transparently handle transition between a cluster of A15's 1245 and a cluster of A7's in a big.LITTLE system. 1246 1247config BL_SWITCHER_DUMMY_IF 1248 tristate "Simple big.LITTLE switcher user interface" 1249 depends on BL_SWITCHER && DEBUG_KERNEL 1250 help 1251 This is a simple and dummy char dev interface to control 1252 the big.LITTLE switcher core code. It is meant for 1253 debugging purposes only. 1254 1255choice 1256 prompt "Memory split" 1257 depends on MMU 1258 default VMSPLIT_3G 1259 help 1260 Select the desired split between kernel and user memory. 1261 1262 If you are not absolutely sure what you are doing, leave this 1263 option alone! 1264 1265 config VMSPLIT_3G 1266 bool "3G/1G user/kernel split" 1267 config VMSPLIT_3G_OPT 1268 depends on !ARM_LPAE 1269 bool "3G/1G user/kernel split (for full 1G low memory)" 1270 config VMSPLIT_2G 1271 bool "2G/2G user/kernel split" 1272 config VMSPLIT_1G 1273 bool "1G/3G user/kernel split" 1274endchoice 1275 1276config PAGE_OFFSET 1277 hex 1278 default PHYS_OFFSET if !MMU 1279 default 0x40000000 if VMSPLIT_1G 1280 default 0x80000000 if VMSPLIT_2G 1281 default 0xB0000000 if VMSPLIT_3G_OPT 1282 default 0xC0000000 1283 1284config KASAN_SHADOW_OFFSET 1285 hex 1286 depends on KASAN 1287 default 0x1f000000 if PAGE_OFFSET=0x40000000 1288 default 0x5f000000 if PAGE_OFFSET=0x80000000 1289 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1290 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1291 default 0xffffffff 1292 1293config NR_CPUS 1294 int "Maximum number of CPUs (2-32)" 1295 range 2 16 if DEBUG_KMAP_LOCAL 1296 range 2 32 if !DEBUG_KMAP_LOCAL 1297 depends on SMP 1298 default "4" 1299 help 1300 The maximum number of CPUs that the kernel can support. 1301 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1302 debugging is enabled, which uses half of the per-CPU fixmap 1303 slots as guard regions. 1304 1305config HOTPLUG_CPU 1306 bool "Support for hot-pluggable CPUs" 1307 depends on SMP 1308 select GENERIC_IRQ_MIGRATION 1309 help 1310 Say Y here to experiment with turning CPUs off and on. CPUs 1311 can be controlled through /sys/devices/system/cpu. 1312 1313config ARM_PSCI 1314 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1315 depends on HAVE_ARM_SMCCC 1316 select ARM_PSCI_FW 1317 help 1318 Say Y here if you want Linux to communicate with system firmware 1319 implementing the PSCI specification for CPU-centric power 1320 management operations described in ARM document number ARM DEN 1321 0022A ("Power State Coordination Interface System Software on 1322 ARM processors"). 1323 1324# The GPIO number here must be sorted by descending number. In case of 1325# a multiplatform kernel, we just want the highest value required by the 1326# selected platforms. 1327config ARCH_NR_GPIO 1328 int 1329 default 2048 if ARCH_INTEL_SOCFPGA 1330 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1331 ARCH_ZYNQ || ARCH_ASPEED 1332 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1333 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1334 default 416 if ARCH_SUNXI 1335 default 392 if ARCH_U8500 1336 default 352 if ARCH_VT8500 1337 default 288 if ARCH_ROCKCHIP 1338 default 264 if MACH_H4700 1339 default 0 1340 help 1341 Maximum number of GPIOs in the system. 1342 1343 If unsure, leave the default value. 1344 1345config HZ_FIXED 1346 int 1347 default 128 if SOC_AT91RM9200 1348 default 0 1349 1350choice 1351 depends on HZ_FIXED = 0 1352 prompt "Timer frequency" 1353 1354config HZ_100 1355 bool "100 Hz" 1356 1357config HZ_200 1358 bool "200 Hz" 1359 1360config HZ_250 1361 bool "250 Hz" 1362 1363config HZ_300 1364 bool "300 Hz" 1365 1366config HZ_500 1367 bool "500 Hz" 1368 1369config HZ_1000 1370 bool "1000 Hz" 1371 1372endchoice 1373 1374config HZ 1375 int 1376 default HZ_FIXED if HZ_FIXED != 0 1377 default 100 if HZ_100 1378 default 200 if HZ_200 1379 default 250 if HZ_250 1380 default 300 if HZ_300 1381 default 500 if HZ_500 1382 default 1000 1383 1384config SCHED_HRTICK 1385 def_bool HIGH_RES_TIMERS 1386 1387config THUMB2_KERNEL 1388 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1389 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1390 default y if CPU_THUMBONLY 1391 select ARM_UNWIND 1392 help 1393 By enabling this option, the kernel will be compiled in 1394 Thumb-2 mode. 1395 1396 If unsure, say N. 1397 1398config ARM_PATCH_IDIV 1399 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1400 depends on CPU_32v7 && !XIP_KERNEL 1401 default y 1402 help 1403 The ARM compiler inserts calls to __aeabi_idiv() and 1404 __aeabi_uidiv() when it needs to perform division on signed 1405 and unsigned integers. Some v7 CPUs have support for the sdiv 1406 and udiv instructions that can be used to implement those 1407 functions. 1408 1409 Enabling this option allows the kernel to modify itself to 1410 replace the first two instructions of these library functions 1411 with the sdiv or udiv plus "bx lr" instructions when the CPU 1412 it is running on supports them. Typically this will be faster 1413 and less power intensive than running the original library 1414 code to do integer division. 1415 1416config AEABI 1417 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1418 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1419 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1420 help 1421 This option allows for the kernel to be compiled using the latest 1422 ARM ABI (aka EABI). This is only useful if you are using a user 1423 space environment that is also compiled with EABI. 1424 1425 Since there are major incompatibilities between the legacy ABI and 1426 EABI, especially with regard to structure member alignment, this 1427 option also changes the kernel syscall calling convention to 1428 disambiguate both ABIs and allow for backward compatibility support 1429 (selected with CONFIG_OABI_COMPAT). 1430 1431 To use this you need GCC version 4.0.0 or later. 1432 1433config OABI_COMPAT 1434 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1435 depends on AEABI && !THUMB2_KERNEL 1436 help 1437 This option preserves the old syscall interface along with the 1438 new (ARM EABI) one. It also provides a compatibility layer to 1439 intercept syscalls that have structure arguments which layout 1440 in memory differs between the legacy ABI and the new ARM EABI 1441 (only for non "thumb" binaries). This option adds a tiny 1442 overhead to all syscalls and produces a slightly larger kernel. 1443 1444 The seccomp filter system will not be available when this is 1445 selected, since there is no way yet to sensibly distinguish 1446 between calling conventions during filtering. 1447 1448 If you know you'll be using only pure EABI user space then you 1449 can say N here. If this option is not selected and you attempt 1450 to execute a legacy ABI binary then the result will be 1451 UNPREDICTABLE (in fact it can be predicted that it won't work 1452 at all). If in doubt say N. 1453 1454config ARCH_SELECT_MEMORY_MODEL 1455 bool 1456 1457config ARCH_FLATMEM_ENABLE 1458 bool 1459 1460config ARCH_SPARSEMEM_ENABLE 1461 bool 1462 select SPARSEMEM_STATIC if SPARSEMEM 1463 1464config HIGHMEM 1465 bool "High Memory Support" 1466 depends on MMU 1467 select KMAP_LOCAL 1468 help 1469 The address space of ARM processors is only 4 Gigabytes large 1470 and it has to accommodate user address space, kernel address 1471 space as well as some memory mapped IO. That means that, if you 1472 have a large amount of physical memory and/or IO, not all of the 1473 memory can be "permanently mapped" by the kernel. The physical 1474 memory that is not permanently mapped is called "high memory". 1475 1476 Depending on the selected kernel/user memory split, minimum 1477 vmalloc space and actual amount of RAM, you may not need this 1478 option which should result in a slightly faster kernel. 1479 1480 If unsure, say n. 1481 1482config HIGHPTE 1483 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1484 depends on HIGHMEM 1485 default y 1486 help 1487 The VM uses one page of physical memory for each page table. 1488 For systems with a lot of processes, this can use a lot of 1489 precious low memory, eventually leading to low memory being 1490 consumed by page tables. Setting this option will allow 1491 user-space 2nd level page tables to reside in high memory. 1492 1493config CPU_SW_DOMAIN_PAN 1494 bool "Enable use of CPU domains to implement privileged no-access" 1495 depends on MMU && !ARM_LPAE 1496 default y 1497 help 1498 Increase kernel security by ensuring that normal kernel accesses 1499 are unable to access userspace addresses. This can help prevent 1500 use-after-free bugs becoming an exploitable privilege escalation 1501 by ensuring that magic values (such as LIST_POISON) will always 1502 fault when dereferenced. 1503 1504 CPUs with low-vector mappings use a best-efforts implementation. 1505 Their lower 1MB needs to remain accessible for the vectors, but 1506 the remainder of userspace will become appropriately inaccessible. 1507 1508config HW_PERF_EVENTS 1509 def_bool y 1510 depends on ARM_PMU 1511 1512config ARCH_WANT_GENERAL_HUGETLB 1513 def_bool y 1514 1515config ARM_MODULE_PLTS 1516 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1517 depends on MODULES 1518 default y 1519 help 1520 Allocate PLTs when loading modules so that jumps and calls whose 1521 targets are too far away for their relative offsets to be encoded 1522 in the instructions themselves can be bounced via veneers in the 1523 module's PLT. This allows modules to be allocated in the generic 1524 vmalloc area after the dedicated module memory area has been 1525 exhausted. The modules will use slightly more memory, but after 1526 rounding up to page size, the actual memory footprint is usually 1527 the same. 1528 1529 Disabling this is usually safe for small single-platform 1530 configurations. If unsure, say y. 1531 1532config FORCE_MAX_ZONEORDER 1533 int "Maximum zone order" 1534 default "12" if SOC_AM33XX 1535 default "9" if SA1111 1536 default "11" 1537 help 1538 The kernel memory allocator divides physically contiguous memory 1539 blocks into "zones", where each zone is a power of two number of 1540 pages. This option selects the largest power of two that the kernel 1541 keeps in the memory allocator. If you need to allocate very large 1542 blocks of physically contiguous memory, then you may need to 1543 increase this value. 1544 1545 This config option is actually maximum order plus one. For example, 1546 a value of 11 means that the largest free memory block is 2^10 pages. 1547 1548config ALIGNMENT_TRAP 1549 def_bool CPU_CP15_MMU 1550 select HAVE_PROC_CPU if PROC_FS 1551 help 1552 ARM processors cannot fetch/store information which is not 1553 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1554 address divisible by 4. On 32-bit ARM processors, these non-aligned 1555 fetch/store instructions will be emulated in software if you say 1556 here, which has a severe performance impact. This is necessary for 1557 correct operation of some network protocols. With an IP-only 1558 configuration it is safe to say N, otherwise say Y. 1559 1560config UACCESS_WITH_MEMCPY 1561 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1562 depends on MMU 1563 default y if CPU_FEROCEON 1564 help 1565 Implement faster copy_to_user and clear_user methods for CPU 1566 cores where a 8-word STM instruction give significantly higher 1567 memory write throughput than a sequence of individual 32bit stores. 1568 1569 A possible side effect is a slight increase in scheduling latency 1570 between threads sharing the same address space if they invoke 1571 such copy operations with large buffers. 1572 1573 However, if the CPU data cache is using a write-allocate mode, 1574 this option is unlikely to provide any performance gain. 1575 1576config PARAVIRT 1577 bool "Enable paravirtualization code" 1578 help 1579 This changes the kernel so it can modify itself when it is run 1580 under a hypervisor, potentially improving performance significantly 1581 over full virtualization. 1582 1583config PARAVIRT_TIME_ACCOUNTING 1584 bool "Paravirtual steal time accounting" 1585 select PARAVIRT 1586 help 1587 Select this option to enable fine granularity task steal time 1588 accounting. Time spent executing other tasks in parallel with 1589 the current vCPU is discounted from the vCPU power. To account for 1590 that, there can be a small performance impact. 1591 1592 If in doubt, say N here. 1593 1594config XEN_DOM0 1595 def_bool y 1596 depends on XEN 1597 1598config XEN 1599 bool "Xen guest support on ARM" 1600 depends on ARM && AEABI && OF 1601 depends on CPU_V7 && !CPU_V6 1602 depends on !GENERIC_ATOMIC64 1603 depends on MMU 1604 select ARCH_DMA_ADDR_T_64BIT 1605 select ARM_PSCI 1606 select SWIOTLB 1607 select SWIOTLB_XEN 1608 select PARAVIRT 1609 help 1610 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1611 1612config STACKPROTECTOR_PER_TASK 1613 bool "Use a unique stack canary value for each task" 1614 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1615 select GCC_PLUGIN_ARM_SSP_PER_TASK 1616 default y 1617 help 1618 Due to the fact that GCC uses an ordinary symbol reference from 1619 which to load the value of the stack canary, this value can only 1620 change at reboot time on SMP systems, and all tasks running in the 1621 kernel's address space are forced to use the same canary value for 1622 the entire duration that the system is up. 1623 1624 Enable this option to switch to a different method that uses a 1625 different canary value for each task. 1626 1627endmenu 1628 1629menu "Boot options" 1630 1631config USE_OF 1632 bool "Flattened Device Tree support" 1633 select IRQ_DOMAIN 1634 select OF 1635 help 1636 Include support for flattened device tree machine descriptions. 1637 1638config ATAGS 1639 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1640 default y 1641 help 1642 This is the traditional way of passing data to the kernel at boot 1643 time. If you are solely relying on the flattened device tree (or 1644 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1645 to remove ATAGS support from your kernel binary. If unsure, 1646 leave this to y. 1647 1648config DEPRECATED_PARAM_STRUCT 1649 bool "Provide old way to pass kernel parameters" 1650 depends on ATAGS 1651 help 1652 This was deprecated in 2001 and announced to live on for 5 years. 1653 Some old boot loaders still use this way. 1654 1655# Compressed boot loader in ROM. Yes, we really want to ask about 1656# TEXT and BSS so we preserve their values in the config files. 1657config ZBOOT_ROM_TEXT 1658 hex "Compressed ROM boot loader base address" 1659 default 0x0 1660 help 1661 The physical address at which the ROM-able zImage is to be 1662 placed in the target. Platforms which normally make use of 1663 ROM-able zImage formats normally set this to a suitable 1664 value in their defconfig file. 1665 1666 If ZBOOT_ROM is not enabled, this has no effect. 1667 1668config ZBOOT_ROM_BSS 1669 hex "Compressed ROM boot loader BSS address" 1670 default 0x0 1671 help 1672 The base address of an area of read/write memory in the target 1673 for the ROM-able zImage which must be available while the 1674 decompressor is running. It must be large enough to hold the 1675 entire decompressed kernel plus an additional 128 KiB. 1676 Platforms which normally make use of ROM-able zImage formats 1677 normally set this to a suitable value in their defconfig file. 1678 1679 If ZBOOT_ROM is not enabled, this has no effect. 1680 1681config ZBOOT_ROM 1682 bool "Compressed boot loader in ROM/flash" 1683 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1684 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1685 help 1686 Say Y here if you intend to execute your compressed kernel image 1687 (zImage) directly from ROM or flash. If unsure, say N. 1688 1689config ARM_APPENDED_DTB 1690 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1691 depends on OF 1692 help 1693 With this option, the boot code will look for a device tree binary 1694 (DTB) appended to zImage 1695 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1696 1697 This is meant as a backward compatibility convenience for those 1698 systems with a bootloader that can't be upgraded to accommodate 1699 the documented boot protocol using a device tree. 1700 1701 Beware that there is very little in terms of protection against 1702 this option being confused by leftover garbage in memory that might 1703 look like a DTB header after a reboot if no actual DTB is appended 1704 to zImage. Do not leave this option active in a production kernel 1705 if you don't intend to always append a DTB. Proper passing of the 1706 location into r2 of a bootloader provided DTB is always preferable 1707 to this option. 1708 1709config ARM_ATAG_DTB_COMPAT 1710 bool "Supplement the appended DTB with traditional ATAG information" 1711 depends on ARM_APPENDED_DTB 1712 help 1713 Some old bootloaders can't be updated to a DTB capable one, yet 1714 they provide ATAGs with memory configuration, the ramdisk address, 1715 the kernel cmdline string, etc. Such information is dynamically 1716 provided by the bootloader and can't always be stored in a static 1717 DTB. To allow a device tree enabled kernel to be used with such 1718 bootloaders, this option allows zImage to extract the information 1719 from the ATAG list and store it at run time into the appended DTB. 1720 1721choice 1722 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1723 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1724 1725config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1726 bool "Use bootloader kernel arguments if available" 1727 help 1728 Uses the command-line options passed by the boot loader instead of 1729 the device tree bootargs property. If the boot loader doesn't provide 1730 any, the device tree bootargs property will be used. 1731 1732config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1733 bool "Extend with bootloader kernel arguments" 1734 help 1735 The command-line arguments provided by the boot loader will be 1736 appended to the the device tree bootargs property. 1737 1738endchoice 1739 1740config CMDLINE 1741 string "Default kernel command string" 1742 default "" 1743 help 1744 On some architectures (e.g. CATS), there is currently no way 1745 for the boot loader to pass arguments to the kernel. For these 1746 architectures, you should supply some command-line options at build 1747 time by entering them here. As a minimum, you should specify the 1748 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1749 1750choice 1751 prompt "Kernel command line type" if CMDLINE != "" 1752 default CMDLINE_FROM_BOOTLOADER 1753 depends on ATAGS 1754 1755config CMDLINE_FROM_BOOTLOADER 1756 bool "Use bootloader kernel arguments if available" 1757 help 1758 Uses the command-line options passed by the boot loader. If 1759 the boot loader doesn't provide any, the default kernel command 1760 string provided in CMDLINE will be used. 1761 1762config CMDLINE_EXTEND 1763 bool "Extend bootloader kernel arguments" 1764 help 1765 The command-line arguments provided by the boot loader will be 1766 appended to the default kernel command string. 1767 1768config CMDLINE_FORCE 1769 bool "Always use the default kernel command string" 1770 help 1771 Always use the default kernel command string, even if the boot 1772 loader passes other arguments to the kernel. 1773 This is useful if you cannot or don't want to change the 1774 command-line options your boot loader passes to the kernel. 1775endchoice 1776 1777config XIP_KERNEL 1778 bool "Kernel Execute-In-Place from ROM" 1779 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1780 help 1781 Execute-In-Place allows the kernel to run from non-volatile storage 1782 directly addressable by the CPU, such as NOR flash. This saves RAM 1783 space since the text section of the kernel is not loaded from flash 1784 to RAM. Read-write sections, such as the data section and stack, 1785 are still copied to RAM. The XIP kernel is not compressed since 1786 it has to run directly from flash, so it will take more space to 1787 store it. The flash address used to link the kernel object files, 1788 and for storing it, is configuration dependent. Therefore, if you 1789 say Y here, you must know the proper physical address where to 1790 store the kernel image depending on your own flash memory usage. 1791 1792 Also note that the make target becomes "make xipImage" rather than 1793 "make zImage" or "make Image". The final kernel binary to put in 1794 ROM memory will be arch/arm/boot/xipImage. 1795 1796 If unsure, say N. 1797 1798config XIP_PHYS_ADDR 1799 hex "XIP Kernel Physical Location" 1800 depends on XIP_KERNEL 1801 default "0x00080000" 1802 help 1803 This is the physical address in your flash memory the kernel will 1804 be linked for and stored to. This address is dependent on your 1805 own flash usage. 1806 1807config XIP_DEFLATED_DATA 1808 bool "Store kernel .data section compressed in ROM" 1809 depends on XIP_KERNEL 1810 select ZLIB_INFLATE 1811 help 1812 Before the kernel is actually executed, its .data section has to be 1813 copied to RAM from ROM. This option allows for storing that data 1814 in compressed form and decompressed to RAM rather than merely being 1815 copied, saving some precious ROM space. A possible drawback is a 1816 slightly longer boot delay. 1817 1818config KEXEC 1819 bool "Kexec system call (EXPERIMENTAL)" 1820 depends on (!SMP || PM_SLEEP_SMP) 1821 depends on MMU 1822 select KEXEC_CORE 1823 help 1824 kexec is a system call that implements the ability to shutdown your 1825 current kernel, and to start another kernel. It is like a reboot 1826 but it is independent of the system firmware. And like a reboot 1827 you can start any kernel with it, not just Linux. 1828 1829 It is an ongoing process to be certain the hardware in a machine 1830 is properly shutdown, so do not be surprised if this code does not 1831 initially work for you. 1832 1833config ATAGS_PROC 1834 bool "Export atags in procfs" 1835 depends on ATAGS && KEXEC 1836 default y 1837 help 1838 Should the atags used to boot the kernel be exported in an "atags" 1839 file in procfs. Useful with kexec. 1840 1841config CRASH_DUMP 1842 bool "Build kdump crash kernel (EXPERIMENTAL)" 1843 help 1844 Generate crash dump after being started by kexec. This should 1845 be normally only set in special crash dump kernels which are 1846 loaded in the main kernel with kexec-tools into a specially 1847 reserved region and then later executed after a crash by 1848 kdump/kexec. The crash dump kernel must be compiled to a 1849 memory address not used by the main kernel 1850 1851 For more details see Documentation/admin-guide/kdump/kdump.rst 1852 1853config AUTO_ZRELADDR 1854 bool "Auto calculation of the decompressed kernel image address" 1855 help 1856 ZRELADDR is the physical address where the decompressed kernel 1857 image will be placed. If AUTO_ZRELADDR is selected, the address 1858 will be determined at run-time, either by masking the current IP 1859 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1860 This assumes the zImage being placed in the first 128MB from 1861 start of memory. 1862 1863config EFI_STUB 1864 bool 1865 1866config EFI 1867 bool "UEFI runtime support" 1868 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1869 select UCS2_STRING 1870 select EFI_PARAMS_FROM_FDT 1871 select EFI_STUB 1872 select EFI_GENERIC_STUB 1873 select EFI_RUNTIME_WRAPPERS 1874 help 1875 This option provides support for runtime services provided 1876 by UEFI firmware (such as non-volatile variables, realtime 1877 clock, and platform reset). A UEFI stub is also provided to 1878 allow the kernel to be booted as an EFI application. This 1879 is only useful for kernels that may run on systems that have 1880 UEFI firmware. 1881 1882config DMI 1883 bool "Enable support for SMBIOS (DMI) tables" 1884 depends on EFI 1885 default y 1886 help 1887 This enables SMBIOS/DMI feature for systems. 1888 1889 This option is only useful on systems that have UEFI firmware. 1890 However, even with this option, the resultant kernel should 1891 continue to boot on existing non-UEFI platforms. 1892 1893 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1894 i.e., the the practice of identifying the platform via DMI to 1895 decide whether certain workarounds for buggy hardware and/or 1896 firmware need to be enabled. This would require the DMI subsystem 1897 to be enabled much earlier than we do on ARM, which is non-trivial. 1898 1899endmenu 1900 1901menu "CPU Power Management" 1902 1903source "drivers/cpufreq/Kconfig" 1904 1905source "drivers/cpuidle/Kconfig" 1906 1907endmenu 1908 1909menu "Floating point emulation" 1910 1911comment "At least one emulation must be selected" 1912 1913config FPE_NWFPE 1914 bool "NWFPE math emulation" 1915 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1916 help 1917 Say Y to include the NWFPE floating point emulator in the kernel. 1918 This is necessary to run most binaries. Linux does not currently 1919 support floating point hardware so you need to say Y here even if 1920 your machine has an FPA or floating point co-processor podule. 1921 1922 You may say N here if you are going to load the Acorn FPEmulator 1923 early in the bootup. 1924 1925config FPE_NWFPE_XP 1926 bool "Support extended precision" 1927 depends on FPE_NWFPE 1928 help 1929 Say Y to include 80-bit support in the kernel floating-point 1930 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1931 Note that gcc does not generate 80-bit operations by default, 1932 so in most cases this option only enlarges the size of the 1933 floating point emulator without any good reason. 1934 1935 You almost surely want to say N here. 1936 1937config FPE_FASTFPE 1938 bool "FastFPE math emulation (EXPERIMENTAL)" 1939 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1940 help 1941 Say Y here to include the FAST floating point emulator in the kernel. 1942 This is an experimental much faster emulator which now also has full 1943 precision for the mantissa. It does not support any exceptions. 1944 It is very simple, and approximately 3-6 times faster than NWFPE. 1945 1946 It should be sufficient for most programs. It may be not suitable 1947 for scientific calculations, but you have to check this for yourself. 1948 If you do not feel you need a faster FP emulation you should better 1949 choose NWFPE. 1950 1951config VFP 1952 bool "VFP-format floating point maths" 1953 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1954 help 1955 Say Y to include VFP support code in the kernel. This is needed 1956 if your hardware includes a VFP unit. 1957 1958 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1959 release notes and additional status information. 1960 1961 Say N if your target does not have VFP hardware. 1962 1963config VFPv3 1964 bool 1965 depends on VFP 1966 default y if CPU_V7 1967 1968config NEON 1969 bool "Advanced SIMD (NEON) Extension support" 1970 depends on VFPv3 && CPU_V7 1971 help 1972 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1973 Extension. 1974 1975config KERNEL_MODE_NEON 1976 bool "Support for NEON in kernel mode" 1977 depends on NEON && AEABI 1978 help 1979 Say Y to include support for NEON in kernel mode. 1980 1981endmenu 1982 1983menu "Power management options" 1984 1985source "kernel/power/Kconfig" 1986 1987config ARCH_SUSPEND_POSSIBLE 1988 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1989 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1990 def_bool y 1991 1992config ARM_CPU_SUSPEND 1993 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1994 depends on ARCH_SUSPEND_POSSIBLE 1995 1996config ARCH_HIBERNATION_POSSIBLE 1997 bool 1998 depends on MMU 1999 default y if ARCH_SUSPEND_POSSIBLE 2000 2001endmenu 2002 2003source "drivers/firmware/Kconfig" 2004 2005if CRYPTO 2006source "arch/arm/crypto/Kconfig" 2007endif 2008 2009source "arch/arm/Kconfig.assembler" 2010