1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_KEEP_MEMBLOCK 30 select ARCH_MIGHT_HAVE_PC_PARPORT 31 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 32 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 33 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 34 select ARCH_SUPPORTS_ATOMIC_RMW 35 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_USE_MEMTEST 39 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 40 select ARCH_WANT_IPC_PARSE_VERSION 41 select ARCH_WANT_LD_ORPHAN_WARN 42 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 43 select BUILDTIME_TABLE_SORT if MMU 44 select CLONE_BACKWARDS 45 select CPU_PM if SUSPEND || CPU_IDLE 46 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 47 select DMA_DECLARE_COHERENT 48 select DMA_GLOBAL_POOL if !MMU 49 select DMA_OPS 50 select DMA_REMAP if MMU 51 select EDAC_SUPPORT 52 select EDAC_ATOMIC_SCRUB 53 select GENERIC_ALLOCATOR 54 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 55 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 56 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 57 select GENERIC_IRQ_IPI if SMP 58 select GENERIC_CPU_AUTOPROBE 59 select GENERIC_EARLY_IOREMAP 60 select GENERIC_IDLE_POLL_SETUP 61 select GENERIC_IRQ_PROBE 62 select GENERIC_IRQ_SHOW 63 select GENERIC_IRQ_SHOW_LEVEL 64 select GENERIC_LIB_DEVMEM_IS_ALLOWED 65 select GENERIC_PCI_IOMAP 66 select GENERIC_SCHED_CLOCK 67 select GENERIC_SMP_IDLE_THREAD 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 87 select HAVE_DMA_CONTIGUOUS if MMU 88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 91 select HAVE_EXIT_THREAD 92 select HAVE_FAST_GUP if ARM_LPAE 93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IRQ_TIME_ACCOUNTING 99 select HAVE_KERNEL_GZIP 100 select HAVE_KERNEL_LZ4 101 select HAVE_KERNEL_LZMA 102 select HAVE_KERNEL_LZO 103 select HAVE_KERNEL_XZ 104 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 105 select HAVE_KRETPROBES if HAVE_KPROBES 106 select HAVE_MOD_ARCH_SPECIFIC 107 select HAVE_NMI 108 select HAVE_OPTPROBES if !THUMB2_KERNEL 109 select HAVE_PERF_EVENTS 110 select HAVE_PERF_REGS 111 select HAVE_PERF_USER_STACK_DUMP 112 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 113 select HAVE_REGS_AND_STACK_ACCESS_API 114 select HAVE_RSEQ 115 select HAVE_STACKPROTECTOR 116 select HAVE_SYSCALL_TRACEPOINTS 117 select HAVE_UID16 118 select HAVE_VIRT_CPU_ACCOUNTING_GEN 119 select IRQ_FORCED_THREADING 120 select MODULES_USE_ELF_REL 121 select NEED_DMA_MAP_STATE 122 select OF_EARLY_FLATTREE if OF 123 select OLD_SIGACTION 124 select OLD_SIGSUSPEND3 125 select PCI_SYSCALL if PCI 126 select PERF_USE_VMALLOC 127 select RTC_LIB 128 select SYS_SUPPORTS_APM_EMULATION 129 select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO 130 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 131 # Above selects are sorted alphabetically; please add new ones 132 # according to that. Thanks. 133 help 134 The ARM series is a line of low-power-consumption RISC chip designs 135 licensed by ARM Ltd and targeted at embedded applications and 136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 137 manufactured, but legacy ARM-based PC hardware remains popular in 138 Europe. There is an ARM Linux project with a web page at 139 <http://www.arm.linux.org.uk/>. 140 141config ARM_HAS_SG_CHAIN 142 bool 143 144config ARM_DMA_USE_IOMMU 145 bool 146 select ARM_HAS_SG_CHAIN 147 select NEED_SG_DMA_LENGTH 148 149if ARM_DMA_USE_IOMMU 150 151config ARM_DMA_IOMMU_ALIGNMENT 152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 153 range 4 9 154 default 8 155 help 156 DMA mapping framework by default aligns all buffers to the smallest 157 PAGE_SIZE order which is greater than or equal to the requested buffer 158 size. This works well for buffers up to a few hundreds kilobytes, but 159 for larger buffers it just a waste of address space. Drivers which has 160 relatively small addressing window (like 64Mib) might run out of 161 virtual space with just a few allocations. 162 163 With this parameter you can specify the maximum PAGE_SIZE order for 164 DMA IOMMU buffers. Larger buffers will be aligned only to this 165 specified order. The order is expressed as a power of two multiplied 166 by the PAGE_SIZE. 167 168endif 169 170config SYS_SUPPORTS_APM_EMULATION 171 bool 172 173config HAVE_TCM 174 bool 175 select GENERIC_ALLOCATOR 176 177config HAVE_PROC_CPU 178 bool 179 180config NO_IOPORT_MAP 181 bool 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config ARCH_HAS_ILOG2_U32 195 bool 196 197config ARCH_HAS_ILOG2_U64 198 bool 199 200config ARCH_HAS_BANDGAP 201 bool 202 203config FIX_EARLYCON_MEM 204 def_bool y if MMU 205 206config GENERIC_HWEIGHT 207 bool 208 default y 209 210config GENERIC_CALIBRATE_DELAY 211 bool 212 default y 213 214config ARCH_MAY_HAVE_PC_FDC 215 bool 216 217config ARCH_SUPPORTS_UPROBES 218 def_bool y 219 220config ARCH_HAS_DMA_SET_COHERENT_MASK 221 bool 222 223config GENERIC_ISA_DMA 224 bool 225 226config FIQ 227 bool 228 229config NEED_RET_TO_USER 230 bool 231 232config ARCH_MTD_XIP 233 bool 234 235config ARM_PATCH_PHYS_VIRT 236 bool "Patch physical to virtual translations at runtime" if EMBEDDED 237 default y 238 depends on !XIP_KERNEL && MMU 239 help 240 Patch phys-to-virt and virt-to-phys translation functions at 241 boot and module load time according to the position of the 242 kernel in system memory. 243 244 This can only be used with non-XIP MMU kernels where the base 245 of physical memory is at a 2 MiB boundary. 246 247 Only disable this option if you know that you do not require 248 this feature (eg, building a kernel for a single machine) and 249 you need to shrink the kernel to the minimal size. 250 251config NEED_MACH_IO_H 252 bool 253 help 254 Select this when mach/io.h is required to provide special 255 definitions for this platform. The need for mach/io.h should 256 be avoided when possible. 257 258config NEED_MACH_MEMORY_H 259 bool 260 help 261 Select this when mach/memory.h is required to provide special 262 definitions for this platform. The need for mach/memory.h should 263 be avoided when possible. 264 265config PHYS_OFFSET 266 hex "Physical address of main memory" if MMU 267 depends on !ARM_PATCH_PHYS_VIRT 268 default DRAM_BASE if !MMU 269 default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX 270 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 271 default 0x30000000 if ARCH_S3C24XX 272 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 273 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 274 default 0 275 help 276 Please provide the physical address corresponding to the 277 location of main memory in your system. 278 279config GENERIC_BUG 280 def_bool y 281 depends on BUG 282 283config PGTABLE_LEVELS 284 int 285 default 3 if ARM_LPAE 286 default 2 287 288menu "System Type" 289 290config MMU 291 bool "MMU-based Paged Memory Management Support" 292 default y 293 help 294 Select if you want MMU-based virtualised addressing space 295 support by paged memory management. If unsure, say 'Y'. 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 8 299 300config ARCH_MMAP_RND_BITS_MAX 301 default 14 if PAGE_OFFSET=0x40000000 302 default 15 if PAGE_OFFSET=0x80000000 303 default 16 304 305# 306# The "ARM system type" choice list is ordered alphabetically by option 307# text. Please add new entries in the option alphabetic order. 308# 309choice 310 prompt "ARM system type" 311 default ARM_SINGLE_ARMV7M if !MMU 312 default ARCH_MULTIPLATFORM if MMU 313 314config ARCH_MULTIPLATFORM 315 bool "Allow multiple platforms to be selected" 316 depends on MMU 317 select ARCH_FLATMEM_ENABLE 318 select ARCH_SPARSEMEM_ENABLE 319 select ARCH_SELECT_MEMORY_MODEL 320 select ARM_HAS_SG_CHAIN 321 select ARM_PATCH_PHYS_VIRT 322 select AUTO_ZRELADDR 323 select TIMER_OF 324 select COMMON_CLK 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select NO_IOPORT_MAP 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARCH_EP93XX 344 bool "EP93xx-based" 345 select ARCH_SPARSEMEM_ENABLE 346 select ARM_AMBA 347 imply ARM_PATCH_PHYS_VIRT 348 select ARM_VIC 349 select GENERIC_IRQ_MULTI_HANDLER 350 select AUTO_ZRELADDR 351 select CLKSRC_MMIO 352 select CPU_ARM920T 353 select GPIOLIB 354 select COMMON_CLK 355 help 356 This enables support for the Cirrus EP93xx series of CPUs. 357 358config ARCH_FOOTBRIDGE 359 bool "FootBridge" 360 select CPU_SA110 361 select FOOTBRIDGE 362 select NEED_MACH_IO_H if !MMU 363 select NEED_MACH_MEMORY_H 364 help 365 Support for systems based on the DC21285 companion chip 366 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 367 368config ARCH_IOP32X 369 bool "IOP32x-based" 370 depends on MMU 371 select CPU_XSCALE 372 select GPIO_IOP 373 select GPIOLIB 374 select NEED_RET_TO_USER 375 select FORCE_PCI 376 select PLAT_IOP 377 help 378 Support for Intel's 80219 and IOP32X (XScale) family of 379 processors. 380 381config ARCH_IXP4XX 382 bool "IXP4xx-based" 383 depends on MMU 384 select ARCH_HAS_DMA_SET_COHERENT_MASK 385 select ARCH_SUPPORTS_BIG_ENDIAN 386 select CPU_XSCALE 387 select DMABOUNCE if PCI 388 select GENERIC_IRQ_MULTI_HANDLER 389 select GPIO_IXP4XX 390 select GPIOLIB 391 select HAVE_PCI 392 select IXP4XX_IRQ 393 select IXP4XX_TIMER 394 # With the new PCI driver this is not needed 395 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 396 select USB_EHCI_BIG_ENDIAN_DESC 397 select USB_EHCI_BIG_ENDIAN_MMIO 398 help 399 Support for Intel's IXP4XX (XScale) family of processors. 400 401config ARCH_DOVE 402 bool "Marvell Dove" 403 select CPU_PJ4 404 select GENERIC_IRQ_MULTI_HANDLER 405 select GPIOLIB 406 select HAVE_PCI 407 select MVEBU_MBUS 408 select PINCTRL 409 select PINCTRL_DOVE 410 select PLAT_ORION_LEGACY 411 select SPARSE_IRQ 412 select PM_GENERIC_DOMAINS if PM 413 help 414 Support for the Marvell Dove SoC 88AP510 415 416config ARCH_PXA 417 bool "PXA2xx/PXA3xx-based" 418 depends on MMU 419 select ARCH_MTD_XIP 420 select ARM_CPU_SUSPEND if PM 421 select AUTO_ZRELADDR 422 select COMMON_CLK 423 select CLKSRC_PXA 424 select CLKSRC_MMIO 425 select TIMER_OF 426 select CPU_XSCALE if !CPU_XSC3 427 select GENERIC_IRQ_MULTI_HANDLER 428 select GPIO_PXA 429 select GPIOLIB 430 select IRQ_DOMAIN 431 select PLAT_PXA 432 select SPARSE_IRQ 433 help 434 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 435 436config ARCH_RPC 437 bool "RiscPC" 438 depends on MMU 439 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 440 select ARCH_ACORN 441 select ARCH_MAY_HAVE_PC_FDC 442 select ARCH_SPARSEMEM_ENABLE 443 select ARM_HAS_SG_CHAIN 444 select CPU_SA110 445 select FIQ 446 select HAVE_PATA_PLATFORM 447 select ISA_DMA_API 448 select LEGACY_TIMER_TICK 449 select NEED_MACH_IO_H 450 select NEED_MACH_MEMORY_H 451 select NO_IOPORT_MAP 452 help 453 On the Acorn Risc-PC, Linux can support the internal IDE disk and 454 CD-ROM interface, serial and parallel port, and the floppy drive. 455 456config ARCH_SA1100 457 bool "SA1100-based" 458 select ARCH_MTD_XIP 459 select ARCH_SPARSEMEM_ENABLE 460 select CLKSRC_MMIO 461 select CLKSRC_PXA 462 select TIMER_OF if OF 463 select COMMON_CLK 464 select CPU_FREQ 465 select CPU_SA1100 466 select GENERIC_IRQ_MULTI_HANDLER 467 select GPIOLIB 468 select IRQ_DOMAIN 469 select ISA 470 select NEED_MACH_MEMORY_H 471 select SPARSE_IRQ 472 help 473 Support for StrongARM 11x0 based boards. 474 475config ARCH_S3C24XX 476 bool "Samsung S3C24XX SoCs" 477 select ATAGS 478 select CLKSRC_SAMSUNG_PWM 479 select GPIO_SAMSUNG 480 select GPIOLIB 481 select GENERIC_IRQ_MULTI_HANDLER 482 select NEED_MACH_IO_H 483 select S3C2410_WATCHDOG 484 select SAMSUNG_ATAGS 485 select USE_OF 486 select WATCHDOG 487 help 488 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 489 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 490 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 491 Samsung SMDK2410 development board (and derivatives). 492 493config ARCH_OMAP1 494 bool "TI OMAP1" 495 depends on MMU 496 select ARCH_OMAP 497 select CLKSRC_MMIO 498 select GENERIC_IRQ_CHIP 499 select GENERIC_IRQ_MULTI_HANDLER 500 select GPIOLIB 501 select HAVE_LEGACY_CLK 502 select IRQ_DOMAIN 503 select NEED_MACH_IO_H if PCCARD 504 select NEED_MACH_MEMORY_H 505 select SPARSE_IRQ 506 help 507 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 508 509endchoice 510 511menu "Multiple platform selection" 512 depends on ARCH_MULTIPLATFORM 513 514comment "CPU Core family selection" 515 516config ARCH_MULTI_V4 517 bool "ARMv4 based platforms (FA526)" 518 depends on !ARCH_MULTI_V6_V7 519 select ARCH_MULTI_V4_V5 520 select CPU_FA526 521 522config ARCH_MULTI_V4T 523 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 524 depends on !ARCH_MULTI_V6_V7 525 select ARCH_MULTI_V4_V5 526 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 527 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 528 CPU_ARM925T || CPU_ARM940T) 529 530config ARCH_MULTI_V5 531 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 532 depends on !ARCH_MULTI_V6_V7 533 select ARCH_MULTI_V4_V5 534 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 535 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 536 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 537 538config ARCH_MULTI_V4_V5 539 bool 540 541config ARCH_MULTI_V6 542 bool "ARMv6 based platforms (ARM11)" 543 select ARCH_MULTI_V6_V7 544 select CPU_V6K 545 546config ARCH_MULTI_V7 547 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 548 default y 549 select ARCH_MULTI_V6_V7 550 select CPU_V7 551 select HAVE_SMP 552 553config ARCH_MULTI_V6_V7 554 bool 555 select MIGHT_HAVE_CACHE_L2X0 556 557config ARCH_MULTI_CPU_AUTO 558 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 559 select ARCH_MULTI_V5 560 561endmenu 562 563config ARCH_VIRT 564 bool "Dummy Virtual Machine" 565 depends on ARCH_MULTI_V7 566 select ARM_AMBA 567 select ARM_GIC 568 select ARM_GIC_V2M if PCI 569 select ARM_GIC_V3 570 select ARM_GIC_V3_ITS if PCI 571 select ARM_PSCI 572 select HAVE_ARM_ARCH_TIMER 573 select ARCH_SUPPORTS_BIG_ENDIAN 574 575config ARCH_AIROHA 576 bool "Airoha SoC Support" 577 depends on ARCH_MULTI_V7 578 select ARM_AMBA 579 select ARM_GIC 580 select ARM_GIC_V3 581 select ARM_PSCI 582 select HAVE_ARM_ARCH_TIMER 583 select COMMON_CLK 584 help 585 Support for Airoha EN7523 SoCs 586 587# 588# This is sorted alphabetically by mach-* pathname. However, plat-* 589# Kconfigs may be included either alphabetically (according to the 590# plat- suffix) or along side the corresponding mach-* source. 591# 592source "arch/arm/mach-actions/Kconfig" 593 594source "arch/arm/mach-alpine/Kconfig" 595 596source "arch/arm/mach-artpec/Kconfig" 597 598source "arch/arm/mach-asm9260/Kconfig" 599 600source "arch/arm/mach-aspeed/Kconfig" 601 602source "arch/arm/mach-at91/Kconfig" 603 604source "arch/arm/mach-axxia/Kconfig" 605 606source "arch/arm/mach-bcm/Kconfig" 607 608source "arch/arm/mach-berlin/Kconfig" 609 610source "arch/arm/mach-clps711x/Kconfig" 611 612source "arch/arm/mach-cns3xxx/Kconfig" 613 614source "arch/arm/mach-davinci/Kconfig" 615 616source "arch/arm/mach-digicolor/Kconfig" 617 618source "arch/arm/mach-dove/Kconfig" 619 620source "arch/arm/mach-ep93xx/Kconfig" 621 622source "arch/arm/mach-exynos/Kconfig" 623 624source "arch/arm/mach-footbridge/Kconfig" 625 626source "arch/arm/mach-gemini/Kconfig" 627 628source "arch/arm/mach-highbank/Kconfig" 629 630source "arch/arm/mach-hisi/Kconfig" 631 632source "arch/arm/mach-imx/Kconfig" 633 634source "arch/arm/mach-integrator/Kconfig" 635 636source "arch/arm/mach-iop32x/Kconfig" 637 638source "arch/arm/mach-ixp4xx/Kconfig" 639 640source "arch/arm/mach-keystone/Kconfig" 641 642source "arch/arm/mach-lpc32xx/Kconfig" 643 644source "arch/arm/mach-mediatek/Kconfig" 645 646source "arch/arm/mach-meson/Kconfig" 647 648source "arch/arm/mach-milbeaut/Kconfig" 649 650source "arch/arm/mach-mmp/Kconfig" 651 652source "arch/arm/mach-moxart/Kconfig" 653 654source "arch/arm/mach-mstar/Kconfig" 655 656source "arch/arm/mach-mv78xx0/Kconfig" 657 658source "arch/arm/mach-mvebu/Kconfig" 659 660source "arch/arm/mach-mxs/Kconfig" 661 662source "arch/arm/mach-nomadik/Kconfig" 663 664source "arch/arm/mach-npcm/Kconfig" 665 666source "arch/arm/mach-nspire/Kconfig" 667 668source "arch/arm/plat-omap/Kconfig" 669 670source "arch/arm/mach-omap1/Kconfig" 671 672source "arch/arm/mach-omap2/Kconfig" 673 674source "arch/arm/mach-orion5x/Kconfig" 675 676source "arch/arm/mach-oxnas/Kconfig" 677 678source "arch/arm/mach-pxa/Kconfig" 679source "arch/arm/plat-pxa/Kconfig" 680 681source "arch/arm/mach-qcom/Kconfig" 682 683source "arch/arm/mach-rda/Kconfig" 684 685source "arch/arm/mach-realtek/Kconfig" 686 687source "arch/arm/mach-realview/Kconfig" 688 689source "arch/arm/mach-rockchip/Kconfig" 690 691source "arch/arm/mach-s3c/Kconfig" 692 693source "arch/arm/mach-s5pv210/Kconfig" 694 695source "arch/arm/mach-sa1100/Kconfig" 696 697source "arch/arm/mach-shmobile/Kconfig" 698 699source "arch/arm/mach-socfpga/Kconfig" 700 701source "arch/arm/mach-spear/Kconfig" 702 703source "arch/arm/mach-sti/Kconfig" 704 705source "arch/arm/mach-stm32/Kconfig" 706 707source "arch/arm/mach-sunxi/Kconfig" 708 709source "arch/arm/mach-tegra/Kconfig" 710 711source "arch/arm/mach-uniphier/Kconfig" 712 713source "arch/arm/mach-ux500/Kconfig" 714 715source "arch/arm/mach-versatile/Kconfig" 716 717source "arch/arm/mach-vexpress/Kconfig" 718 719source "arch/arm/mach-vt8500/Kconfig" 720 721source "arch/arm/mach-zynq/Kconfig" 722 723# ARMv7-M architecture 724config ARCH_LPC18XX 725 bool "NXP LPC18xx/LPC43xx" 726 depends on ARM_SINGLE_ARMV7M 727 select ARCH_HAS_RESET_CONTROLLER 728 select ARM_AMBA 729 select CLKSRC_LPC32XX 730 select PINCTRL 731 help 732 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 733 high performance microcontrollers. 734 735config ARCH_MPS2 736 bool "ARM MPS2 platform" 737 depends on ARM_SINGLE_ARMV7M 738 select ARM_AMBA 739 select CLKSRC_MPS2 740 help 741 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 742 with a range of available cores like Cortex-M3/M4/M7. 743 744 Please, note that depends which Application Note is used memory map 745 for the platform may vary, so adjustment of RAM base might be needed. 746 747# Definitions to make life easier 748config ARCH_ACORN 749 bool 750 751config PLAT_IOP 752 bool 753 754config PLAT_ORION 755 bool 756 select CLKSRC_MMIO 757 select COMMON_CLK 758 select GENERIC_IRQ_CHIP 759 select IRQ_DOMAIN 760 761config PLAT_ORION_LEGACY 762 bool 763 select PLAT_ORION 764 765config PLAT_PXA 766 bool 767 768config PLAT_VERSATILE 769 bool 770 771source "arch/arm/mm/Kconfig" 772 773config IWMMXT 774 bool "Enable iWMMXt support" 775 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 776 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 777 help 778 Enable support for iWMMXt context switching at run time if 779 running on a CPU that supports it. 780 781if !MMU 782source "arch/arm/Kconfig-nommu" 783endif 784 785config PJ4B_ERRATA_4742 786 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 787 depends on CPU_PJ4B && MACH_ARMADA_370 788 default y 789 help 790 When coming out of either a Wait for Interrupt (WFI) or a Wait for 791 Event (WFE) IDLE states, a specific timing sensitivity exists between 792 the retiring WFI/WFE instructions and the newly issued subsequent 793 instructions. This sensitivity can result in a CPU hang scenario. 794 Workaround: 795 The software must insert either a Data Synchronization Barrier (DSB) 796 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 797 instruction 798 799config ARM_ERRATA_326103 800 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 801 depends on CPU_V6 802 help 803 Executing a SWP instruction to read-only memory does not set bit 11 804 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 805 treat the access as a read, preventing a COW from occurring and 806 causing the faulting task to livelock. 807 808config ARM_ERRATA_411920 809 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 810 depends on CPU_V6 || CPU_V6K 811 help 812 Invalidation of the Instruction Cache operation can 813 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 814 It does not affect the MPCore. This option enables the ARM Ltd. 815 recommended workaround. 816 817config ARM_ERRATA_430973 818 bool "ARM errata: Stale prediction on replaced interworking branch" 819 depends on CPU_V7 820 help 821 This option enables the workaround for the 430973 Cortex-A8 822 r1p* erratum. If a code sequence containing an ARM/Thumb 823 interworking branch is replaced with another code sequence at the 824 same virtual address, whether due to self-modifying code or virtual 825 to physical address re-mapping, Cortex-A8 does not recover from the 826 stale interworking branch prediction. This results in Cortex-A8 827 executing the new code sequence in the incorrect ARM or Thumb state. 828 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 829 and also flushes the branch target cache at every context switch. 830 Note that setting specific bits in the ACTLR register may not be 831 available in non-secure mode. 832 833config ARM_ERRATA_458693 834 bool "ARM errata: Processor deadlock when a false hazard is created" 835 depends on CPU_V7 836 depends on !ARCH_MULTIPLATFORM 837 help 838 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 839 erratum. For very specific sequences of memory operations, it is 840 possible for a hazard condition intended for a cache line to instead 841 be incorrectly associated with a different cache line. This false 842 hazard might then cause a processor deadlock. The workaround enables 843 the L1 caching of the NEON accesses and disables the PLD instruction 844 in the ACTLR register. Note that setting specific bits in the ACTLR 845 register may not be available in non-secure mode. 846 847config ARM_ERRATA_460075 848 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 849 depends on CPU_V7 850 depends on !ARCH_MULTIPLATFORM 851 help 852 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 853 erratum. Any asynchronous access to the L2 cache may encounter a 854 situation in which recent store transactions to the L2 cache are lost 855 and overwritten with stale memory contents from external memory. The 856 workaround disables the write-allocate mode for the L2 cache via the 857 ACTLR register. Note that setting specific bits in the ACTLR register 858 may not be available in non-secure mode. 859 860config ARM_ERRATA_742230 861 bool "ARM errata: DMB operation may be faulty" 862 depends on CPU_V7 && SMP 863 depends on !ARCH_MULTIPLATFORM 864 help 865 This option enables the workaround for the 742230 Cortex-A9 866 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 867 between two write operations may not ensure the correct visibility 868 ordering of the two writes. This workaround sets a specific bit in 869 the diagnostic register of the Cortex-A9 which causes the DMB 870 instruction to behave as a DSB, ensuring the correct behaviour of 871 the two writes. 872 873config ARM_ERRATA_742231 874 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 875 depends on CPU_V7 && SMP 876 depends on !ARCH_MULTIPLATFORM 877 help 878 This option enables the workaround for the 742231 Cortex-A9 879 (r2p0..r2p2) erratum. Under certain conditions, specific to the 880 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 881 accessing some data located in the same cache line, may get corrupted 882 data due to bad handling of the address hazard when the line gets 883 replaced from one of the CPUs at the same time as another CPU is 884 accessing it. This workaround sets specific bits in the diagnostic 885 register of the Cortex-A9 which reduces the linefill issuing 886 capabilities of the processor. 887 888config ARM_ERRATA_643719 889 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 890 depends on CPU_V7 && SMP 891 default y 892 help 893 This option enables the workaround for the 643719 Cortex-A9 (prior to 894 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 895 register returns zero when it should return one. The workaround 896 corrects this value, ensuring cache maintenance operations which use 897 it behave as intended and avoiding data corruption. 898 899config ARM_ERRATA_720789 900 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 901 depends on CPU_V7 902 help 903 This option enables the workaround for the 720789 Cortex-A9 (prior to 904 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 905 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 906 As a consequence of this erratum, some TLB entries which should be 907 invalidated are not, resulting in an incoherency in the system page 908 tables. The workaround changes the TLB flushing routines to invalidate 909 entries regardless of the ASID. 910 911config ARM_ERRATA_743622 912 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 913 depends on CPU_V7 914 depends on !ARCH_MULTIPLATFORM 915 help 916 This option enables the workaround for the 743622 Cortex-A9 917 (r2p*) erratum. Under very rare conditions, a faulty 918 optimisation in the Cortex-A9 Store Buffer may lead to data 919 corruption. This workaround sets a specific bit in the diagnostic 920 register of the Cortex-A9 which disables the Store Buffer 921 optimisation, preventing the defect from occurring. This has no 922 visible impact on the overall performance or power consumption of the 923 processor. 924 925config ARM_ERRATA_751472 926 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 927 depends on CPU_V7 928 depends on !ARCH_MULTIPLATFORM 929 help 930 This option enables the workaround for the 751472 Cortex-A9 (prior 931 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 932 completion of a following broadcasted operation if the second 933 operation is received by a CPU before the ICIALLUIS has completed, 934 potentially leading to corrupted entries in the cache or TLB. 935 936config ARM_ERRATA_754322 937 bool "ARM errata: possible faulty MMU translations following an ASID switch" 938 depends on CPU_V7 939 help 940 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 941 r3p*) erratum. A speculative memory access may cause a page table walk 942 which starts prior to an ASID switch but completes afterwards. This 943 can populate the micro-TLB with a stale entry which may be hit with 944 the new ASID. This workaround places two dsb instructions in the mm 945 switching code so that no page table walks can cross the ASID switch. 946 947config ARM_ERRATA_754327 948 bool "ARM errata: no automatic Store Buffer drain" 949 depends on CPU_V7 && SMP 950 help 951 This option enables the workaround for the 754327 Cortex-A9 (prior to 952 r2p0) erratum. The Store Buffer does not have any automatic draining 953 mechanism and therefore a livelock may occur if an external agent 954 continuously polls a memory location waiting to observe an update. 955 This workaround defines cpu_relax() as smp_mb(), preventing correctly 956 written polling loops from denying visibility of updates to memory. 957 958config ARM_ERRATA_364296 959 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 960 depends on CPU_V6 961 help 962 This options enables the workaround for the 364296 ARM1136 963 r0p2 erratum (possible cache data corruption with 964 hit-under-miss enabled). It sets the undocumented bit 31 in 965 the auxiliary control register and the FI bit in the control 966 register, thus disabling hit-under-miss without putting the 967 processor into full low interrupt latency mode. ARM11MPCore 968 is not affected. 969 970config ARM_ERRATA_764369 971 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 972 depends on CPU_V7 && SMP 973 help 974 This option enables the workaround for erratum 764369 975 affecting Cortex-A9 MPCore with two or more processors (all 976 current revisions). Under certain timing circumstances, a data 977 cache line maintenance operation by MVA targeting an Inner 978 Shareable memory region may fail to proceed up to either the 979 Point of Coherency or to the Point of Unification of the 980 system. This workaround adds a DSB instruction before the 981 relevant cache maintenance functions and sets a specific bit 982 in the diagnostic control register of the SCU. 983 984config ARM_ERRATA_775420 985 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 986 depends on CPU_V7 987 help 988 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 989 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 990 operation aborts with MMU exception, it might cause the processor 991 to deadlock. This workaround puts DSB before executing ISB if 992 an abort may occur on cache maintenance. 993 994config ARM_ERRATA_798181 995 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 996 depends on CPU_V7 && SMP 997 help 998 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 999 adequately shooting down all use of the old entries. This 1000 option enables the Linux kernel workaround for this erratum 1001 which sends an IPI to the CPUs that are running the same ASID 1002 as the one being invalidated. 1003 1004config ARM_ERRATA_773022 1005 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1006 depends on CPU_V7 1007 help 1008 This option enables the workaround for the 773022 Cortex-A15 1009 (up to r0p4) erratum. In certain rare sequences of code, the 1010 loop buffer may deliver incorrect instructions. This 1011 workaround disables the loop buffer to avoid the erratum. 1012 1013config ARM_ERRATA_818325_852422 1014 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1015 depends on CPU_V7 1016 help 1017 This option enables the workaround for: 1018 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1019 instruction might deadlock. Fixed in r0p1. 1020 - Cortex-A12 852422: Execution of a sequence of instructions might 1021 lead to either a data corruption or a CPU deadlock. Not fixed in 1022 any Cortex-A12 cores yet. 1023 This workaround for all both errata involves setting bit[12] of the 1024 Feature Register. This bit disables an optimisation applied to a 1025 sequence of 2 instructions that use opposing condition codes. 1026 1027config ARM_ERRATA_821420 1028 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1029 depends on CPU_V7 1030 help 1031 This option enables the workaround for the 821420 Cortex-A12 1032 (all revs) erratum. In very rare timing conditions, a sequence 1033 of VMOV to Core registers instructions, for which the second 1034 one is in the shadow of a branch or abort, can lead to a 1035 deadlock when the VMOV instructions are issued out-of-order. 1036 1037config ARM_ERRATA_825619 1038 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1039 depends on CPU_V7 1040 help 1041 This option enables the workaround for the 825619 Cortex-A12 1042 (all revs) erratum. Within rare timing constraints, executing a 1043 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1044 and Device/Strongly-Ordered loads and stores might cause deadlock 1045 1046config ARM_ERRATA_857271 1047 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1048 depends on CPU_V7 1049 help 1050 This option enables the workaround for the 857271 Cortex-A12 1051 (all revs) erratum. Under very rare timing conditions, the CPU might 1052 hang. The workaround is expected to have a < 1% performance impact. 1053 1054config ARM_ERRATA_852421 1055 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1056 depends on CPU_V7 1057 help 1058 This option enables the workaround for the 852421 Cortex-A17 1059 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1060 execution of a DMB ST instruction might fail to properly order 1061 stores from GroupA and stores from GroupB. 1062 1063config ARM_ERRATA_852423 1064 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1065 depends on CPU_V7 1066 help 1067 This option enables the workaround for: 1068 - Cortex-A17 852423: Execution of a sequence of instructions might 1069 lead to either a data corruption or a CPU deadlock. Not fixed in 1070 any Cortex-A17 cores yet. 1071 This is identical to Cortex-A12 erratum 852422. It is a separate 1072 config option from the A12 erratum due to the way errata are checked 1073 for and handled. 1074 1075config ARM_ERRATA_857272 1076 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for the 857272 Cortex-A17 erratum. 1080 This erratum is not known to be fixed in any A17 revision. 1081 This is identical to Cortex-A12 erratum 857271. It is a separate 1082 config option from the A12 erratum due to the way errata are checked 1083 for and handled. 1084 1085endmenu 1086 1087source "arch/arm/common/Kconfig" 1088 1089menu "Bus support" 1090 1091config ISA 1092 bool 1093 help 1094 Find out whether you have ISA slots on your motherboard. ISA is the 1095 name of a bus system, i.e. the way the CPU talks to the other stuff 1096 inside your box. Other bus systems are PCI, EISA, MicroChannel 1097 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1098 newer boards don't support it. If you have ISA, say Y, otherwise N. 1099 1100# Select ISA DMA controller support 1101config ISA_DMA 1102 bool 1103 select ISA_DMA_API 1104 1105# Select ISA DMA interface 1106config ISA_DMA_API 1107 bool 1108 1109config PCI_NANOENGINE 1110 bool "BSE nanoEngine PCI support" 1111 depends on SA1100_NANOENGINE 1112 help 1113 Enable PCI on the BSE nanoEngine board. 1114 1115config ARM_ERRATA_814220 1116 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1117 depends on CPU_V7 1118 help 1119 The v7 ARM states that all cache and branch predictor maintenance 1120 operations that do not specify an address execute, relative to 1121 each other, in program order. 1122 However, because of this erratum, an L2 set/way cache maintenance 1123 operation can overtake an L1 set/way cache maintenance operation. 1124 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1125 r0p4, r0p5. 1126 1127endmenu 1128 1129menu "Kernel Features" 1130 1131config HAVE_SMP 1132 bool 1133 help 1134 This option should be selected by machines which have an SMP- 1135 capable CPU. 1136 1137 The only effect of this option is to make the SMP-related 1138 options available to the user for configuration. 1139 1140config SMP 1141 bool "Symmetric Multi-Processing" 1142 depends on CPU_V6K || CPU_V7 1143 depends on HAVE_SMP 1144 depends on MMU || ARM_MPU 1145 select IRQ_WORK 1146 help 1147 This enables support for systems with more than one CPU. If you have 1148 a system with only one CPU, say N. If you have a system with more 1149 than one CPU, say Y. 1150 1151 If you say N here, the kernel will run on uni- and multiprocessor 1152 machines, but will use only one CPU of a multiprocessor machine. If 1153 you say Y here, the kernel will run on many, but not all, 1154 uniprocessor machines. On a uniprocessor machine, the kernel 1155 will run faster if you say N here. 1156 1157 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1158 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1159 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1160 1161 If you don't know what to do here, say N. 1162 1163config SMP_ON_UP 1164 bool "Allow booting SMP kernel on uniprocessor systems" 1165 depends on SMP && !XIP_KERNEL && MMU 1166 default y 1167 help 1168 SMP kernels contain instructions which fail on non-SMP processors. 1169 Enabling this option allows the kernel to modify itself to make 1170 these instructions safe. Disabling it allows about 1K of space 1171 savings. 1172 1173 If you don't know what to do here, say Y. 1174 1175 1176config CURRENT_POINTER_IN_TPIDRURO 1177 def_bool y 1178 depends on SMP && CPU_32v6K && !CPU_V6 1179 1180config ARM_CPU_TOPOLOGY 1181 bool "Support cpu topology definition" 1182 depends on SMP && CPU_V7 1183 default y 1184 help 1185 Support ARM cpu topology definition. The MPIDR register defines 1186 affinity between processors which is then used to describe the cpu 1187 topology of an ARM System. 1188 1189config SCHED_MC 1190 bool "Multi-core scheduler support" 1191 depends on ARM_CPU_TOPOLOGY 1192 help 1193 Multi-core scheduler support improves the CPU scheduler's decision 1194 making when dealing with multi-core CPU chips at a cost of slightly 1195 increased overhead in some places. If unsure say N here. 1196 1197config SCHED_SMT 1198 bool "SMT scheduler support" 1199 depends on ARM_CPU_TOPOLOGY 1200 help 1201 Improves the CPU scheduler's decision making when dealing with 1202 MultiThreading at a cost of slightly increased overhead in some 1203 places. If unsure say N here. 1204 1205config HAVE_ARM_SCU 1206 bool 1207 help 1208 This option enables support for the ARM snoop control unit 1209 1210config HAVE_ARM_ARCH_TIMER 1211 bool "Architected timer support" 1212 depends on CPU_V7 1213 select ARM_ARCH_TIMER 1214 help 1215 This option enables support for the ARM architected timer 1216 1217config HAVE_ARM_TWD 1218 bool 1219 help 1220 This options enables support for the ARM timer and watchdog unit 1221 1222config MCPM 1223 bool "Multi-Cluster Power Management" 1224 depends on CPU_V7 && SMP 1225 help 1226 This option provides the common power management infrastructure 1227 for (multi-)cluster based systems, such as big.LITTLE based 1228 systems. 1229 1230config MCPM_QUAD_CLUSTER 1231 bool 1232 depends on MCPM 1233 help 1234 To avoid wasting resources unnecessarily, MCPM only supports up 1235 to 2 clusters by default. 1236 Platforms with 3 or 4 clusters that use MCPM must select this 1237 option to allow the additional clusters to be managed. 1238 1239config BIG_LITTLE 1240 bool "big.LITTLE support (Experimental)" 1241 depends on CPU_V7 && SMP 1242 select MCPM 1243 help 1244 This option enables support selections for the big.LITTLE 1245 system architecture. 1246 1247config BL_SWITCHER 1248 bool "big.LITTLE switcher support" 1249 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1250 select CPU_PM 1251 help 1252 The big.LITTLE "switcher" provides the core functionality to 1253 transparently handle transition between a cluster of A15's 1254 and a cluster of A7's in a big.LITTLE system. 1255 1256config BL_SWITCHER_DUMMY_IF 1257 tristate "Simple big.LITTLE switcher user interface" 1258 depends on BL_SWITCHER && DEBUG_KERNEL 1259 help 1260 This is a simple and dummy char dev interface to control 1261 the big.LITTLE switcher core code. It is meant for 1262 debugging purposes only. 1263 1264choice 1265 prompt "Memory split" 1266 depends on MMU 1267 default VMSPLIT_3G 1268 help 1269 Select the desired split between kernel and user memory. 1270 1271 If you are not absolutely sure what you are doing, leave this 1272 option alone! 1273 1274 config VMSPLIT_3G 1275 bool "3G/1G user/kernel split" 1276 config VMSPLIT_3G_OPT 1277 depends on !ARM_LPAE 1278 bool "3G/1G user/kernel split (for full 1G low memory)" 1279 config VMSPLIT_2G 1280 bool "2G/2G user/kernel split" 1281 config VMSPLIT_1G 1282 bool "1G/3G user/kernel split" 1283endchoice 1284 1285config PAGE_OFFSET 1286 hex 1287 default PHYS_OFFSET if !MMU 1288 default 0x40000000 if VMSPLIT_1G 1289 default 0x80000000 if VMSPLIT_2G 1290 default 0xB0000000 if VMSPLIT_3G_OPT 1291 default 0xC0000000 1292 1293config KASAN_SHADOW_OFFSET 1294 hex 1295 depends on KASAN 1296 default 0x1f000000 if PAGE_OFFSET=0x40000000 1297 default 0x5f000000 if PAGE_OFFSET=0x80000000 1298 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1299 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1300 default 0xffffffff 1301 1302config NR_CPUS 1303 int "Maximum number of CPUs (2-32)" 1304 range 2 16 if DEBUG_KMAP_LOCAL 1305 range 2 32 if !DEBUG_KMAP_LOCAL 1306 depends on SMP 1307 default "4" 1308 help 1309 The maximum number of CPUs that the kernel can support. 1310 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1311 debugging is enabled, which uses half of the per-CPU fixmap 1312 slots as guard regions. 1313 1314config HOTPLUG_CPU 1315 bool "Support for hot-pluggable CPUs" 1316 depends on SMP 1317 select GENERIC_IRQ_MIGRATION 1318 help 1319 Say Y here to experiment with turning CPUs off and on. CPUs 1320 can be controlled through /sys/devices/system/cpu. 1321 1322config ARM_PSCI 1323 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1324 depends on HAVE_ARM_SMCCC 1325 select ARM_PSCI_FW 1326 help 1327 Say Y here if you want Linux to communicate with system firmware 1328 implementing the PSCI specification for CPU-centric power 1329 management operations described in ARM document number ARM DEN 1330 0022A ("Power State Coordination Interface System Software on 1331 ARM processors"). 1332 1333# The GPIO number here must be sorted by descending number. In case of 1334# a multiplatform kernel, we just want the highest value required by the 1335# selected platforms. 1336config ARCH_NR_GPIO 1337 int 1338 default 2048 if ARCH_INTEL_SOCFPGA 1339 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1340 ARCH_ZYNQ || ARCH_ASPEED 1341 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1342 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1343 default 416 if ARCH_SUNXI 1344 default 392 if ARCH_U8500 1345 default 352 if ARCH_VT8500 1346 default 288 if ARCH_ROCKCHIP 1347 default 264 if MACH_H4700 1348 default 0 1349 help 1350 Maximum number of GPIOs in the system. 1351 1352 If unsure, leave the default value. 1353 1354config HZ_FIXED 1355 int 1356 default 128 if SOC_AT91RM9200 1357 default 0 1358 1359choice 1360 depends on HZ_FIXED = 0 1361 prompt "Timer frequency" 1362 1363config HZ_100 1364 bool "100 Hz" 1365 1366config HZ_200 1367 bool "200 Hz" 1368 1369config HZ_250 1370 bool "250 Hz" 1371 1372config HZ_300 1373 bool "300 Hz" 1374 1375config HZ_500 1376 bool "500 Hz" 1377 1378config HZ_1000 1379 bool "1000 Hz" 1380 1381endchoice 1382 1383config HZ 1384 int 1385 default HZ_FIXED if HZ_FIXED != 0 1386 default 100 if HZ_100 1387 default 200 if HZ_200 1388 default 250 if HZ_250 1389 default 300 if HZ_300 1390 default 500 if HZ_500 1391 default 1000 1392 1393config SCHED_HRTICK 1394 def_bool HIGH_RES_TIMERS 1395 1396config THUMB2_KERNEL 1397 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1398 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1399 default y if CPU_THUMBONLY 1400 select ARM_UNWIND 1401 help 1402 By enabling this option, the kernel will be compiled in 1403 Thumb-2 mode. 1404 1405 If unsure, say N. 1406 1407config ARM_PATCH_IDIV 1408 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1409 depends on CPU_32v7 && !XIP_KERNEL 1410 default y 1411 help 1412 The ARM compiler inserts calls to __aeabi_idiv() and 1413 __aeabi_uidiv() when it needs to perform division on signed 1414 and unsigned integers. Some v7 CPUs have support for the sdiv 1415 and udiv instructions that can be used to implement those 1416 functions. 1417 1418 Enabling this option allows the kernel to modify itself to 1419 replace the first two instructions of these library functions 1420 with the sdiv or udiv plus "bx lr" instructions when the CPU 1421 it is running on supports them. Typically this will be faster 1422 and less power intensive than running the original library 1423 code to do integer division. 1424 1425config AEABI 1426 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1427 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1428 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1429 help 1430 This option allows for the kernel to be compiled using the latest 1431 ARM ABI (aka EABI). This is only useful if you are using a user 1432 space environment that is also compiled with EABI. 1433 1434 Since there are major incompatibilities between the legacy ABI and 1435 EABI, especially with regard to structure member alignment, this 1436 option also changes the kernel syscall calling convention to 1437 disambiguate both ABIs and allow for backward compatibility support 1438 (selected with CONFIG_OABI_COMPAT). 1439 1440 To use this you need GCC version 4.0.0 or later. 1441 1442config OABI_COMPAT 1443 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1444 depends on AEABI && !THUMB2_KERNEL 1445 help 1446 This option preserves the old syscall interface along with the 1447 new (ARM EABI) one. It also provides a compatibility layer to 1448 intercept syscalls that have structure arguments which layout 1449 in memory differs between the legacy ABI and the new ARM EABI 1450 (only for non "thumb" binaries). This option adds a tiny 1451 overhead to all syscalls and produces a slightly larger kernel. 1452 1453 The seccomp filter system will not be available when this is 1454 selected, since there is no way yet to sensibly distinguish 1455 between calling conventions during filtering. 1456 1457 If you know you'll be using only pure EABI user space then you 1458 can say N here. If this option is not selected and you attempt 1459 to execute a legacy ABI binary then the result will be 1460 UNPREDICTABLE (in fact it can be predicted that it won't work 1461 at all). If in doubt say N. 1462 1463config ARCH_SELECT_MEMORY_MODEL 1464 bool 1465 1466config ARCH_FLATMEM_ENABLE 1467 bool 1468 1469config ARCH_SPARSEMEM_ENABLE 1470 bool 1471 select SPARSEMEM_STATIC if SPARSEMEM 1472 1473config HIGHMEM 1474 bool "High Memory Support" 1475 depends on MMU 1476 select KMAP_LOCAL 1477 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1478 help 1479 The address space of ARM processors is only 4 Gigabytes large 1480 and it has to accommodate user address space, kernel address 1481 space as well as some memory mapped IO. That means that, if you 1482 have a large amount of physical memory and/or IO, not all of the 1483 memory can be "permanently mapped" by the kernel. The physical 1484 memory that is not permanently mapped is called "high memory". 1485 1486 Depending on the selected kernel/user memory split, minimum 1487 vmalloc space and actual amount of RAM, you may not need this 1488 option which should result in a slightly faster kernel. 1489 1490 If unsure, say n. 1491 1492config HIGHPTE 1493 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1494 depends on HIGHMEM 1495 default y 1496 help 1497 The VM uses one page of physical memory for each page table. 1498 For systems with a lot of processes, this can use a lot of 1499 precious low memory, eventually leading to low memory being 1500 consumed by page tables. Setting this option will allow 1501 user-space 2nd level page tables to reside in high memory. 1502 1503config CPU_SW_DOMAIN_PAN 1504 bool "Enable use of CPU domains to implement privileged no-access" 1505 depends on MMU && !ARM_LPAE 1506 default y 1507 help 1508 Increase kernel security by ensuring that normal kernel accesses 1509 are unable to access userspace addresses. This can help prevent 1510 use-after-free bugs becoming an exploitable privilege escalation 1511 by ensuring that magic values (such as LIST_POISON) will always 1512 fault when dereferenced. 1513 1514 CPUs with low-vector mappings use a best-efforts implementation. 1515 Their lower 1MB needs to remain accessible for the vectors, but 1516 the remainder of userspace will become appropriately inaccessible. 1517 1518config HW_PERF_EVENTS 1519 def_bool y 1520 depends on ARM_PMU 1521 1522config ARCH_WANT_GENERAL_HUGETLB 1523 def_bool y 1524 1525config ARM_MODULE_PLTS 1526 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1527 depends on MODULES 1528 default y 1529 help 1530 Allocate PLTs when loading modules so that jumps and calls whose 1531 targets are too far away for their relative offsets to be encoded 1532 in the instructions themselves can be bounced via veneers in the 1533 module's PLT. This allows modules to be allocated in the generic 1534 vmalloc area after the dedicated module memory area has been 1535 exhausted. The modules will use slightly more memory, but after 1536 rounding up to page size, the actual memory footprint is usually 1537 the same. 1538 1539 Disabling this is usually safe for small single-platform 1540 configurations. If unsure, say y. 1541 1542config FORCE_MAX_ZONEORDER 1543 int "Maximum zone order" 1544 default "12" if SOC_AM33XX 1545 default "9" if SA1111 1546 default "11" 1547 help 1548 The kernel memory allocator divides physically contiguous memory 1549 blocks into "zones", where each zone is a power of two number of 1550 pages. This option selects the largest power of two that the kernel 1551 keeps in the memory allocator. If you need to allocate very large 1552 blocks of physically contiguous memory, then you may need to 1553 increase this value. 1554 1555 This config option is actually maximum order plus one. For example, 1556 a value of 11 means that the largest free memory block is 2^10 pages. 1557 1558config ALIGNMENT_TRAP 1559 def_bool CPU_CP15_MMU 1560 select HAVE_PROC_CPU if PROC_FS 1561 help 1562 ARM processors cannot fetch/store information which is not 1563 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1564 address divisible by 4. On 32-bit ARM processors, these non-aligned 1565 fetch/store instructions will be emulated in software if you say 1566 here, which has a severe performance impact. This is necessary for 1567 correct operation of some network protocols. With an IP-only 1568 configuration it is safe to say N, otherwise say Y. 1569 1570config UACCESS_WITH_MEMCPY 1571 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1572 depends on MMU 1573 default y if CPU_FEROCEON 1574 help 1575 Implement faster copy_to_user and clear_user methods for CPU 1576 cores where a 8-word STM instruction give significantly higher 1577 memory write throughput than a sequence of individual 32bit stores. 1578 1579 A possible side effect is a slight increase in scheduling latency 1580 between threads sharing the same address space if they invoke 1581 such copy operations with large buffers. 1582 1583 However, if the CPU data cache is using a write-allocate mode, 1584 this option is unlikely to provide any performance gain. 1585 1586config PARAVIRT 1587 bool "Enable paravirtualization code" 1588 help 1589 This changes the kernel so it can modify itself when it is run 1590 under a hypervisor, potentially improving performance significantly 1591 over full virtualization. 1592 1593config PARAVIRT_TIME_ACCOUNTING 1594 bool "Paravirtual steal time accounting" 1595 select PARAVIRT 1596 help 1597 Select this option to enable fine granularity task steal time 1598 accounting. Time spent executing other tasks in parallel with 1599 the current vCPU is discounted from the vCPU power. To account for 1600 that, there can be a small performance impact. 1601 1602 If in doubt, say N here. 1603 1604config XEN_DOM0 1605 def_bool y 1606 depends on XEN 1607 1608config XEN 1609 bool "Xen guest support on ARM" 1610 depends on ARM && AEABI && OF 1611 depends on CPU_V7 && !CPU_V6 1612 depends on !GENERIC_ATOMIC64 1613 depends on MMU 1614 select ARCH_DMA_ADDR_T_64BIT 1615 select ARM_PSCI 1616 select SWIOTLB 1617 select SWIOTLB_XEN 1618 select PARAVIRT 1619 help 1620 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1621 1622config STACKPROTECTOR_PER_TASK 1623 bool "Use a unique stack canary value for each task" 1624 depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA 1625 select GCC_PLUGIN_ARM_SSP_PER_TASK 1626 default y 1627 help 1628 Due to the fact that GCC uses an ordinary symbol reference from 1629 which to load the value of the stack canary, this value can only 1630 change at reboot time on SMP systems, and all tasks running in the 1631 kernel's address space are forced to use the same canary value for 1632 the entire duration that the system is up. 1633 1634 Enable this option to switch to a different method that uses a 1635 different canary value for each task. 1636 1637endmenu 1638 1639menu "Boot options" 1640 1641config USE_OF 1642 bool "Flattened Device Tree support" 1643 select IRQ_DOMAIN 1644 select OF 1645 help 1646 Include support for flattened device tree machine descriptions. 1647 1648config ATAGS 1649 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1650 default y 1651 help 1652 This is the traditional way of passing data to the kernel at boot 1653 time. If you are solely relying on the flattened device tree (or 1654 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1655 to remove ATAGS support from your kernel binary. If unsure, 1656 leave this to y. 1657 1658config DEPRECATED_PARAM_STRUCT 1659 bool "Provide old way to pass kernel parameters" 1660 depends on ATAGS 1661 help 1662 This was deprecated in 2001 and announced to live on for 5 years. 1663 Some old boot loaders still use this way. 1664 1665# Compressed boot loader in ROM. Yes, we really want to ask about 1666# TEXT and BSS so we preserve their values in the config files. 1667config ZBOOT_ROM_TEXT 1668 hex "Compressed ROM boot loader base address" 1669 default 0x0 1670 help 1671 The physical address at which the ROM-able zImage is to be 1672 placed in the target. Platforms which normally make use of 1673 ROM-able zImage formats normally set this to a suitable 1674 value in their defconfig file. 1675 1676 If ZBOOT_ROM is not enabled, this has no effect. 1677 1678config ZBOOT_ROM_BSS 1679 hex "Compressed ROM boot loader BSS address" 1680 default 0x0 1681 help 1682 The base address of an area of read/write memory in the target 1683 for the ROM-able zImage which must be available while the 1684 decompressor is running. It must be large enough to hold the 1685 entire decompressed kernel plus an additional 128 KiB. 1686 Platforms which normally make use of ROM-able zImage formats 1687 normally set this to a suitable value in their defconfig file. 1688 1689 If ZBOOT_ROM is not enabled, this has no effect. 1690 1691config ZBOOT_ROM 1692 bool "Compressed boot loader in ROM/flash" 1693 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1694 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1695 help 1696 Say Y here if you intend to execute your compressed kernel image 1697 (zImage) directly from ROM or flash. If unsure, say N. 1698 1699config ARM_APPENDED_DTB 1700 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1701 depends on OF 1702 help 1703 With this option, the boot code will look for a device tree binary 1704 (DTB) appended to zImage 1705 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1706 1707 This is meant as a backward compatibility convenience for those 1708 systems with a bootloader that can't be upgraded to accommodate 1709 the documented boot protocol using a device tree. 1710 1711 Beware that there is very little in terms of protection against 1712 this option being confused by leftover garbage in memory that might 1713 look like a DTB header after a reboot if no actual DTB is appended 1714 to zImage. Do not leave this option active in a production kernel 1715 if you don't intend to always append a DTB. Proper passing of the 1716 location into r2 of a bootloader provided DTB is always preferable 1717 to this option. 1718 1719config ARM_ATAG_DTB_COMPAT 1720 bool "Supplement the appended DTB with traditional ATAG information" 1721 depends on ARM_APPENDED_DTB 1722 help 1723 Some old bootloaders can't be updated to a DTB capable one, yet 1724 they provide ATAGs with memory configuration, the ramdisk address, 1725 the kernel cmdline string, etc. Such information is dynamically 1726 provided by the bootloader and can't always be stored in a static 1727 DTB. To allow a device tree enabled kernel to be used with such 1728 bootloaders, this option allows zImage to extract the information 1729 from the ATAG list and store it at run time into the appended DTB. 1730 1731choice 1732 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1733 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1734 1735config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1736 bool "Use bootloader kernel arguments if available" 1737 help 1738 Uses the command-line options passed by the boot loader instead of 1739 the device tree bootargs property. If the boot loader doesn't provide 1740 any, the device tree bootargs property will be used. 1741 1742config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1743 bool "Extend with bootloader kernel arguments" 1744 help 1745 The command-line arguments provided by the boot loader will be 1746 appended to the the device tree bootargs property. 1747 1748endchoice 1749 1750config CMDLINE 1751 string "Default kernel command string" 1752 default "" 1753 help 1754 On some architectures (e.g. CATS), there is currently no way 1755 for the boot loader to pass arguments to the kernel. For these 1756 architectures, you should supply some command-line options at build 1757 time by entering them here. As a minimum, you should specify the 1758 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1759 1760choice 1761 prompt "Kernel command line type" if CMDLINE != "" 1762 default CMDLINE_FROM_BOOTLOADER 1763 depends on ATAGS 1764 1765config CMDLINE_FROM_BOOTLOADER 1766 bool "Use bootloader kernel arguments if available" 1767 help 1768 Uses the command-line options passed by the boot loader. If 1769 the boot loader doesn't provide any, the default kernel command 1770 string provided in CMDLINE will be used. 1771 1772config CMDLINE_EXTEND 1773 bool "Extend bootloader kernel arguments" 1774 help 1775 The command-line arguments provided by the boot loader will be 1776 appended to the default kernel command string. 1777 1778config CMDLINE_FORCE 1779 bool "Always use the default kernel command string" 1780 help 1781 Always use the default kernel command string, even if the boot 1782 loader passes other arguments to the kernel. 1783 This is useful if you cannot or don't want to change the 1784 command-line options your boot loader passes to the kernel. 1785endchoice 1786 1787config XIP_KERNEL 1788 bool "Kernel Execute-In-Place from ROM" 1789 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1790 help 1791 Execute-In-Place allows the kernel to run from non-volatile storage 1792 directly addressable by the CPU, such as NOR flash. This saves RAM 1793 space since the text section of the kernel is not loaded from flash 1794 to RAM. Read-write sections, such as the data section and stack, 1795 are still copied to RAM. The XIP kernel is not compressed since 1796 it has to run directly from flash, so it will take more space to 1797 store it. The flash address used to link the kernel object files, 1798 and for storing it, is configuration dependent. Therefore, if you 1799 say Y here, you must know the proper physical address where to 1800 store the kernel image depending on your own flash memory usage. 1801 1802 Also note that the make target becomes "make xipImage" rather than 1803 "make zImage" or "make Image". The final kernel binary to put in 1804 ROM memory will be arch/arm/boot/xipImage. 1805 1806 If unsure, say N. 1807 1808config XIP_PHYS_ADDR 1809 hex "XIP Kernel Physical Location" 1810 depends on XIP_KERNEL 1811 default "0x00080000" 1812 help 1813 This is the physical address in your flash memory the kernel will 1814 be linked for and stored to. This address is dependent on your 1815 own flash usage. 1816 1817config XIP_DEFLATED_DATA 1818 bool "Store kernel .data section compressed in ROM" 1819 depends on XIP_KERNEL 1820 select ZLIB_INFLATE 1821 help 1822 Before the kernel is actually executed, its .data section has to be 1823 copied to RAM from ROM. This option allows for storing that data 1824 in compressed form and decompressed to RAM rather than merely being 1825 copied, saving some precious ROM space. A possible drawback is a 1826 slightly longer boot delay. 1827 1828config KEXEC 1829 bool "Kexec system call (EXPERIMENTAL)" 1830 depends on (!SMP || PM_SLEEP_SMP) 1831 depends on MMU 1832 select KEXEC_CORE 1833 help 1834 kexec is a system call that implements the ability to shutdown your 1835 current kernel, and to start another kernel. It is like a reboot 1836 but it is independent of the system firmware. And like a reboot 1837 you can start any kernel with it, not just Linux. 1838 1839 It is an ongoing process to be certain the hardware in a machine 1840 is properly shutdown, so do not be surprised if this code does not 1841 initially work for you. 1842 1843config ATAGS_PROC 1844 bool "Export atags in procfs" 1845 depends on ATAGS && KEXEC 1846 default y 1847 help 1848 Should the atags used to boot the kernel be exported in an "atags" 1849 file in procfs. Useful with kexec. 1850 1851config CRASH_DUMP 1852 bool "Build kdump crash kernel (EXPERIMENTAL)" 1853 help 1854 Generate crash dump after being started by kexec. This should 1855 be normally only set in special crash dump kernels which are 1856 loaded in the main kernel with kexec-tools into a specially 1857 reserved region and then later executed after a crash by 1858 kdump/kexec. The crash dump kernel must be compiled to a 1859 memory address not used by the main kernel 1860 1861 For more details see Documentation/admin-guide/kdump/kdump.rst 1862 1863config AUTO_ZRELADDR 1864 bool "Auto calculation of the decompressed kernel image address" 1865 help 1866 ZRELADDR is the physical address where the decompressed kernel 1867 image will be placed. If AUTO_ZRELADDR is selected, the address 1868 will be determined at run-time, either by masking the current IP 1869 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1870 This assumes the zImage being placed in the first 128MB from 1871 start of memory. 1872 1873config EFI_STUB 1874 bool 1875 1876config EFI 1877 bool "UEFI runtime support" 1878 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1879 select UCS2_STRING 1880 select EFI_PARAMS_FROM_FDT 1881 select EFI_STUB 1882 select EFI_GENERIC_STUB 1883 select EFI_RUNTIME_WRAPPERS 1884 help 1885 This option provides support for runtime services provided 1886 by UEFI firmware (such as non-volatile variables, realtime 1887 clock, and platform reset). A UEFI stub is also provided to 1888 allow the kernel to be booted as an EFI application. This 1889 is only useful for kernels that may run on systems that have 1890 UEFI firmware. 1891 1892config DMI 1893 bool "Enable support for SMBIOS (DMI) tables" 1894 depends on EFI 1895 default y 1896 help 1897 This enables SMBIOS/DMI feature for systems. 1898 1899 This option is only useful on systems that have UEFI firmware. 1900 However, even with this option, the resultant kernel should 1901 continue to boot on existing non-UEFI platforms. 1902 1903 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1904 i.e., the the practice of identifying the platform via DMI to 1905 decide whether certain workarounds for buggy hardware and/or 1906 firmware need to be enabled. This would require the DMI subsystem 1907 to be enabled much earlier than we do on ARM, which is non-trivial. 1908 1909endmenu 1910 1911menu "CPU Power Management" 1912 1913source "drivers/cpufreq/Kconfig" 1914 1915source "drivers/cpuidle/Kconfig" 1916 1917endmenu 1918 1919menu "Floating point emulation" 1920 1921comment "At least one emulation must be selected" 1922 1923config FPE_NWFPE 1924 bool "NWFPE math emulation" 1925 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1926 help 1927 Say Y to include the NWFPE floating point emulator in the kernel. 1928 This is necessary to run most binaries. Linux does not currently 1929 support floating point hardware so you need to say Y here even if 1930 your machine has an FPA or floating point co-processor podule. 1931 1932 You may say N here if you are going to load the Acorn FPEmulator 1933 early in the bootup. 1934 1935config FPE_NWFPE_XP 1936 bool "Support extended precision" 1937 depends on FPE_NWFPE 1938 help 1939 Say Y to include 80-bit support in the kernel floating-point 1940 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1941 Note that gcc does not generate 80-bit operations by default, 1942 so in most cases this option only enlarges the size of the 1943 floating point emulator without any good reason. 1944 1945 You almost surely want to say N here. 1946 1947config FPE_FASTFPE 1948 bool "FastFPE math emulation (EXPERIMENTAL)" 1949 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1950 help 1951 Say Y here to include the FAST floating point emulator in the kernel. 1952 This is an experimental much faster emulator which now also has full 1953 precision for the mantissa. It does not support any exceptions. 1954 It is very simple, and approximately 3-6 times faster than NWFPE. 1955 1956 It should be sufficient for most programs. It may be not suitable 1957 for scientific calculations, but you have to check this for yourself. 1958 If you do not feel you need a faster FP emulation you should better 1959 choose NWFPE. 1960 1961config VFP 1962 bool "VFP-format floating point maths" 1963 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1964 help 1965 Say Y to include VFP support code in the kernel. This is needed 1966 if your hardware includes a VFP unit. 1967 1968 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1969 release notes and additional status information. 1970 1971 Say N if your target does not have VFP hardware. 1972 1973config VFPv3 1974 bool 1975 depends on VFP 1976 default y if CPU_V7 1977 1978config NEON 1979 bool "Advanced SIMD (NEON) Extension support" 1980 depends on VFPv3 && CPU_V7 1981 help 1982 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1983 Extension. 1984 1985config KERNEL_MODE_NEON 1986 bool "Support for NEON in kernel mode" 1987 depends on NEON && AEABI 1988 help 1989 Say Y to include support for NEON in kernel mode. 1990 1991endmenu 1992 1993menu "Power management options" 1994 1995source "kernel/power/Kconfig" 1996 1997config ARCH_SUSPEND_POSSIBLE 1998 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1999 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2000 def_bool y 2001 2002config ARM_CPU_SUSPEND 2003 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2004 depends on ARCH_SUSPEND_POSSIBLE 2005 2006config ARCH_HIBERNATION_POSSIBLE 2007 bool 2008 depends on MMU 2009 default y if ARCH_SUSPEND_POSSIBLE 2010 2011endmenu 2012 2013if CRYPTO 2014source "arch/arm/crypto/Kconfig" 2015endif 2016 2017source "arch/arm/Kconfig.assembler" 2018