1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_STACKWALK 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 24 select ARCH_HAS_SYNC_DMA_FOR_CPU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 80 select HAVE_ARCH_MMAP_RND_BITS if MMU 81 select HAVE_ARCH_PFN_VALID 82 select HAVE_ARCH_SECCOMP 83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 85 select HAVE_ARCH_TRACEHOOK 86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 87 select HAVE_ARM_SMCCC if CPU_V7 88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 89 select HAVE_CONTEXT_TRACKING_USER 90 select HAVE_C_RECORDMCOUNT 91 select HAVE_BUILDTIME_MCOUNT_SORT 92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 93 select HAVE_DMA_CONTIGUOUS if MMU 94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 97 select HAVE_EXIT_THREAD 98 select HAVE_FAST_GUP if ARM_LPAE 99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 100 select HAVE_FUNCTION_ERROR_INJECTION 101 select HAVE_FUNCTION_GRAPH_TRACER 102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 103 select HAVE_GCC_PLUGINS 104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 105 select HAVE_IRQ_TIME_ACCOUNTING 106 select HAVE_KERNEL_GZIP 107 select HAVE_KERNEL_LZ4 108 select HAVE_KERNEL_LZMA 109 select HAVE_KERNEL_LZO 110 select HAVE_KERNEL_XZ 111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 112 select HAVE_KRETPROBES if HAVE_KPROBES 113 select HAVE_MOD_ARCH_SPECIFIC 114 select HAVE_NMI 115 select HAVE_OPTPROBES if !THUMB2_KERNEL 116 select HAVE_PCI if MMU 117 select HAVE_PERF_EVENTS 118 select HAVE_PERF_REGS 119 select HAVE_PERF_USER_STACK_DUMP 120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 121 select HAVE_REGS_AND_STACK_ACCESS_API 122 select HAVE_RSEQ 123 select HAVE_STACKPROTECTOR 124 select HAVE_SYSCALL_TRACEPOINTS 125 select HAVE_UID16 126 select HAVE_VIRT_CPU_ACCOUNTING_GEN 127 select IRQ_FORCED_THREADING 128 select MODULES_USE_ELF_REL 129 select NEED_DMA_MAP_STATE 130 select OF_EARLY_FLATTREE if OF 131 select OLD_SIGACTION 132 select OLD_SIGSUSPEND3 133 select PCI_DOMAINS_GENERIC if PCI 134 select PCI_SYSCALL if PCI 135 select PERF_USE_VMALLOC 136 select RTC_LIB 137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 138 select SYS_SUPPORTS_APM_EMULATION 139 select THREAD_INFO_IN_TASK 140 select TIMER_OF if OF 141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 144 # Above selects are sorted alphabetically; please add new ones 145 # according to that. Thanks. 146 help 147 The ARM series is a line of low-power-consumption RISC chip designs 148 licensed by ARM Ltd and targeted at embedded applications and 149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 150 manufactured, but legacy ARM-based PC hardware remains popular in 151 Europe. There is an ARM Linux project with a web page at 152 <http://www.arm.linux.org.uk/>. 153 154config ARM_HAS_GROUP_RELOCS 155 def_bool y 156 depends on !LD_IS_LLD || LLD_VERSION >= 140000 157 depends on !COMPILE_TEST 158 help 159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 160 relocations, which have been around for a long time, but were not 161 supported in LLD until version 14. The combined range is -/+ 256 MiB, 162 which is usually sufficient, but not for allyesconfig, so we disable 163 this feature when doing compile testing. 164 165config ARM_DMA_USE_IOMMU 166 bool 167 select NEED_SG_DMA_LENGTH 168 169if ARM_DMA_USE_IOMMU 170 171config ARM_DMA_IOMMU_ALIGNMENT 172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 173 range 4 9 174 default 8 175 help 176 DMA mapping framework by default aligns all buffers to the smallest 177 PAGE_SIZE order which is greater than or equal to the requested buffer 178 size. This works well for buffers up to a few hundreds kilobytes, but 179 for larger buffers it just a waste of address space. Drivers which has 180 relatively small addressing window (like 64Mib) might run out of 181 virtual space with just a few allocations. 182 183 With this parameter you can specify the maximum PAGE_SIZE order for 184 DMA IOMMU buffers. Larger buffers will be aligned only to this 185 specified order. The order is expressed as a power of two multiplied 186 by the PAGE_SIZE. 187 188endif 189 190config SYS_SUPPORTS_APM_EMULATION 191 bool 192 193config HAVE_TCM 194 bool 195 select GENERIC_ALLOCATOR 196 197config HAVE_PROC_CPU 198 bool 199 200config NO_IOPORT_MAP 201 bool 202 203config SBUS 204 bool 205 206config STACKTRACE_SUPPORT 207 bool 208 default y 209 210config LOCKDEP_SUPPORT 211 bool 212 default y 213 214config ARCH_HAS_ILOG2_U32 215 bool 216 217config ARCH_HAS_ILOG2_U64 218 bool 219 220config ARCH_HAS_BANDGAP 221 bool 222 223config FIX_EARLYCON_MEM 224 def_bool y if MMU 225 226config GENERIC_HWEIGHT 227 bool 228 default y 229 230config GENERIC_CALIBRATE_DELAY 231 bool 232 default y 233 234config ARCH_MAY_HAVE_PC_FDC 235 bool 236 237config ARCH_SUPPORTS_UPROBES 238 def_bool y 239 240config GENERIC_ISA_DMA 241 bool 242 243config FIQ 244 bool 245 246config ARCH_MTD_XIP 247 bool 248 249config ARM_PATCH_PHYS_VIRT 250 bool "Patch physical to virtual translations at runtime" if EMBEDDED 251 default y 252 depends on MMU 253 help 254 Patch phys-to-virt and virt-to-phys translation functions at 255 boot and module load time according to the position of the 256 kernel in system memory. 257 258 This can only be used with non-XIP MMU kernels where the base 259 of physical memory is at a 2 MiB boundary. 260 261 Only disable this option if you know that you do not require 262 this feature (eg, building a kernel for a single machine) and 263 you need to shrink the kernel to the minimal size. 264 265config NEED_MACH_IO_H 266 bool 267 help 268 Select this when mach/io.h is required to provide special 269 definitions for this platform. The need for mach/io.h should 270 be avoided when possible. 271 272config NEED_MACH_MEMORY_H 273 bool 274 help 275 Select this when mach/memory.h is required to provide special 276 definitions for this platform. The need for mach/memory.h should 277 be avoided when possible. 278 279config PHYS_OFFSET 280 hex "Physical address of main memory" if MMU 281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 282 default DRAM_BASE if !MMU 283 default 0x00000000 if ARCH_FOOTBRIDGE 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0xa0000000 if ARCH_PXA 286 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 287 default 0 288 help 289 Please provide the physical address corresponding to the 290 location of main memory in your system. 291 292config GENERIC_BUG 293 def_bool y 294 depends on BUG 295 296config PGTABLE_LEVELS 297 int 298 default 3 if ARM_LPAE 299 default 2 300 301menu "System Type" 302 303config MMU 304 bool "MMU-based Paged Memory Management Support" 305 default y 306 help 307 Select if you want MMU-based virtualised addressing space 308 support by paged memory management. If unsure, say 'Y'. 309 310config ARM_SINGLE_ARMV7M 311 def_bool !MMU 312 select ARM_NVIC 313 select CPU_V7M 314 select NO_IOPORT_MAP 315 316config ARCH_MMAP_RND_BITS_MIN 317 default 8 318 319config ARCH_MMAP_RND_BITS_MAX 320 default 14 if PAGE_OFFSET=0x40000000 321 default 15 if PAGE_OFFSET=0x80000000 322 default 16 323 324config ARCH_MULTIPLATFORM 325 bool "Require kernel to be portable to multiple machines" if EXPERT 326 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 327 default y 328 help 329 In general, all Arm machines can be supported in a single 330 kernel image, covering either Armv4/v5 or Armv6/v7. 331 332 However, some configuration options require hardcoding machine 333 specific physical addresses or enable errata workarounds that may 334 break other machines. 335 336 Selecting N here allows using those options, including 337 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 338 339menu "Platform selection" 340 depends on MMU 341 342comment "CPU Core family selection" 343 344config ARCH_MULTI_V4 345 bool "ARMv4 based platforms (FA526, StrongARM)" 346 depends on !ARCH_MULTI_V6_V7 347 # https://github.com/llvm/llvm-project/issues/50764 348 depends on !LD_IS_LLD || LLD_VERSION >= 160000 349 select ARCH_MULTI_V4_V5 350 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 351 352config ARCH_MULTI_V4T 353 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 354 depends on !ARCH_MULTI_V6_V7 355 # https://github.com/llvm/llvm-project/issues/50764 356 depends on !LD_IS_LLD || LLD_VERSION >= 160000 357 select ARCH_MULTI_V4_V5 358 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 359 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 360 CPU_ARM925T || CPU_ARM940T) 361 362config ARCH_MULTI_V5 363 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 364 depends on !ARCH_MULTI_V6_V7 365 select ARCH_MULTI_V4_V5 366 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 367 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 368 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 369 370config ARCH_MULTI_V4_V5 371 bool 372 373config ARCH_MULTI_V6 374 bool "ARMv6 based platforms (ARM11)" 375 select ARCH_MULTI_V6_V7 376 select CPU_V6K 377 378config ARCH_MULTI_V7 379 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 380 default y 381 select ARCH_MULTI_V6_V7 382 select CPU_V7 383 select HAVE_SMP 384 385config ARCH_MULTI_V6_V7 386 bool 387 select MIGHT_HAVE_CACHE_L2X0 388 389config ARCH_MULTI_CPU_AUTO 390 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 391 select ARCH_MULTI_V5 392 393endmenu 394 395config ARCH_VIRT 396 bool "Dummy Virtual Machine" 397 depends on ARCH_MULTI_V7 398 select ARM_AMBA 399 select ARM_GIC 400 select ARM_GIC_V2M if PCI 401 select ARM_GIC_V3 402 select ARM_GIC_V3_ITS if PCI 403 select ARM_PSCI 404 select HAVE_ARM_ARCH_TIMER 405 406config ARCH_AIROHA 407 bool "Airoha SoC Support" 408 depends on ARCH_MULTI_V7 409 select ARM_AMBA 410 select ARM_GIC 411 select ARM_GIC_V3 412 select ARM_PSCI 413 select HAVE_ARM_ARCH_TIMER 414 help 415 Support for Airoha EN7523 SoCs 416 417# 418# This is sorted alphabetically by mach-* pathname. However, plat-* 419# Kconfigs may be included either alphabetically (according to the 420# plat- suffix) or along side the corresponding mach-* source. 421# 422source "arch/arm/mach-actions/Kconfig" 423 424source "arch/arm/mach-alpine/Kconfig" 425 426source "arch/arm/mach-artpec/Kconfig" 427 428source "arch/arm/mach-asm9260/Kconfig" 429 430source "arch/arm/mach-aspeed/Kconfig" 431 432source "arch/arm/mach-at91/Kconfig" 433 434source "arch/arm/mach-axxia/Kconfig" 435 436source "arch/arm/mach-bcm/Kconfig" 437 438source "arch/arm/mach-berlin/Kconfig" 439 440source "arch/arm/mach-clps711x/Kconfig" 441 442source "arch/arm/mach-davinci/Kconfig" 443 444source "arch/arm/mach-digicolor/Kconfig" 445 446source "arch/arm/mach-dove/Kconfig" 447 448source "arch/arm/mach-ep93xx/Kconfig" 449 450source "arch/arm/mach-exynos/Kconfig" 451 452source "arch/arm/mach-footbridge/Kconfig" 453 454source "arch/arm/mach-gemini/Kconfig" 455 456source "arch/arm/mach-highbank/Kconfig" 457 458source "arch/arm/mach-hisi/Kconfig" 459 460source "arch/arm/mach-hpe/Kconfig" 461 462source "arch/arm/mach-imx/Kconfig" 463 464source "arch/arm/mach-ixp4xx/Kconfig" 465 466source "arch/arm/mach-keystone/Kconfig" 467 468source "arch/arm/mach-lpc32xx/Kconfig" 469 470source "arch/arm/mach-mediatek/Kconfig" 471 472source "arch/arm/mach-meson/Kconfig" 473 474source "arch/arm/mach-milbeaut/Kconfig" 475 476source "arch/arm/mach-mmp/Kconfig" 477 478source "arch/arm/mach-moxart/Kconfig" 479 480source "arch/arm/mach-mstar/Kconfig" 481 482source "arch/arm/mach-mv78xx0/Kconfig" 483 484source "arch/arm/mach-mvebu/Kconfig" 485 486source "arch/arm/mach-mxs/Kconfig" 487 488source "arch/arm/mach-nomadik/Kconfig" 489 490source "arch/arm/mach-npcm/Kconfig" 491 492source "arch/arm/mach-nspire/Kconfig" 493 494source "arch/arm/mach-omap1/Kconfig" 495 496source "arch/arm/mach-omap2/Kconfig" 497 498source "arch/arm/mach-orion5x/Kconfig" 499 500source "arch/arm/mach-oxnas/Kconfig" 501 502source "arch/arm/mach-pxa/Kconfig" 503 504source "arch/arm/mach-qcom/Kconfig" 505 506source "arch/arm/mach-rda/Kconfig" 507 508source "arch/arm/mach-realtek/Kconfig" 509 510source "arch/arm/mach-rpc/Kconfig" 511 512source "arch/arm/mach-rockchip/Kconfig" 513 514source "arch/arm/mach-s3c/Kconfig" 515 516source "arch/arm/mach-s5pv210/Kconfig" 517 518source "arch/arm/mach-sa1100/Kconfig" 519 520source "arch/arm/mach-shmobile/Kconfig" 521 522source "arch/arm/mach-socfpga/Kconfig" 523 524source "arch/arm/mach-spear/Kconfig" 525 526source "arch/arm/mach-sti/Kconfig" 527 528source "arch/arm/mach-stm32/Kconfig" 529 530source "arch/arm/mach-sunplus/Kconfig" 531 532source "arch/arm/mach-sunxi/Kconfig" 533 534source "arch/arm/mach-tegra/Kconfig" 535 536source "arch/arm/mach-uniphier/Kconfig" 537 538source "arch/arm/mach-ux500/Kconfig" 539 540source "arch/arm/mach-versatile/Kconfig" 541 542source "arch/arm/mach-vt8500/Kconfig" 543 544source "arch/arm/mach-zynq/Kconfig" 545 546# ARMv7-M architecture 547config ARCH_LPC18XX 548 bool "NXP LPC18xx/LPC43xx" 549 depends on ARM_SINGLE_ARMV7M 550 select ARCH_HAS_RESET_CONTROLLER 551 select ARM_AMBA 552 select CLKSRC_LPC32XX 553 select PINCTRL 554 help 555 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 556 high performance microcontrollers. 557 558config ARCH_MPS2 559 bool "ARM MPS2 platform" 560 depends on ARM_SINGLE_ARMV7M 561 select ARM_AMBA 562 select CLKSRC_MPS2 563 help 564 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 565 with a range of available cores like Cortex-M3/M4/M7. 566 567 Please, note that depends which Application Note is used memory map 568 for the platform may vary, so adjustment of RAM base might be needed. 569 570# Definitions to make life easier 571config ARCH_ACORN 572 bool 573 574config PLAT_ORION 575 bool 576 select CLKSRC_MMIO 577 select GENERIC_IRQ_CHIP 578 select IRQ_DOMAIN 579 580config PLAT_ORION_LEGACY 581 bool 582 select PLAT_ORION 583 584config PLAT_VERSATILE 585 bool 586 587source "arch/arm/mm/Kconfig" 588 589config IWMMXT 590 bool "Enable iWMMXt support" 591 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 592 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 593 help 594 Enable support for iWMMXt context switching at run time if 595 running on a CPU that supports it. 596 597if !MMU 598source "arch/arm/Kconfig-nommu" 599endif 600 601config PJ4B_ERRATA_4742 602 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 603 depends on CPU_PJ4B && MACH_ARMADA_370 604 default y 605 help 606 When coming out of either a Wait for Interrupt (WFI) or a Wait for 607 Event (WFE) IDLE states, a specific timing sensitivity exists between 608 the retiring WFI/WFE instructions and the newly issued subsequent 609 instructions. This sensitivity can result in a CPU hang scenario. 610 Workaround: 611 The software must insert either a Data Synchronization Barrier (DSB) 612 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 613 instruction 614 615config ARM_ERRATA_326103 616 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 617 depends on CPU_V6 618 help 619 Executing a SWP instruction to read-only memory does not set bit 11 620 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 621 treat the access as a read, preventing a COW from occurring and 622 causing the faulting task to livelock. 623 624config ARM_ERRATA_411920 625 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 626 depends on CPU_V6 || CPU_V6K 627 help 628 Invalidation of the Instruction Cache operation can 629 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 630 It does not affect the MPCore. This option enables the ARM Ltd. 631 recommended workaround. 632 633config ARM_ERRATA_430973 634 bool "ARM errata: Stale prediction on replaced interworking branch" 635 depends on CPU_V7 636 help 637 This option enables the workaround for the 430973 Cortex-A8 638 r1p* erratum. If a code sequence containing an ARM/Thumb 639 interworking branch is replaced with another code sequence at the 640 same virtual address, whether due to self-modifying code or virtual 641 to physical address re-mapping, Cortex-A8 does not recover from the 642 stale interworking branch prediction. This results in Cortex-A8 643 executing the new code sequence in the incorrect ARM or Thumb state. 644 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 645 and also flushes the branch target cache at every context switch. 646 Note that setting specific bits in the ACTLR register may not be 647 available in non-secure mode. 648 649config ARM_ERRATA_458693 650 bool "ARM errata: Processor deadlock when a false hazard is created" 651 depends on CPU_V7 652 depends on !ARCH_MULTIPLATFORM 653 help 654 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 655 erratum. For very specific sequences of memory operations, it is 656 possible for a hazard condition intended for a cache line to instead 657 be incorrectly associated with a different cache line. This false 658 hazard might then cause a processor deadlock. The workaround enables 659 the L1 caching of the NEON accesses and disables the PLD instruction 660 in the ACTLR register. Note that setting specific bits in the ACTLR 661 register may not be available in non-secure mode and thus is not 662 available on a multiplatform kernel. This should be applied by the 663 bootloader instead. 664 665config ARM_ERRATA_460075 666 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 667 depends on CPU_V7 668 depends on !ARCH_MULTIPLATFORM 669 help 670 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 671 erratum. Any asynchronous access to the L2 cache may encounter a 672 situation in which recent store transactions to the L2 cache are lost 673 and overwritten with stale memory contents from external memory. The 674 workaround disables the write-allocate mode for the L2 cache via the 675 ACTLR register. Note that setting specific bits in the ACTLR register 676 may not be available in non-secure mode and thus is not available on 677 a multiplatform kernel. This should be applied by the bootloader 678 instead. 679 680config ARM_ERRATA_742230 681 bool "ARM errata: DMB operation may be faulty" 682 depends on CPU_V7 && SMP 683 depends on !ARCH_MULTIPLATFORM 684 help 685 This option enables the workaround for the 742230 Cortex-A9 686 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 687 between two write operations may not ensure the correct visibility 688 ordering of the two writes. This workaround sets a specific bit in 689 the diagnostic register of the Cortex-A9 which causes the DMB 690 instruction to behave as a DSB, ensuring the correct behaviour of 691 the two writes. Note that setting specific bits in the diagnostics 692 register may not be available in non-secure mode and thus is not 693 available on a multiplatform kernel. This should be applied by the 694 bootloader instead. 695 696config ARM_ERRATA_742231 697 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 698 depends on CPU_V7 && SMP 699 depends on !ARCH_MULTIPLATFORM 700 help 701 This option enables the workaround for the 742231 Cortex-A9 702 (r2p0..r2p2) erratum. Under certain conditions, specific to the 703 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 704 accessing some data located in the same cache line, may get corrupted 705 data due to bad handling of the address hazard when the line gets 706 replaced from one of the CPUs at the same time as another CPU is 707 accessing it. This workaround sets specific bits in the diagnostic 708 register of the Cortex-A9 which reduces the linefill issuing 709 capabilities of the processor. Note that setting specific bits in the 710 diagnostics register may not be available in non-secure mode and thus 711 is not available on a multiplatform kernel. This should be applied by 712 the bootloader instead. 713 714config ARM_ERRATA_643719 715 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 716 depends on CPU_V7 && SMP 717 default y 718 help 719 This option enables the workaround for the 643719 Cortex-A9 (prior to 720 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 721 register returns zero when it should return one. The workaround 722 corrects this value, ensuring cache maintenance operations which use 723 it behave as intended and avoiding data corruption. 724 725config ARM_ERRATA_720789 726 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 727 depends on CPU_V7 728 help 729 This option enables the workaround for the 720789 Cortex-A9 (prior to 730 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 731 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 732 As a consequence of this erratum, some TLB entries which should be 733 invalidated are not, resulting in an incoherency in the system page 734 tables. The workaround changes the TLB flushing routines to invalidate 735 entries regardless of the ASID. 736 737config ARM_ERRATA_743622 738 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 739 depends on CPU_V7 740 depends on !ARCH_MULTIPLATFORM 741 help 742 This option enables the workaround for the 743622 Cortex-A9 743 (r2p*) erratum. Under very rare conditions, a faulty 744 optimisation in the Cortex-A9 Store Buffer may lead to data 745 corruption. This workaround sets a specific bit in the diagnostic 746 register of the Cortex-A9 which disables the Store Buffer 747 optimisation, preventing the defect from occurring. This has no 748 visible impact on the overall performance or power consumption of the 749 processor. Note that setting specific bits in the diagnostics register 750 may not be available in non-secure mode and thus is not available on a 751 multiplatform kernel. This should be applied by the bootloader instead. 752 753config ARM_ERRATA_751472 754 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 755 depends on CPU_V7 756 depends on !ARCH_MULTIPLATFORM 757 help 758 This option enables the workaround for the 751472 Cortex-A9 (prior 759 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 760 completion of a following broadcasted operation if the second 761 operation is received by a CPU before the ICIALLUIS has completed, 762 potentially leading to corrupted entries in the cache or TLB. 763 Note that setting specific bits in the diagnostics register may 764 not be available in non-secure mode and thus is not available on 765 a multiplatform kernel. This should be applied by the bootloader 766 instead. 767 768config ARM_ERRATA_754322 769 bool "ARM errata: possible faulty MMU translations following an ASID switch" 770 depends on CPU_V7 771 help 772 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 773 r3p*) erratum. A speculative memory access may cause a page table walk 774 which starts prior to an ASID switch but completes afterwards. This 775 can populate the micro-TLB with a stale entry which may be hit with 776 the new ASID. This workaround places two dsb instructions in the mm 777 switching code so that no page table walks can cross the ASID switch. 778 779config ARM_ERRATA_754327 780 bool "ARM errata: no automatic Store Buffer drain" 781 depends on CPU_V7 && SMP 782 help 783 This option enables the workaround for the 754327 Cortex-A9 (prior to 784 r2p0) erratum. The Store Buffer does not have any automatic draining 785 mechanism and therefore a livelock may occur if an external agent 786 continuously polls a memory location waiting to observe an update. 787 This workaround defines cpu_relax() as smp_mb(), preventing correctly 788 written polling loops from denying visibility of updates to memory. 789 790config ARM_ERRATA_364296 791 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 792 depends on CPU_V6 793 help 794 This options enables the workaround for the 364296 ARM1136 795 r0p2 erratum (possible cache data corruption with 796 hit-under-miss enabled). It sets the undocumented bit 31 in 797 the auxiliary control register and the FI bit in the control 798 register, thus disabling hit-under-miss without putting the 799 processor into full low interrupt latency mode. ARM11MPCore 800 is not affected. 801 802config ARM_ERRATA_764369 803 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 804 depends on CPU_V7 && SMP 805 help 806 This option enables the workaround for erratum 764369 807 affecting Cortex-A9 MPCore with two or more processors (all 808 current revisions). Under certain timing circumstances, a data 809 cache line maintenance operation by MVA targeting an Inner 810 Shareable memory region may fail to proceed up to either the 811 Point of Coherency or to the Point of Unification of the 812 system. This workaround adds a DSB instruction before the 813 relevant cache maintenance functions and sets a specific bit 814 in the diagnostic control register of the SCU. 815 816config ARM_ERRATA_764319 817 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 818 depends on CPU_V7 819 help 820 This option enables the workaround for the 764319 Cortex A-9 erratum. 821 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 822 unexpected Undefined Instruction exception when the DBGSWENABLE 823 external pin is set to 0, even when the CP14 accesses are performed 824 from a privileged mode. This work around catches the exception in a 825 way the kernel does not stop execution. 826 827config ARM_ERRATA_775420 828 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 829 depends on CPU_V7 830 help 831 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 832 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 833 operation aborts with MMU exception, it might cause the processor 834 to deadlock. This workaround puts DSB before executing ISB if 835 an abort may occur on cache maintenance. 836 837config ARM_ERRATA_798181 838 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 839 depends on CPU_V7 && SMP 840 help 841 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 842 adequately shooting down all use of the old entries. This 843 option enables the Linux kernel workaround for this erratum 844 which sends an IPI to the CPUs that are running the same ASID 845 as the one being invalidated. 846 847config ARM_ERRATA_773022 848 bool "ARM errata: incorrect instructions may be executed from loop buffer" 849 depends on CPU_V7 850 help 851 This option enables the workaround for the 773022 Cortex-A15 852 (up to r0p4) erratum. In certain rare sequences of code, the 853 loop buffer may deliver incorrect instructions. This 854 workaround disables the loop buffer to avoid the erratum. 855 856config ARM_ERRATA_818325_852422 857 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 858 depends on CPU_V7 859 help 860 This option enables the workaround for: 861 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 862 instruction might deadlock. Fixed in r0p1. 863 - Cortex-A12 852422: Execution of a sequence of instructions might 864 lead to either a data corruption or a CPU deadlock. Not fixed in 865 any Cortex-A12 cores yet. 866 This workaround for all both errata involves setting bit[12] of the 867 Feature Register. This bit disables an optimisation applied to a 868 sequence of 2 instructions that use opposing condition codes. 869 870config ARM_ERRATA_821420 871 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 872 depends on CPU_V7 873 help 874 This option enables the workaround for the 821420 Cortex-A12 875 (all revs) erratum. In very rare timing conditions, a sequence 876 of VMOV to Core registers instructions, for which the second 877 one is in the shadow of a branch or abort, can lead to a 878 deadlock when the VMOV instructions are issued out-of-order. 879 880config ARM_ERRATA_825619 881 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 882 depends on CPU_V7 883 help 884 This option enables the workaround for the 825619 Cortex-A12 885 (all revs) erratum. Within rare timing constraints, executing a 886 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 887 and Device/Strongly-Ordered loads and stores might cause deadlock 888 889config ARM_ERRATA_857271 890 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 891 depends on CPU_V7 892 help 893 This option enables the workaround for the 857271 Cortex-A12 894 (all revs) erratum. Under very rare timing conditions, the CPU might 895 hang. The workaround is expected to have a < 1% performance impact. 896 897config ARM_ERRATA_852421 898 bool "ARM errata: A17: DMB ST might fail to create order between stores" 899 depends on CPU_V7 900 help 901 This option enables the workaround for the 852421 Cortex-A17 902 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 903 execution of a DMB ST instruction might fail to properly order 904 stores from GroupA and stores from GroupB. 905 906config ARM_ERRATA_852423 907 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 908 depends on CPU_V7 909 help 910 This option enables the workaround for: 911 - Cortex-A17 852423: Execution of a sequence of instructions might 912 lead to either a data corruption or a CPU deadlock. Not fixed in 913 any Cortex-A17 cores yet. 914 This is identical to Cortex-A12 erratum 852422. It is a separate 915 config option from the A12 erratum due to the way errata are checked 916 for and handled. 917 918config ARM_ERRATA_857272 919 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 920 depends on CPU_V7 921 help 922 This option enables the workaround for the 857272 Cortex-A17 erratum. 923 This erratum is not known to be fixed in any A17 revision. 924 This is identical to Cortex-A12 erratum 857271. It is a separate 925 config option from the A12 erratum due to the way errata are checked 926 for and handled. 927 928endmenu 929 930source "arch/arm/common/Kconfig" 931 932menu "Bus support" 933 934config ISA 935 bool 936 help 937 Find out whether you have ISA slots on your motherboard. ISA is the 938 name of a bus system, i.e. the way the CPU talks to the other stuff 939 inside your box. Other bus systems are PCI, EISA, MicroChannel 940 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 941 newer boards don't support it. If you have ISA, say Y, otherwise N. 942 943# Select ISA DMA interface 944config ISA_DMA_API 945 bool 946 947config ARM_ERRATA_814220 948 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 949 depends on CPU_V7 950 help 951 The v7 ARM states that all cache and branch predictor maintenance 952 operations that do not specify an address execute, relative to 953 each other, in program order. 954 However, because of this erratum, an L2 set/way cache maintenance 955 operation can overtake an L1 set/way cache maintenance operation. 956 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 957 r0p4, r0p5. 958 959endmenu 960 961menu "Kernel Features" 962 963config HAVE_SMP 964 bool 965 help 966 This option should be selected by machines which have an SMP- 967 capable CPU. 968 969 The only effect of this option is to make the SMP-related 970 options available to the user for configuration. 971 972config SMP 973 bool "Symmetric Multi-Processing" 974 depends on CPU_V6K || CPU_V7 975 depends on HAVE_SMP 976 depends on MMU || ARM_MPU 977 select IRQ_WORK 978 help 979 This enables support for systems with more than one CPU. If you have 980 a system with only one CPU, say N. If you have a system with more 981 than one CPU, say Y. 982 983 If you say N here, the kernel will run on uni- and multiprocessor 984 machines, but will use only one CPU of a multiprocessor machine. If 985 you say Y here, the kernel will run on many, but not all, 986 uniprocessor machines. On a uniprocessor machine, the kernel 987 will run faster if you say N here. 988 989 See also <file:Documentation/x86/i386/IO-APIC.rst>, 990 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 991 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 992 993 If you don't know what to do here, say N. 994 995config SMP_ON_UP 996 bool "Allow booting SMP kernel on uniprocessor systems" 997 depends on SMP && MMU 998 default y 999 help 1000 SMP kernels contain instructions which fail on non-SMP processors. 1001 Enabling this option allows the kernel to modify itself to make 1002 these instructions safe. Disabling it allows about 1K of space 1003 savings. 1004 1005 If you don't know what to do here, say Y. 1006 1007 1008config CURRENT_POINTER_IN_TPIDRURO 1009 def_bool y 1010 depends on CPU_32v6K && !CPU_V6 1011 1012config IRQSTACKS 1013 def_bool y 1014 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1015 select HAVE_SOFTIRQ_ON_OWN_STACK 1016 1017config ARM_CPU_TOPOLOGY 1018 bool "Support cpu topology definition" 1019 depends on SMP && CPU_V7 1020 default y 1021 help 1022 Support ARM cpu topology definition. The MPIDR register defines 1023 affinity between processors which is then used to describe the cpu 1024 topology of an ARM System. 1025 1026config SCHED_MC 1027 bool "Multi-core scheduler support" 1028 depends on ARM_CPU_TOPOLOGY 1029 help 1030 Multi-core scheduler support improves the CPU scheduler's decision 1031 making when dealing with multi-core CPU chips at a cost of slightly 1032 increased overhead in some places. If unsure say N here. 1033 1034config SCHED_SMT 1035 bool "SMT scheduler support" 1036 depends on ARM_CPU_TOPOLOGY 1037 help 1038 Improves the CPU scheduler's decision making when dealing with 1039 MultiThreading at a cost of slightly increased overhead in some 1040 places. If unsure say N here. 1041 1042config HAVE_ARM_SCU 1043 bool 1044 help 1045 This option enables support for the ARM snoop control unit 1046 1047config HAVE_ARM_ARCH_TIMER 1048 bool "Architected timer support" 1049 depends on CPU_V7 1050 select ARM_ARCH_TIMER 1051 help 1052 This option enables support for the ARM architected timer 1053 1054config HAVE_ARM_TWD 1055 bool 1056 help 1057 This options enables support for the ARM timer and watchdog unit 1058 1059config MCPM 1060 bool "Multi-Cluster Power Management" 1061 depends on CPU_V7 && SMP 1062 help 1063 This option provides the common power management infrastructure 1064 for (multi-)cluster based systems, such as big.LITTLE based 1065 systems. 1066 1067config MCPM_QUAD_CLUSTER 1068 bool 1069 depends on MCPM 1070 help 1071 To avoid wasting resources unnecessarily, MCPM only supports up 1072 to 2 clusters by default. 1073 Platforms with 3 or 4 clusters that use MCPM must select this 1074 option to allow the additional clusters to be managed. 1075 1076config BIG_LITTLE 1077 bool "big.LITTLE support (Experimental)" 1078 depends on CPU_V7 && SMP 1079 select MCPM 1080 help 1081 This option enables support selections for the big.LITTLE 1082 system architecture. 1083 1084config BL_SWITCHER 1085 bool "big.LITTLE switcher support" 1086 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1087 select CPU_PM 1088 help 1089 The big.LITTLE "switcher" provides the core functionality to 1090 transparently handle transition between a cluster of A15's 1091 and a cluster of A7's in a big.LITTLE system. 1092 1093config BL_SWITCHER_DUMMY_IF 1094 tristate "Simple big.LITTLE switcher user interface" 1095 depends on BL_SWITCHER && DEBUG_KERNEL 1096 help 1097 This is a simple and dummy char dev interface to control 1098 the big.LITTLE switcher core code. It is meant for 1099 debugging purposes only. 1100 1101choice 1102 prompt "Memory split" 1103 depends on MMU 1104 default VMSPLIT_3G 1105 help 1106 Select the desired split between kernel and user memory. 1107 1108 If you are not absolutely sure what you are doing, leave this 1109 option alone! 1110 1111 config VMSPLIT_3G 1112 bool "3G/1G user/kernel split" 1113 config VMSPLIT_3G_OPT 1114 depends on !ARM_LPAE 1115 bool "3G/1G user/kernel split (for full 1G low memory)" 1116 config VMSPLIT_2G 1117 bool "2G/2G user/kernel split" 1118 config VMSPLIT_1G 1119 bool "1G/3G user/kernel split" 1120endchoice 1121 1122config PAGE_OFFSET 1123 hex 1124 default PHYS_OFFSET if !MMU 1125 default 0x40000000 if VMSPLIT_1G 1126 default 0x80000000 if VMSPLIT_2G 1127 default 0xB0000000 if VMSPLIT_3G_OPT 1128 default 0xC0000000 1129 1130config KASAN_SHADOW_OFFSET 1131 hex 1132 depends on KASAN 1133 default 0x1f000000 if PAGE_OFFSET=0x40000000 1134 default 0x5f000000 if PAGE_OFFSET=0x80000000 1135 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1136 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1137 default 0xffffffff 1138 1139config NR_CPUS 1140 int "Maximum number of CPUs (2-32)" 1141 range 2 16 if DEBUG_KMAP_LOCAL 1142 range 2 32 if !DEBUG_KMAP_LOCAL 1143 depends on SMP 1144 default "4" 1145 help 1146 The maximum number of CPUs that the kernel can support. 1147 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1148 debugging is enabled, which uses half of the per-CPU fixmap 1149 slots as guard regions. 1150 1151config HOTPLUG_CPU 1152 bool "Support for hot-pluggable CPUs" 1153 depends on SMP 1154 select GENERIC_IRQ_MIGRATION 1155 help 1156 Say Y here to experiment with turning CPUs off and on. CPUs 1157 can be controlled through /sys/devices/system/cpu. 1158 1159config ARM_PSCI 1160 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1161 depends on HAVE_ARM_SMCCC 1162 select ARM_PSCI_FW 1163 help 1164 Say Y here if you want Linux to communicate with system firmware 1165 implementing the PSCI specification for CPU-centric power 1166 management operations described in ARM document number ARM DEN 1167 0022A ("Power State Coordination Interface System Software on 1168 ARM processors"). 1169 1170config HZ_FIXED 1171 int 1172 default 128 if SOC_AT91RM9200 1173 default 0 1174 1175choice 1176 depends on HZ_FIXED = 0 1177 prompt "Timer frequency" 1178 1179config HZ_100 1180 bool "100 Hz" 1181 1182config HZ_200 1183 bool "200 Hz" 1184 1185config HZ_250 1186 bool "250 Hz" 1187 1188config HZ_300 1189 bool "300 Hz" 1190 1191config HZ_500 1192 bool "500 Hz" 1193 1194config HZ_1000 1195 bool "1000 Hz" 1196 1197endchoice 1198 1199config HZ 1200 int 1201 default HZ_FIXED if HZ_FIXED != 0 1202 default 100 if HZ_100 1203 default 200 if HZ_200 1204 default 250 if HZ_250 1205 default 300 if HZ_300 1206 default 500 if HZ_500 1207 default 1000 1208 1209config SCHED_HRTICK 1210 def_bool HIGH_RES_TIMERS 1211 1212config THUMB2_KERNEL 1213 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1214 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1215 default y if CPU_THUMBONLY 1216 select ARM_UNWIND 1217 help 1218 By enabling this option, the kernel will be compiled in 1219 Thumb-2 mode. 1220 1221 If unsure, say N. 1222 1223config ARM_PATCH_IDIV 1224 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1225 depends on CPU_32v7 1226 default y 1227 help 1228 The ARM compiler inserts calls to __aeabi_idiv() and 1229 __aeabi_uidiv() when it needs to perform division on signed 1230 and unsigned integers. Some v7 CPUs have support for the sdiv 1231 and udiv instructions that can be used to implement those 1232 functions. 1233 1234 Enabling this option allows the kernel to modify itself to 1235 replace the first two instructions of these library functions 1236 with the sdiv or udiv plus "bx lr" instructions when the CPU 1237 it is running on supports them. Typically this will be faster 1238 and less power intensive than running the original library 1239 code to do integer division. 1240 1241config AEABI 1242 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1243 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1244 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1245 help 1246 This option allows for the kernel to be compiled using the latest 1247 ARM ABI (aka EABI). This is only useful if you are using a user 1248 space environment that is also compiled with EABI. 1249 1250 Since there are major incompatibilities between the legacy ABI and 1251 EABI, especially with regard to structure member alignment, this 1252 option also changes the kernel syscall calling convention to 1253 disambiguate both ABIs and allow for backward compatibility support 1254 (selected with CONFIG_OABI_COMPAT). 1255 1256 To use this you need GCC version 4.0.0 or later. 1257 1258config OABI_COMPAT 1259 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1260 depends on AEABI && !THUMB2_KERNEL 1261 help 1262 This option preserves the old syscall interface along with the 1263 new (ARM EABI) one. It also provides a compatibility layer to 1264 intercept syscalls that have structure arguments which layout 1265 in memory differs between the legacy ABI and the new ARM EABI 1266 (only for non "thumb" binaries). This option adds a tiny 1267 overhead to all syscalls and produces a slightly larger kernel. 1268 1269 The seccomp filter system will not be available when this is 1270 selected, since there is no way yet to sensibly distinguish 1271 between calling conventions during filtering. 1272 1273 If you know you'll be using only pure EABI user space then you 1274 can say N here. If this option is not selected and you attempt 1275 to execute a legacy ABI binary then the result will be 1276 UNPREDICTABLE (in fact it can be predicted that it won't work 1277 at all). If in doubt say N. 1278 1279config ARCH_SELECT_MEMORY_MODEL 1280 def_bool y 1281 1282config ARCH_FLATMEM_ENABLE 1283 def_bool !(ARCH_RPC || ARCH_SA1100) 1284 1285config ARCH_SPARSEMEM_ENABLE 1286 def_bool !ARCH_FOOTBRIDGE 1287 select SPARSEMEM_STATIC if SPARSEMEM 1288 1289config HIGHMEM 1290 bool "High Memory Support" 1291 depends on MMU 1292 select KMAP_LOCAL 1293 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1294 help 1295 The address space of ARM processors is only 4 Gigabytes large 1296 and it has to accommodate user address space, kernel address 1297 space as well as some memory mapped IO. That means that, if you 1298 have a large amount of physical memory and/or IO, not all of the 1299 memory can be "permanently mapped" by the kernel. The physical 1300 memory that is not permanently mapped is called "high memory". 1301 1302 Depending on the selected kernel/user memory split, minimum 1303 vmalloc space and actual amount of RAM, you may not need this 1304 option which should result in a slightly faster kernel. 1305 1306 If unsure, say n. 1307 1308config HIGHPTE 1309 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1310 depends on HIGHMEM 1311 default y 1312 help 1313 The VM uses one page of physical memory for each page table. 1314 For systems with a lot of processes, this can use a lot of 1315 precious low memory, eventually leading to low memory being 1316 consumed by page tables. Setting this option will allow 1317 user-space 2nd level page tables to reside in high memory. 1318 1319config CPU_SW_DOMAIN_PAN 1320 bool "Enable use of CPU domains to implement privileged no-access" 1321 depends on MMU && !ARM_LPAE 1322 default y 1323 help 1324 Increase kernel security by ensuring that normal kernel accesses 1325 are unable to access userspace addresses. This can help prevent 1326 use-after-free bugs becoming an exploitable privilege escalation 1327 by ensuring that magic values (such as LIST_POISON) will always 1328 fault when dereferenced. 1329 1330 CPUs with low-vector mappings use a best-efforts implementation. 1331 Their lower 1MB needs to remain accessible for the vectors, but 1332 the remainder of userspace will become appropriately inaccessible. 1333 1334config HW_PERF_EVENTS 1335 def_bool y 1336 depends on ARM_PMU 1337 1338config ARM_MODULE_PLTS 1339 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1340 depends on MODULES 1341 select KASAN_VMALLOC if KASAN 1342 default y 1343 help 1344 Allocate PLTs when loading modules so that jumps and calls whose 1345 targets are too far away for their relative offsets to be encoded 1346 in the instructions themselves can be bounced via veneers in the 1347 module's PLT. This allows modules to be allocated in the generic 1348 vmalloc area after the dedicated module memory area has been 1349 exhausted. The modules will use slightly more memory, but after 1350 rounding up to page size, the actual memory footprint is usually 1351 the same. 1352 1353 Disabling this is usually safe for small single-platform 1354 configurations. If unsure, say y. 1355 1356config ARCH_FORCE_MAX_ORDER 1357 int "Maximum zone order" 1358 default "11" if SOC_AM33XX 1359 default "8" if SA1111 1360 default "10" 1361 help 1362 The kernel memory allocator divides physically contiguous memory 1363 blocks into "zones", where each zone is a power of two number of 1364 pages. This option selects the largest power of two that the kernel 1365 keeps in the memory allocator. If you need to allocate very large 1366 blocks of physically contiguous memory, then you may need to 1367 increase this value. 1368 1369config ALIGNMENT_TRAP 1370 def_bool CPU_CP15_MMU 1371 select HAVE_PROC_CPU if PROC_FS 1372 help 1373 ARM processors cannot fetch/store information which is not 1374 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1375 address divisible by 4. On 32-bit ARM processors, these non-aligned 1376 fetch/store instructions will be emulated in software if you say 1377 here, which has a severe performance impact. This is necessary for 1378 correct operation of some network protocols. With an IP-only 1379 configuration it is safe to say N, otherwise say Y. 1380 1381config UACCESS_WITH_MEMCPY 1382 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1383 depends on MMU 1384 default y if CPU_FEROCEON 1385 help 1386 Implement faster copy_to_user and clear_user methods for CPU 1387 cores where a 8-word STM instruction give significantly higher 1388 memory write throughput than a sequence of individual 32bit stores. 1389 1390 A possible side effect is a slight increase in scheduling latency 1391 between threads sharing the same address space if they invoke 1392 such copy operations with large buffers. 1393 1394 However, if the CPU data cache is using a write-allocate mode, 1395 this option is unlikely to provide any performance gain. 1396 1397config PARAVIRT 1398 bool "Enable paravirtualization code" 1399 help 1400 This changes the kernel so it can modify itself when it is run 1401 under a hypervisor, potentially improving performance significantly 1402 over full virtualization. 1403 1404config PARAVIRT_TIME_ACCOUNTING 1405 bool "Paravirtual steal time accounting" 1406 select PARAVIRT 1407 help 1408 Select this option to enable fine granularity task steal time 1409 accounting. Time spent executing other tasks in parallel with 1410 the current vCPU is discounted from the vCPU power. To account for 1411 that, there can be a small performance impact. 1412 1413 If in doubt, say N here. 1414 1415config XEN_DOM0 1416 def_bool y 1417 depends on XEN 1418 1419config XEN 1420 bool "Xen guest support on ARM" 1421 depends on ARM && AEABI && OF 1422 depends on CPU_V7 && !CPU_V6 1423 depends on !GENERIC_ATOMIC64 1424 depends on MMU 1425 select ARCH_DMA_ADDR_T_64BIT 1426 select ARM_PSCI 1427 select SWIOTLB 1428 select SWIOTLB_XEN 1429 select PARAVIRT 1430 help 1431 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1432 1433config CC_HAVE_STACKPROTECTOR_TLS 1434 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1435 1436config STACKPROTECTOR_PER_TASK 1437 bool "Use a unique stack canary value for each task" 1438 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1439 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1440 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1441 default y 1442 help 1443 Due to the fact that GCC uses an ordinary symbol reference from 1444 which to load the value of the stack canary, this value can only 1445 change at reboot time on SMP systems, and all tasks running in the 1446 kernel's address space are forced to use the same canary value for 1447 the entire duration that the system is up. 1448 1449 Enable this option to switch to a different method that uses a 1450 different canary value for each task. 1451 1452endmenu 1453 1454menu "Boot options" 1455 1456config USE_OF 1457 bool "Flattened Device Tree support" 1458 select IRQ_DOMAIN 1459 select OF 1460 help 1461 Include support for flattened device tree machine descriptions. 1462 1463config ATAGS 1464 bool "Support for the traditional ATAGS boot data passing" 1465 default y 1466 help 1467 This is the traditional way of passing data to the kernel at boot 1468 time. If you are solely relying on the flattened device tree (or 1469 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1470 to remove ATAGS support from your kernel binary. 1471 1472config DEPRECATED_PARAM_STRUCT 1473 bool "Provide old way to pass kernel parameters" 1474 depends on ATAGS 1475 help 1476 This was deprecated in 2001 and announced to live on for 5 years. 1477 Some old boot loaders still use this way. 1478 1479# Compressed boot loader in ROM. Yes, we really want to ask about 1480# TEXT and BSS so we preserve their values in the config files. 1481config ZBOOT_ROM_TEXT 1482 hex "Compressed ROM boot loader base address" 1483 default 0x0 1484 help 1485 The physical address at which the ROM-able zImage is to be 1486 placed in the target. Platforms which normally make use of 1487 ROM-able zImage formats normally set this to a suitable 1488 value in their defconfig file. 1489 1490 If ZBOOT_ROM is not enabled, this has no effect. 1491 1492config ZBOOT_ROM_BSS 1493 hex "Compressed ROM boot loader BSS address" 1494 default 0x0 1495 help 1496 The base address of an area of read/write memory in the target 1497 for the ROM-able zImage which must be available while the 1498 decompressor is running. It must be large enough to hold the 1499 entire decompressed kernel plus an additional 128 KiB. 1500 Platforms which normally make use of ROM-able zImage formats 1501 normally set this to a suitable value in their defconfig file. 1502 1503 If ZBOOT_ROM is not enabled, this has no effect. 1504 1505config ZBOOT_ROM 1506 bool "Compressed boot loader in ROM/flash" 1507 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1508 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1509 help 1510 Say Y here if you intend to execute your compressed kernel image 1511 (zImage) directly from ROM or flash. If unsure, say N. 1512 1513config ARM_APPENDED_DTB 1514 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1515 depends on OF 1516 help 1517 With this option, the boot code will look for a device tree binary 1518 (DTB) appended to zImage 1519 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1520 1521 This is meant as a backward compatibility convenience for those 1522 systems with a bootloader that can't be upgraded to accommodate 1523 the documented boot protocol using a device tree. 1524 1525 Beware that there is very little in terms of protection against 1526 this option being confused by leftover garbage in memory that might 1527 look like a DTB header after a reboot if no actual DTB is appended 1528 to zImage. Do not leave this option active in a production kernel 1529 if you don't intend to always append a DTB. Proper passing of the 1530 location into r2 of a bootloader provided DTB is always preferable 1531 to this option. 1532 1533config ARM_ATAG_DTB_COMPAT 1534 bool "Supplement the appended DTB with traditional ATAG information" 1535 depends on ARM_APPENDED_DTB 1536 help 1537 Some old bootloaders can't be updated to a DTB capable one, yet 1538 they provide ATAGs with memory configuration, the ramdisk address, 1539 the kernel cmdline string, etc. Such information is dynamically 1540 provided by the bootloader and can't always be stored in a static 1541 DTB. To allow a device tree enabled kernel to be used with such 1542 bootloaders, this option allows zImage to extract the information 1543 from the ATAG list and store it at run time into the appended DTB. 1544 1545choice 1546 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1547 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1548 1549config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1550 bool "Use bootloader kernel arguments if available" 1551 help 1552 Uses the command-line options passed by the boot loader instead of 1553 the device tree bootargs property. If the boot loader doesn't provide 1554 any, the device tree bootargs property will be used. 1555 1556config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1557 bool "Extend with bootloader kernel arguments" 1558 help 1559 The command-line arguments provided by the boot loader will be 1560 appended to the the device tree bootargs property. 1561 1562endchoice 1563 1564config CMDLINE 1565 string "Default kernel command string" 1566 default "" 1567 help 1568 On some architectures (e.g. CATS), there is currently no way 1569 for the boot loader to pass arguments to the kernel. For these 1570 architectures, you should supply some command-line options at build 1571 time by entering them here. As a minimum, you should specify the 1572 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1573 1574choice 1575 prompt "Kernel command line type" if CMDLINE != "" 1576 default CMDLINE_FROM_BOOTLOADER 1577 1578config CMDLINE_FROM_BOOTLOADER 1579 bool "Use bootloader kernel arguments if available" 1580 help 1581 Uses the command-line options passed by the boot loader. If 1582 the boot loader doesn't provide any, the default kernel command 1583 string provided in CMDLINE will be used. 1584 1585config CMDLINE_EXTEND 1586 bool "Extend bootloader kernel arguments" 1587 help 1588 The command-line arguments provided by the boot loader will be 1589 appended to the default kernel command string. 1590 1591config CMDLINE_FORCE 1592 bool "Always use the default kernel command string" 1593 help 1594 Always use the default kernel command string, even if the boot 1595 loader passes other arguments to the kernel. 1596 This is useful if you cannot or don't want to change the 1597 command-line options your boot loader passes to the kernel. 1598endchoice 1599 1600config XIP_KERNEL 1601 bool "Kernel Execute-In-Place from ROM" 1602 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1603 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1604 help 1605 Execute-In-Place allows the kernel to run from non-volatile storage 1606 directly addressable by the CPU, such as NOR flash. This saves RAM 1607 space since the text section of the kernel is not loaded from flash 1608 to RAM. Read-write sections, such as the data section and stack, 1609 are still copied to RAM. The XIP kernel is not compressed since 1610 it has to run directly from flash, so it will take more space to 1611 store it. The flash address used to link the kernel object files, 1612 and for storing it, is configuration dependent. Therefore, if you 1613 say Y here, you must know the proper physical address where to 1614 store the kernel image depending on your own flash memory usage. 1615 1616 Also note that the make target becomes "make xipImage" rather than 1617 "make zImage" or "make Image". The final kernel binary to put in 1618 ROM memory will be arch/arm/boot/xipImage. 1619 1620 If unsure, say N. 1621 1622config XIP_PHYS_ADDR 1623 hex "XIP Kernel Physical Location" 1624 depends on XIP_KERNEL 1625 default "0x00080000" 1626 help 1627 This is the physical address in your flash memory the kernel will 1628 be linked for and stored to. This address is dependent on your 1629 own flash usage. 1630 1631config XIP_DEFLATED_DATA 1632 bool "Store kernel .data section compressed in ROM" 1633 depends on XIP_KERNEL 1634 select ZLIB_INFLATE 1635 help 1636 Before the kernel is actually executed, its .data section has to be 1637 copied to RAM from ROM. This option allows for storing that data 1638 in compressed form and decompressed to RAM rather than merely being 1639 copied, saving some precious ROM space. A possible drawback is a 1640 slightly longer boot delay. 1641 1642config KEXEC 1643 bool "Kexec system call (EXPERIMENTAL)" 1644 depends on (!SMP || PM_SLEEP_SMP) 1645 depends on MMU 1646 select KEXEC_CORE 1647 help 1648 kexec is a system call that implements the ability to shutdown your 1649 current kernel, and to start another kernel. It is like a reboot 1650 but it is independent of the system firmware. And like a reboot 1651 you can start any kernel with it, not just Linux. 1652 1653 It is an ongoing process to be certain the hardware in a machine 1654 is properly shutdown, so do not be surprised if this code does not 1655 initially work for you. 1656 1657config ATAGS_PROC 1658 bool "Export atags in procfs" 1659 depends on ATAGS && KEXEC 1660 default y 1661 help 1662 Should the atags used to boot the kernel be exported in an "atags" 1663 file in procfs. Useful with kexec. 1664 1665config CRASH_DUMP 1666 bool "Build kdump crash kernel (EXPERIMENTAL)" 1667 help 1668 Generate crash dump after being started by kexec. This should 1669 be normally only set in special crash dump kernels which are 1670 loaded in the main kernel with kexec-tools into a specially 1671 reserved region and then later executed after a crash by 1672 kdump/kexec. The crash dump kernel must be compiled to a 1673 memory address not used by the main kernel 1674 1675 For more details see Documentation/admin-guide/kdump/kdump.rst 1676 1677config AUTO_ZRELADDR 1678 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1679 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1680 help 1681 ZRELADDR is the physical address where the decompressed kernel 1682 image will be placed. If AUTO_ZRELADDR is selected, the address 1683 will be determined at run-time, either by masking the current IP 1684 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1685 This assumes the zImage being placed in the first 128MB from 1686 start of memory. 1687 1688config EFI_STUB 1689 bool 1690 1691config EFI 1692 bool "UEFI runtime support" 1693 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1694 select UCS2_STRING 1695 select EFI_PARAMS_FROM_FDT 1696 select EFI_STUB 1697 select EFI_GENERIC_STUB 1698 select EFI_RUNTIME_WRAPPERS 1699 help 1700 This option provides support for runtime services provided 1701 by UEFI firmware (such as non-volatile variables, realtime 1702 clock, and platform reset). A UEFI stub is also provided to 1703 allow the kernel to be booted as an EFI application. This 1704 is only useful for kernels that may run on systems that have 1705 UEFI firmware. 1706 1707config DMI 1708 bool "Enable support for SMBIOS (DMI) tables" 1709 depends on EFI 1710 default y 1711 help 1712 This enables SMBIOS/DMI feature for systems. 1713 1714 This option is only useful on systems that have UEFI firmware. 1715 However, even with this option, the resultant kernel should 1716 continue to boot on existing non-UEFI platforms. 1717 1718 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1719 i.e., the the practice of identifying the platform via DMI to 1720 decide whether certain workarounds for buggy hardware and/or 1721 firmware need to be enabled. This would require the DMI subsystem 1722 to be enabled much earlier than we do on ARM, which is non-trivial. 1723 1724endmenu 1725 1726menu "CPU Power Management" 1727 1728source "drivers/cpufreq/Kconfig" 1729 1730source "drivers/cpuidle/Kconfig" 1731 1732endmenu 1733 1734menu "Floating point emulation" 1735 1736comment "At least one emulation must be selected" 1737 1738config FPE_NWFPE 1739 bool "NWFPE math emulation" 1740 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1741 help 1742 Say Y to include the NWFPE floating point emulator in the kernel. 1743 This is necessary to run most binaries. Linux does not currently 1744 support floating point hardware so you need to say Y here even if 1745 your machine has an FPA or floating point co-processor podule. 1746 1747 You may say N here if you are going to load the Acorn FPEmulator 1748 early in the bootup. 1749 1750config FPE_NWFPE_XP 1751 bool "Support extended precision" 1752 depends on FPE_NWFPE 1753 help 1754 Say Y to include 80-bit support in the kernel floating-point 1755 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1756 Note that gcc does not generate 80-bit operations by default, 1757 so in most cases this option only enlarges the size of the 1758 floating point emulator without any good reason. 1759 1760 You almost surely want to say N here. 1761 1762config FPE_FASTFPE 1763 bool "FastFPE math emulation (EXPERIMENTAL)" 1764 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1765 help 1766 Say Y here to include the FAST floating point emulator in the kernel. 1767 This is an experimental much faster emulator which now also has full 1768 precision for the mantissa. It does not support any exceptions. 1769 It is very simple, and approximately 3-6 times faster than NWFPE. 1770 1771 It should be sufficient for most programs. It may be not suitable 1772 for scientific calculations, but you have to check this for yourself. 1773 If you do not feel you need a faster FP emulation you should better 1774 choose NWFPE. 1775 1776config VFP 1777 bool "VFP-format floating point maths" 1778 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1779 help 1780 Say Y to include VFP support code in the kernel. This is needed 1781 if your hardware includes a VFP unit. 1782 1783 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1784 release notes and additional status information. 1785 1786 Say N if your target does not have VFP hardware. 1787 1788config VFPv3 1789 bool 1790 depends on VFP 1791 default y if CPU_V7 1792 1793config NEON 1794 bool "Advanced SIMD (NEON) Extension support" 1795 depends on VFPv3 && CPU_V7 1796 help 1797 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1798 Extension. 1799 1800config KERNEL_MODE_NEON 1801 bool "Support for NEON in kernel mode" 1802 depends on NEON && AEABI 1803 help 1804 Say Y to include support for NEON in kernel mode. 1805 1806endmenu 1807 1808menu "Power management options" 1809 1810source "kernel/power/Kconfig" 1811 1812config ARCH_SUSPEND_POSSIBLE 1813 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1814 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1815 def_bool y 1816 1817config ARM_CPU_SUSPEND 1818 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1819 depends on ARCH_SUSPEND_POSSIBLE 1820 1821config ARCH_HIBERNATION_POSSIBLE 1822 bool 1823 depends on MMU 1824 default y if ARCH_SUSPEND_POSSIBLE 1825 1826endmenu 1827 1828source "arch/arm/Kconfig.assembler" 1829