1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_DEBUG_VIRTUAL if MMU 9 select ARCH_HAS_DEVMEM_IS_ALLOWED 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 22 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 23 select ARCH_HAVE_CUSTOM_GPIO_H 24 select ARCH_HAS_GCOV_PROFILE_ALL 25 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 26 select ARCH_MIGHT_HAVE_PC_PARPORT 27 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 28 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 29 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 30 select ARCH_SUPPORTS_ATOMIC_RMW 31 select ARCH_USE_BUILTIN_BSWAP 32 select ARCH_USE_CMPXCHG_LOCKREF 33 select ARCH_WANT_IPC_PARSE_VERSION 34 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 35 select BUILDTIME_EXTABLE_SORT if MMU 36 select CLONE_BACKWARDS 37 select CPU_PM if SUSPEND || CPU_IDLE 38 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 39 select DMA_DECLARE_COHERENT 40 select DMA_REMAP if MMU 41 select EDAC_SUPPORT 42 select EDAC_ATOMIC_SCRUB 43 select GENERIC_ALLOCATOR 44 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 45 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 46 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 47 select GENERIC_CPU_AUTOPROBE 48 select GENERIC_EARLY_IOREMAP 49 select GENERIC_IDLE_POLL_SETUP 50 select GENERIC_IRQ_PROBE 51 select GENERIC_IRQ_SHOW 52 select GENERIC_IRQ_SHOW_LEVEL 53 select GENERIC_PCI_IOMAP 54 select GENERIC_SCHED_CLOCK 55 select GENERIC_SMP_IDLE_THREAD 56 select GENERIC_STRNCPY_FROM_USER 57 select GENERIC_STRNLEN_USER 58 select HANDLE_DOMAIN_IRQ 59 select HARDIRQS_SW_RESEND 60 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 61 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 62 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 63 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 64 select HAVE_ARCH_MMAP_RND_BITS if MMU 65 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 66 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 67 select HAVE_ARCH_TRACEHOOK 68 select HAVE_ARM_SMCCC if CPU_V7 69 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 70 select HAVE_CONTEXT_TRACKING 71 select HAVE_C_RECORDMCOUNT 72 select HAVE_DEBUG_KMEMLEAK 73 select HAVE_DMA_CONTIGUOUS if MMU 74 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 75 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 76 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 77 select HAVE_EXIT_THREAD 78 select HAVE_FAST_GUP if ARM_LPAE 79 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 80 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 81 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 82 select HAVE_GCC_PLUGINS 83 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 84 select HAVE_IDE if PCI || ISA || PCMCIA 85 select HAVE_IRQ_TIME_ACCOUNTING 86 select HAVE_KERNEL_GZIP 87 select HAVE_KERNEL_LZ4 88 select HAVE_KERNEL_LZMA 89 select HAVE_KERNEL_LZO 90 select HAVE_KERNEL_XZ 91 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 92 select HAVE_KRETPROBES if HAVE_KPROBES 93 select HAVE_MOD_ARCH_SPECIFIC 94 select HAVE_NMI 95 select HAVE_OPROFILE if HAVE_PERF_EVENTS 96 select HAVE_OPTPROBES if !THUMB2_KERNEL 97 select HAVE_PERF_EVENTS 98 select HAVE_PERF_REGS 99 select HAVE_PERF_USER_STACK_DUMP 100 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 101 select HAVE_REGS_AND_STACK_ACCESS_API 102 select HAVE_RSEQ 103 select HAVE_STACKPROTECTOR 104 select HAVE_SYSCALL_TRACEPOINTS 105 select HAVE_UID16 106 select HAVE_VIRT_CPU_ACCOUNTING_GEN 107 select IRQ_FORCED_THREADING 108 select MODULES_USE_ELF_REL 109 select NEED_DMA_MAP_STATE 110 select OF_EARLY_FLATTREE if OF 111 select OLD_SIGACTION 112 select OLD_SIGSUSPEND3 113 select PCI_SYSCALL if PCI 114 select PERF_USE_VMALLOC 115 select REFCOUNT_FULL 116 select RTC_LIB 117 select SYS_SUPPORTS_APM_EMULATION 118 # Above selects are sorted alphabetically; please add new ones 119 # according to that. Thanks. 120 help 121 The ARM series is a line of low-power-consumption RISC chip designs 122 licensed by ARM Ltd and targeted at embedded applications and 123 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 124 manufactured, but legacy ARM-based PC hardware remains popular in 125 Europe. There is an ARM Linux project with a web page at 126 <http://www.arm.linux.org.uk/>. 127 128config ARM_HAS_SG_CHAIN 129 bool 130 131config ARM_DMA_USE_IOMMU 132 bool 133 select ARM_HAS_SG_CHAIN 134 select NEED_SG_DMA_LENGTH 135 136if ARM_DMA_USE_IOMMU 137 138config ARM_DMA_IOMMU_ALIGNMENT 139 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 140 range 4 9 141 default 8 142 help 143 DMA mapping framework by default aligns all buffers to the smallest 144 PAGE_SIZE order which is greater than or equal to the requested buffer 145 size. This works well for buffers up to a few hundreds kilobytes, but 146 for larger buffers it just a waste of address space. Drivers which has 147 relatively small addressing window (like 64Mib) might run out of 148 virtual space with just a few allocations. 149 150 With this parameter you can specify the maximum PAGE_SIZE order for 151 DMA IOMMU buffers. Larger buffers will be aligned only to this 152 specified order. The order is expressed as a power of two multiplied 153 by the PAGE_SIZE. 154 155endif 156 157config SYS_SUPPORTS_APM_EMULATION 158 bool 159 160config HAVE_TCM 161 bool 162 select GENERIC_ALLOCATOR 163 164config HAVE_PROC_CPU 165 bool 166 167config NO_IOPORT_MAP 168 bool 169 170config SBUS 171 bool 172 173config STACKTRACE_SUPPORT 174 bool 175 default y 176 177config LOCKDEP_SUPPORT 178 bool 179 default y 180 181config TRACE_IRQFLAGS_SUPPORT 182 bool 183 default !CPU_V7M 184 185config ARCH_HAS_ILOG2_U32 186 bool 187 188config ARCH_HAS_ILOG2_U64 189 bool 190 191config ARCH_HAS_BANDGAP 192 bool 193 194config FIX_EARLYCON_MEM 195 def_bool y if MMU 196 197config GENERIC_HWEIGHT 198 bool 199 default y 200 201config GENERIC_CALIBRATE_DELAY 202 bool 203 default y 204 205config ARCH_MAY_HAVE_PC_FDC 206 bool 207 208config ZONE_DMA 209 bool 210 211config ARCH_SUPPORTS_UPROBES 212 def_bool y 213 214config ARCH_HAS_DMA_SET_COHERENT_MASK 215 bool 216 217config GENERIC_ISA_DMA 218 bool 219 220config FIQ 221 bool 222 223config NEED_RET_TO_USER 224 bool 225 226config ARCH_MTD_XIP 227 bool 228 229config ARM_PATCH_PHYS_VIRT 230 bool "Patch physical to virtual translations at runtime" if EMBEDDED 231 default y 232 depends on !XIP_KERNEL && MMU 233 help 234 Patch phys-to-virt and virt-to-phys translation functions at 235 boot and module load time according to the position of the 236 kernel in system memory. 237 238 This can only be used with non-XIP MMU kernels where the base 239 of physical memory is at a 16MB boundary. 240 241 Only disable this option if you know that you do not require 242 this feature (eg, building a kernel for a single machine) and 243 you need to shrink the kernel to the minimal size. 244 245config NEED_MACH_IO_H 246 bool 247 help 248 Select this when mach/io.h is required to provide special 249 definitions for this platform. The need for mach/io.h should 250 be avoided when possible. 251 252config NEED_MACH_MEMORY_H 253 bool 254 help 255 Select this when mach/memory.h is required to provide special 256 definitions for this platform. The need for mach/memory.h should 257 be avoided when possible. 258 259config PHYS_OFFSET 260 hex "Physical address of main memory" if MMU 261 depends on !ARM_PATCH_PHYS_VIRT 262 default DRAM_BASE if !MMU 263 default 0x00000000 if ARCH_EBSA110 || \ 264 ARCH_FOOTBRIDGE || \ 265 ARCH_INTEGRATOR || \ 266 ARCH_IOP13XX || \ 267 ARCH_KS8695 || \ 268 ARCH_REALVIEW 269 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 270 default 0x20000000 if ARCH_S5PV210 271 default 0xc0000000 if ARCH_SA1100 272 help 273 Please provide the physical address corresponding to the 274 location of main memory in your system. 275 276config GENERIC_BUG 277 def_bool y 278 depends on BUG 279 280config PGTABLE_LEVELS 281 int 282 default 3 if ARM_LPAE 283 default 2 284 285menu "System Type" 286 287config MMU 288 bool "MMU-based Paged Memory Management Support" 289 default y 290 help 291 Select if you want MMU-based virtualised addressing space 292 support by paged memory management. If unsure, say 'Y'. 293 294config ARCH_MMAP_RND_BITS_MIN 295 default 8 296 297config ARCH_MMAP_RND_BITS_MAX 298 default 14 if PAGE_OFFSET=0x40000000 299 default 15 if PAGE_OFFSET=0x80000000 300 default 16 301 302# 303# The "ARM system type" choice list is ordered alphabetically by option 304# text. Please add new entries in the option alphabetic order. 305# 306choice 307 prompt "ARM system type" 308 default ARM_SINGLE_ARMV7M if !MMU 309 default ARCH_MULTIPLATFORM if MMU 310 311config ARCH_MULTIPLATFORM 312 bool "Allow multiple platforms to be selected" 313 depends on MMU 314 select ARM_HAS_SG_CHAIN 315 select ARM_PATCH_PHYS_VIRT 316 select AUTO_ZRELADDR 317 select TIMER_OF 318 select COMMON_CLK 319 select GENERIC_CLOCKEVENTS 320 select GENERIC_IRQ_MULTI_HANDLER 321 select HAVE_PCI 322 select PCI_DOMAINS_GENERIC if PCI 323 select SPARSE_IRQ 324 select USE_OF 325 326config ARM_SINGLE_ARMV7M 327 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 328 depends on !MMU 329 select ARM_NVIC 330 select AUTO_ZRELADDR 331 select TIMER_OF 332 select COMMON_CLK 333 select CPU_V7M 334 select GENERIC_CLOCKEVENTS 335 select NO_IOPORT_MAP 336 select SPARSE_IRQ 337 select USE_OF 338 339config ARCH_EBSA110 340 bool "EBSA-110" 341 select ARCH_USES_GETTIMEOFFSET 342 select CPU_SA110 343 select ISA 344 select NEED_MACH_IO_H 345 select NEED_MACH_MEMORY_H 346 select NO_IOPORT_MAP 347 help 348 This is an evaluation board for the StrongARM processor available 349 from Digital. It has limited hardware on-board, including an 350 Ethernet interface, two PCMCIA sockets, two serial ports and a 351 parallel port. 352 353config ARCH_EP93XX 354 bool "EP93xx-based" 355 select ARCH_SPARSEMEM_ENABLE 356 select ARM_AMBA 357 imply ARM_PATCH_PHYS_VIRT 358 select ARM_VIC 359 select AUTO_ZRELADDR 360 select CLKDEV_LOOKUP 361 select CLKSRC_MMIO 362 select CPU_ARM920T 363 select GENERIC_CLOCKEVENTS 364 select GPIOLIB 365 help 366 This enables support for the Cirrus EP93xx series of CPUs. 367 368config ARCH_FOOTBRIDGE 369 bool "FootBridge" 370 select CPU_SA110 371 select FOOTBRIDGE 372 select GENERIC_CLOCKEVENTS 373 select HAVE_IDE 374 select NEED_MACH_IO_H if !MMU 375 select NEED_MACH_MEMORY_H 376 help 377 Support for systems based on the DC21285 companion chip 378 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 379 380config ARCH_NETX 381 bool "Hilscher NetX based" 382 select ARM_VIC 383 select CLKSRC_MMIO 384 select CPU_ARM926T 385 select GENERIC_CLOCKEVENTS 386 help 387 This enables support for systems based on the Hilscher NetX Soc 388 389config ARCH_IOP13XX 390 bool "IOP13xx-based" 391 depends on MMU 392 select CPU_XSC3 393 select NEED_MACH_MEMORY_H 394 select NEED_RET_TO_USER 395 select FORCE_PCI 396 select PLAT_IOP 397 select VMSPLIT_1G 398 select SPARSE_IRQ 399 help 400 Support for Intel's IOP13XX (XScale) family of processors. 401 402config ARCH_IOP32X 403 bool "IOP32x-based" 404 depends on MMU 405 select CPU_XSCALE 406 select GPIO_IOP 407 select GPIOLIB 408 select NEED_RET_TO_USER 409 select FORCE_PCI 410 select PLAT_IOP 411 help 412 Support for Intel's 80219 and IOP32X (XScale) family of 413 processors. 414 415config ARCH_IOP33X 416 bool "IOP33x-based" 417 depends on MMU 418 select CPU_XSCALE 419 select GPIO_IOP 420 select GPIOLIB 421 select NEED_RET_TO_USER 422 select FORCE_PCI 423 select PLAT_IOP 424 help 425 Support for Intel's IOP33X (XScale) family of processors. 426 427config ARCH_IXP4XX 428 bool "IXP4xx-based" 429 depends on MMU 430 select ARCH_HAS_DMA_SET_COHERENT_MASK 431 select ARCH_SUPPORTS_BIG_ENDIAN 432 select CPU_XSCALE 433 select DMABOUNCE if PCI 434 select GENERIC_CLOCKEVENTS 435 select GENERIC_IRQ_MULTI_HANDLER 436 select GPIO_IXP4XX 437 select GPIOLIB 438 select HAVE_PCI 439 select IXP4XX_IRQ 440 select IXP4XX_TIMER 441 select NEED_MACH_IO_H 442 select USB_EHCI_BIG_ENDIAN_DESC 443 select USB_EHCI_BIG_ENDIAN_MMIO 444 help 445 Support for Intel's IXP4XX (XScale) family of processors. 446 447config ARCH_DOVE 448 bool "Marvell Dove" 449 select CPU_PJ4 450 select GENERIC_CLOCKEVENTS 451 select GENERIC_IRQ_MULTI_HANDLER 452 select GPIOLIB 453 select HAVE_PCI 454 select MVEBU_MBUS 455 select PINCTRL 456 select PINCTRL_DOVE 457 select PLAT_ORION_LEGACY 458 select SPARSE_IRQ 459 select PM_GENERIC_DOMAINS if PM 460 help 461 Support for the Marvell Dove SoC 88AP510 462 463config ARCH_KS8695 464 bool "Micrel/Kendin KS8695" 465 select CLKSRC_MMIO 466 select CPU_ARM922T 467 select GENERIC_CLOCKEVENTS 468 select GPIOLIB 469 select NEED_MACH_MEMORY_H 470 help 471 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 472 System-on-Chip devices. 473 474config ARCH_W90X900 475 bool "Nuvoton W90X900 CPU" 476 select CLKDEV_LOOKUP 477 select CLKSRC_MMIO 478 select CPU_ARM926T 479 select GENERIC_CLOCKEVENTS 480 select GPIOLIB 481 help 482 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 483 At present, the w90x900 has been renamed nuc900, regarding 484 the ARM series product line, you can login the following 485 link address to know more. 486 487 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 488 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 489 490config ARCH_LPC32XX 491 bool "NXP LPC32XX" 492 select ARM_AMBA 493 select CLKDEV_LOOKUP 494 select CLKSRC_LPC32XX 495 select COMMON_CLK 496 select CPU_ARM926T 497 select GENERIC_CLOCKEVENTS 498 select GENERIC_IRQ_MULTI_HANDLER 499 select GPIOLIB 500 select SPARSE_IRQ 501 select USE_OF 502 help 503 Support for the NXP LPC32XX family of processors 504 505config ARCH_PXA 506 bool "PXA2xx/PXA3xx-based" 507 depends on MMU 508 select ARCH_MTD_XIP 509 select ARM_CPU_SUSPEND if PM 510 select AUTO_ZRELADDR 511 select COMMON_CLK 512 select CLKDEV_LOOKUP 513 select CLKSRC_PXA 514 select CLKSRC_MMIO 515 select TIMER_OF 516 select CPU_XSCALE if !CPU_XSC3 517 select GENERIC_CLOCKEVENTS 518 select GENERIC_IRQ_MULTI_HANDLER 519 select GPIO_PXA 520 select GPIOLIB 521 select HAVE_IDE 522 select IRQ_DOMAIN 523 select PLAT_PXA 524 select SPARSE_IRQ 525 help 526 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 527 528config ARCH_RPC 529 bool "RiscPC" 530 depends on MMU 531 select ARCH_ACORN 532 select ARCH_MAY_HAVE_PC_FDC 533 select ARCH_SPARSEMEM_ENABLE 534 select ARCH_USES_GETTIMEOFFSET 535 select CPU_SA110 536 select FIQ 537 select HAVE_IDE 538 select HAVE_PATA_PLATFORM 539 select ISA_DMA_API 540 select NEED_MACH_IO_H 541 select NEED_MACH_MEMORY_H 542 select NO_IOPORT_MAP 543 help 544 On the Acorn Risc-PC, Linux can support the internal IDE disk and 545 CD-ROM interface, serial and parallel port, and the floppy drive. 546 547config ARCH_SA1100 548 bool "SA1100-based" 549 select ARCH_MTD_XIP 550 select ARCH_SPARSEMEM_ENABLE 551 select CLKDEV_LOOKUP 552 select CLKSRC_MMIO 553 select CLKSRC_PXA 554 select TIMER_OF if OF 555 select CPU_FREQ 556 select CPU_SA1100 557 select GENERIC_CLOCKEVENTS 558 select GENERIC_IRQ_MULTI_HANDLER 559 select GPIOLIB 560 select HAVE_IDE 561 select IRQ_DOMAIN 562 select ISA 563 select NEED_MACH_MEMORY_H 564 select SPARSE_IRQ 565 help 566 Support for StrongARM 11x0 based boards. 567 568config ARCH_S3C24XX 569 bool "Samsung S3C24XX SoCs" 570 select ATAGS 571 select CLKDEV_LOOKUP 572 select CLKSRC_SAMSUNG_PWM 573 select GENERIC_CLOCKEVENTS 574 select GPIO_SAMSUNG 575 select GPIOLIB 576 select GENERIC_IRQ_MULTI_HANDLER 577 select HAVE_S3C2410_I2C if I2C 578 select HAVE_S3C2410_WATCHDOG if WATCHDOG 579 select HAVE_S3C_RTC if RTC_CLASS 580 select NEED_MACH_IO_H 581 select SAMSUNG_ATAGS 582 select USE_OF 583 help 584 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 585 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 586 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 587 Samsung SMDK2410 development board (and derivatives). 588 589config ARCH_DAVINCI 590 bool "TI DaVinci" 591 select ARCH_HAS_HOLES_MEMORYMODEL 592 select COMMON_CLK 593 select CPU_ARM926T 594 select GENERIC_ALLOCATOR 595 select GENERIC_CLOCKEVENTS 596 select GENERIC_IRQ_CHIP 597 select GENERIC_IRQ_MULTI_HANDLER 598 select GPIOLIB 599 select HAVE_IDE 600 select PM_GENERIC_DOMAINS if PM 601 select PM_GENERIC_DOMAINS_OF if PM && OF 602 select REGMAP_MMIO 603 select RESET_CONTROLLER 604 select SPARSE_IRQ 605 select USE_OF 606 select ZONE_DMA 607 help 608 Support for TI's DaVinci platform. 609 610config ARCH_OMAP1 611 bool "TI OMAP1" 612 depends on MMU 613 select ARCH_HAS_HOLES_MEMORYMODEL 614 select ARCH_OMAP 615 select CLKDEV_LOOKUP 616 select CLKSRC_MMIO 617 select GENERIC_CLOCKEVENTS 618 select GENERIC_IRQ_CHIP 619 select GENERIC_IRQ_MULTI_HANDLER 620 select GPIOLIB 621 select HAVE_IDE 622 select IRQ_DOMAIN 623 select NEED_MACH_IO_H if PCCARD 624 select NEED_MACH_MEMORY_H 625 select SPARSE_IRQ 626 help 627 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 628 629endchoice 630 631menu "Multiple platform selection" 632 depends on ARCH_MULTIPLATFORM 633 634comment "CPU Core family selection" 635 636config ARCH_MULTI_V4 637 bool "ARMv4 based platforms (FA526)" 638 depends on !ARCH_MULTI_V6_V7 639 select ARCH_MULTI_V4_V5 640 select CPU_FA526 641 642config ARCH_MULTI_V4T 643 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 644 depends on !ARCH_MULTI_V6_V7 645 select ARCH_MULTI_V4_V5 646 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 647 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 648 CPU_ARM925T || CPU_ARM940T) 649 650config ARCH_MULTI_V5 651 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 652 depends on !ARCH_MULTI_V6_V7 653 select ARCH_MULTI_V4_V5 654 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 655 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 656 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 657 658config ARCH_MULTI_V4_V5 659 bool 660 661config ARCH_MULTI_V6 662 bool "ARMv6 based platforms (ARM11)" 663 select ARCH_MULTI_V6_V7 664 select CPU_V6K 665 666config ARCH_MULTI_V7 667 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 668 default y 669 select ARCH_MULTI_V6_V7 670 select CPU_V7 671 select HAVE_SMP 672 673config ARCH_MULTI_V6_V7 674 bool 675 select MIGHT_HAVE_CACHE_L2X0 676 677config ARCH_MULTI_CPU_AUTO 678 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 679 select ARCH_MULTI_V5 680 681endmenu 682 683config ARCH_VIRT 684 bool "Dummy Virtual Machine" 685 depends on ARCH_MULTI_V7 686 select ARM_AMBA 687 select ARM_GIC 688 select ARM_GIC_V2M if PCI 689 select ARM_GIC_V3 690 select ARM_GIC_V3_ITS if PCI 691 select ARM_PSCI 692 select HAVE_ARM_ARCH_TIMER 693 select ARCH_SUPPORTS_BIG_ENDIAN 694 695# 696# This is sorted alphabetically by mach-* pathname. However, plat-* 697# Kconfigs may be included either alphabetically (according to the 698# plat- suffix) or along side the corresponding mach-* source. 699# 700source "arch/arm/mach-actions/Kconfig" 701 702source "arch/arm/mach-alpine/Kconfig" 703 704source "arch/arm/mach-artpec/Kconfig" 705 706source "arch/arm/mach-asm9260/Kconfig" 707 708source "arch/arm/mach-aspeed/Kconfig" 709 710source "arch/arm/mach-at91/Kconfig" 711 712source "arch/arm/mach-axxia/Kconfig" 713 714source "arch/arm/mach-bcm/Kconfig" 715 716source "arch/arm/mach-berlin/Kconfig" 717 718source "arch/arm/mach-clps711x/Kconfig" 719 720source "arch/arm/mach-cns3xxx/Kconfig" 721 722source "arch/arm/mach-davinci/Kconfig" 723 724source "arch/arm/mach-digicolor/Kconfig" 725 726source "arch/arm/mach-dove/Kconfig" 727 728source "arch/arm/mach-ep93xx/Kconfig" 729 730source "arch/arm/mach-exynos/Kconfig" 731source "arch/arm/plat-samsung/Kconfig" 732 733source "arch/arm/mach-footbridge/Kconfig" 734 735source "arch/arm/mach-gemini/Kconfig" 736 737source "arch/arm/mach-highbank/Kconfig" 738 739source "arch/arm/mach-hisi/Kconfig" 740 741source "arch/arm/mach-imx/Kconfig" 742 743source "arch/arm/mach-integrator/Kconfig" 744 745source "arch/arm/mach-iop13xx/Kconfig" 746 747source "arch/arm/mach-iop32x/Kconfig" 748 749source "arch/arm/mach-iop33x/Kconfig" 750 751source "arch/arm/mach-ixp4xx/Kconfig" 752 753source "arch/arm/mach-keystone/Kconfig" 754 755source "arch/arm/mach-ks8695/Kconfig" 756 757source "arch/arm/mach-mediatek/Kconfig" 758 759source "arch/arm/mach-meson/Kconfig" 760 761source "arch/arm/mach-milbeaut/Kconfig" 762 763source "arch/arm/mach-mmp/Kconfig" 764 765source "arch/arm/mach-moxart/Kconfig" 766 767source "arch/arm/mach-mv78xx0/Kconfig" 768 769source "arch/arm/mach-mvebu/Kconfig" 770 771source "arch/arm/mach-mxs/Kconfig" 772 773source "arch/arm/mach-netx/Kconfig" 774 775source "arch/arm/mach-nomadik/Kconfig" 776 777source "arch/arm/mach-npcm/Kconfig" 778 779source "arch/arm/mach-nspire/Kconfig" 780 781source "arch/arm/plat-omap/Kconfig" 782 783source "arch/arm/mach-omap1/Kconfig" 784 785source "arch/arm/mach-omap2/Kconfig" 786 787source "arch/arm/mach-orion5x/Kconfig" 788 789source "arch/arm/mach-oxnas/Kconfig" 790 791source "arch/arm/mach-picoxcell/Kconfig" 792 793source "arch/arm/mach-prima2/Kconfig" 794 795source "arch/arm/mach-pxa/Kconfig" 796source "arch/arm/plat-pxa/Kconfig" 797 798source "arch/arm/mach-qcom/Kconfig" 799 800source "arch/arm/mach-rda/Kconfig" 801 802source "arch/arm/mach-realview/Kconfig" 803 804source "arch/arm/mach-rockchip/Kconfig" 805 806source "arch/arm/mach-s3c24xx/Kconfig" 807 808source "arch/arm/mach-s3c64xx/Kconfig" 809 810source "arch/arm/mach-s5pv210/Kconfig" 811 812source "arch/arm/mach-sa1100/Kconfig" 813 814source "arch/arm/mach-shmobile/Kconfig" 815 816source "arch/arm/mach-socfpga/Kconfig" 817 818source "arch/arm/mach-spear/Kconfig" 819 820source "arch/arm/mach-sti/Kconfig" 821 822source "arch/arm/mach-stm32/Kconfig" 823 824source "arch/arm/mach-sunxi/Kconfig" 825 826source "arch/arm/mach-tango/Kconfig" 827 828source "arch/arm/mach-tegra/Kconfig" 829 830source "arch/arm/mach-u300/Kconfig" 831 832source "arch/arm/mach-uniphier/Kconfig" 833 834source "arch/arm/mach-ux500/Kconfig" 835 836source "arch/arm/mach-versatile/Kconfig" 837 838source "arch/arm/mach-vexpress/Kconfig" 839source "arch/arm/plat-versatile/Kconfig" 840 841source "arch/arm/mach-vt8500/Kconfig" 842 843source "arch/arm/mach-w90x900/Kconfig" 844 845source "arch/arm/mach-zx/Kconfig" 846 847source "arch/arm/mach-zynq/Kconfig" 848 849# ARMv7-M architecture 850config ARCH_EFM32 851 bool "Energy Micro efm32" 852 depends on ARM_SINGLE_ARMV7M 853 select GPIOLIB 854 help 855 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 856 processors. 857 858config ARCH_LPC18XX 859 bool "NXP LPC18xx/LPC43xx" 860 depends on ARM_SINGLE_ARMV7M 861 select ARCH_HAS_RESET_CONTROLLER 862 select ARM_AMBA 863 select CLKSRC_LPC32XX 864 select PINCTRL 865 help 866 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 867 high performance microcontrollers. 868 869config ARCH_MPS2 870 bool "ARM MPS2 platform" 871 depends on ARM_SINGLE_ARMV7M 872 select ARM_AMBA 873 select CLKSRC_MPS2 874 help 875 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 876 with a range of available cores like Cortex-M3/M4/M7. 877 878 Please, note that depends which Application Note is used memory map 879 for the platform may vary, so adjustment of RAM base might be needed. 880 881# Definitions to make life easier 882config ARCH_ACORN 883 bool 884 885config PLAT_IOP 886 bool 887 select GENERIC_CLOCKEVENTS 888 889config PLAT_ORION 890 bool 891 select CLKSRC_MMIO 892 select COMMON_CLK 893 select GENERIC_IRQ_CHIP 894 select IRQ_DOMAIN 895 896config PLAT_ORION_LEGACY 897 bool 898 select PLAT_ORION 899 900config PLAT_PXA 901 bool 902 903config PLAT_VERSATILE 904 bool 905 906source "arch/arm/mm/Kconfig" 907 908config IWMMXT 909 bool "Enable iWMMXt support" 910 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 911 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 912 help 913 Enable support for iWMMXt context switching at run time if 914 running on a CPU that supports it. 915 916if !MMU 917source "arch/arm/Kconfig-nommu" 918endif 919 920config PJ4B_ERRATA_4742 921 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 922 depends on CPU_PJ4B && MACH_ARMADA_370 923 default y 924 help 925 When coming out of either a Wait for Interrupt (WFI) or a Wait for 926 Event (WFE) IDLE states, a specific timing sensitivity exists between 927 the retiring WFI/WFE instructions and the newly issued subsequent 928 instructions. This sensitivity can result in a CPU hang scenario. 929 Workaround: 930 The software must insert either a Data Synchronization Barrier (DSB) 931 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 932 instruction 933 934config ARM_ERRATA_326103 935 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 936 depends on CPU_V6 937 help 938 Executing a SWP instruction to read-only memory does not set bit 11 939 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 940 treat the access as a read, preventing a COW from occurring and 941 causing the faulting task to livelock. 942 943config ARM_ERRATA_411920 944 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 945 depends on CPU_V6 || CPU_V6K 946 help 947 Invalidation of the Instruction Cache operation can 948 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 949 It does not affect the MPCore. This option enables the ARM Ltd. 950 recommended workaround. 951 952config ARM_ERRATA_430973 953 bool "ARM errata: Stale prediction on replaced interworking branch" 954 depends on CPU_V7 955 help 956 This option enables the workaround for the 430973 Cortex-A8 957 r1p* erratum. If a code sequence containing an ARM/Thumb 958 interworking branch is replaced with another code sequence at the 959 same virtual address, whether due to self-modifying code or virtual 960 to physical address re-mapping, Cortex-A8 does not recover from the 961 stale interworking branch prediction. This results in Cortex-A8 962 executing the new code sequence in the incorrect ARM or Thumb state. 963 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 964 and also flushes the branch target cache at every context switch. 965 Note that setting specific bits in the ACTLR register may not be 966 available in non-secure mode. 967 968config ARM_ERRATA_458693 969 bool "ARM errata: Processor deadlock when a false hazard is created" 970 depends on CPU_V7 971 depends on !ARCH_MULTIPLATFORM 972 help 973 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 974 erratum. For very specific sequences of memory operations, it is 975 possible for a hazard condition intended for a cache line to instead 976 be incorrectly associated with a different cache line. This false 977 hazard might then cause a processor deadlock. The workaround enables 978 the L1 caching of the NEON accesses and disables the PLD instruction 979 in the ACTLR register. Note that setting specific bits in the ACTLR 980 register may not be available in non-secure mode. 981 982config ARM_ERRATA_460075 983 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 984 depends on CPU_V7 985 depends on !ARCH_MULTIPLATFORM 986 help 987 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 988 erratum. Any asynchronous access to the L2 cache may encounter a 989 situation in which recent store transactions to the L2 cache are lost 990 and overwritten with stale memory contents from external memory. The 991 workaround disables the write-allocate mode for the L2 cache via the 992 ACTLR register. Note that setting specific bits in the ACTLR register 993 may not be available in non-secure mode. 994 995config ARM_ERRATA_742230 996 bool "ARM errata: DMB operation may be faulty" 997 depends on CPU_V7 && SMP 998 depends on !ARCH_MULTIPLATFORM 999 help 1000 This option enables the workaround for the 742230 Cortex-A9 1001 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1002 between two write operations may not ensure the correct visibility 1003 ordering of the two writes. This workaround sets a specific bit in 1004 the diagnostic register of the Cortex-A9 which causes the DMB 1005 instruction to behave as a DSB, ensuring the correct behaviour of 1006 the two writes. 1007 1008config ARM_ERRATA_742231 1009 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1010 depends on CPU_V7 && SMP 1011 depends on !ARCH_MULTIPLATFORM 1012 help 1013 This option enables the workaround for the 742231 Cortex-A9 1014 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1015 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1016 accessing some data located in the same cache line, may get corrupted 1017 data due to bad handling of the address hazard when the line gets 1018 replaced from one of the CPUs at the same time as another CPU is 1019 accessing it. This workaround sets specific bits in the diagnostic 1020 register of the Cortex-A9 which reduces the linefill issuing 1021 capabilities of the processor. 1022 1023config ARM_ERRATA_643719 1024 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1025 depends on CPU_V7 && SMP 1026 default y 1027 help 1028 This option enables the workaround for the 643719 Cortex-A9 (prior to 1029 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1030 register returns zero when it should return one. The workaround 1031 corrects this value, ensuring cache maintenance operations which use 1032 it behave as intended and avoiding data corruption. 1033 1034config ARM_ERRATA_720789 1035 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1036 depends on CPU_V7 1037 help 1038 This option enables the workaround for the 720789 Cortex-A9 (prior to 1039 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1040 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1041 As a consequence of this erratum, some TLB entries which should be 1042 invalidated are not, resulting in an incoherency in the system page 1043 tables. The workaround changes the TLB flushing routines to invalidate 1044 entries regardless of the ASID. 1045 1046config ARM_ERRATA_743622 1047 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1048 depends on CPU_V7 1049 depends on !ARCH_MULTIPLATFORM 1050 help 1051 This option enables the workaround for the 743622 Cortex-A9 1052 (r2p*) erratum. Under very rare conditions, a faulty 1053 optimisation in the Cortex-A9 Store Buffer may lead to data 1054 corruption. This workaround sets a specific bit in the diagnostic 1055 register of the Cortex-A9 which disables the Store Buffer 1056 optimisation, preventing the defect from occurring. This has no 1057 visible impact on the overall performance or power consumption of the 1058 processor. 1059 1060config ARM_ERRATA_751472 1061 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1062 depends on CPU_V7 1063 depends on !ARCH_MULTIPLATFORM 1064 help 1065 This option enables the workaround for the 751472 Cortex-A9 (prior 1066 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1067 completion of a following broadcasted operation if the second 1068 operation is received by a CPU before the ICIALLUIS has completed, 1069 potentially leading to corrupted entries in the cache or TLB. 1070 1071config ARM_ERRATA_754322 1072 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1073 depends on CPU_V7 1074 help 1075 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1076 r3p*) erratum. A speculative memory access may cause a page table walk 1077 which starts prior to an ASID switch but completes afterwards. This 1078 can populate the micro-TLB with a stale entry which may be hit with 1079 the new ASID. This workaround places two dsb instructions in the mm 1080 switching code so that no page table walks can cross the ASID switch. 1081 1082config ARM_ERRATA_754327 1083 bool "ARM errata: no automatic Store Buffer drain" 1084 depends on CPU_V7 && SMP 1085 help 1086 This option enables the workaround for the 754327 Cortex-A9 (prior to 1087 r2p0) erratum. The Store Buffer does not have any automatic draining 1088 mechanism and therefore a livelock may occur if an external agent 1089 continuously polls a memory location waiting to observe an update. 1090 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1091 written polling loops from denying visibility of updates to memory. 1092 1093config ARM_ERRATA_364296 1094 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1095 depends on CPU_V6 1096 help 1097 This options enables the workaround for the 364296 ARM1136 1098 r0p2 erratum (possible cache data corruption with 1099 hit-under-miss enabled). It sets the undocumented bit 31 in 1100 the auxiliary control register and the FI bit in the control 1101 register, thus disabling hit-under-miss without putting the 1102 processor into full low interrupt latency mode. ARM11MPCore 1103 is not affected. 1104 1105config ARM_ERRATA_764369 1106 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1107 depends on CPU_V7 && SMP 1108 help 1109 This option enables the workaround for erratum 764369 1110 affecting Cortex-A9 MPCore with two or more processors (all 1111 current revisions). Under certain timing circumstances, a data 1112 cache line maintenance operation by MVA targeting an Inner 1113 Shareable memory region may fail to proceed up to either the 1114 Point of Coherency or to the Point of Unification of the 1115 system. This workaround adds a DSB instruction before the 1116 relevant cache maintenance functions and sets a specific bit 1117 in the diagnostic control register of the SCU. 1118 1119config ARM_ERRATA_775420 1120 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1121 depends on CPU_V7 1122 help 1123 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1124 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1125 operation aborts with MMU exception, it might cause the processor 1126 to deadlock. This workaround puts DSB before executing ISB if 1127 an abort may occur on cache maintenance. 1128 1129config ARM_ERRATA_798181 1130 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1131 depends on CPU_V7 && SMP 1132 help 1133 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1134 adequately shooting down all use of the old entries. This 1135 option enables the Linux kernel workaround for this erratum 1136 which sends an IPI to the CPUs that are running the same ASID 1137 as the one being invalidated. 1138 1139config ARM_ERRATA_773022 1140 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1141 depends on CPU_V7 1142 help 1143 This option enables the workaround for the 773022 Cortex-A15 1144 (up to r0p4) erratum. In certain rare sequences of code, the 1145 loop buffer may deliver incorrect instructions. This 1146 workaround disables the loop buffer to avoid the erratum. 1147 1148config ARM_ERRATA_818325_852422 1149 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1150 depends on CPU_V7 1151 help 1152 This option enables the workaround for: 1153 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1154 instruction might deadlock. Fixed in r0p1. 1155 - Cortex-A12 852422: Execution of a sequence of instructions might 1156 lead to either a data corruption or a CPU deadlock. Not fixed in 1157 any Cortex-A12 cores yet. 1158 This workaround for all both errata involves setting bit[12] of the 1159 Feature Register. This bit disables an optimisation applied to a 1160 sequence of 2 instructions that use opposing condition codes. 1161 1162config ARM_ERRATA_821420 1163 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1164 depends on CPU_V7 1165 help 1166 This option enables the workaround for the 821420 Cortex-A12 1167 (all revs) erratum. In very rare timing conditions, a sequence 1168 of VMOV to Core registers instructions, for which the second 1169 one is in the shadow of a branch or abort, can lead to a 1170 deadlock when the VMOV instructions are issued out-of-order. 1171 1172config ARM_ERRATA_825619 1173 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1174 depends on CPU_V7 1175 help 1176 This option enables the workaround for the 825619 Cortex-A12 1177 (all revs) erratum. Within rare timing constraints, executing a 1178 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1179 and Device/Strongly-Ordered loads and stores might cause deadlock 1180 1181config ARM_ERRATA_857271 1182 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1183 depends on CPU_V7 1184 help 1185 This option enables the workaround for the 857271 Cortex-A12 1186 (all revs) erratum. Under very rare timing conditions, the CPU might 1187 hang. The workaround is expected to have a < 1% performance impact. 1188 1189config ARM_ERRATA_852421 1190 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1191 depends on CPU_V7 1192 help 1193 This option enables the workaround for the 852421 Cortex-A17 1194 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1195 execution of a DMB ST instruction might fail to properly order 1196 stores from GroupA and stores from GroupB. 1197 1198config ARM_ERRATA_852423 1199 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1200 depends on CPU_V7 1201 help 1202 This option enables the workaround for: 1203 - Cortex-A17 852423: Execution of a sequence of instructions might 1204 lead to either a data corruption or a CPU deadlock. Not fixed in 1205 any Cortex-A17 cores yet. 1206 This is identical to Cortex-A12 erratum 852422. It is a separate 1207 config option from the A12 erratum due to the way errata are checked 1208 for and handled. 1209 1210config ARM_ERRATA_857272 1211 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1212 depends on CPU_V7 1213 help 1214 This option enables the workaround for the 857272 Cortex-A17 erratum. 1215 This erratum is not known to be fixed in any A17 revision. 1216 This is identical to Cortex-A12 erratum 857271. It is a separate 1217 config option from the A12 erratum due to the way errata are checked 1218 for and handled. 1219 1220endmenu 1221 1222source "arch/arm/common/Kconfig" 1223 1224menu "Bus support" 1225 1226config ISA 1227 bool 1228 help 1229 Find out whether you have ISA slots on your motherboard. ISA is the 1230 name of a bus system, i.e. the way the CPU talks to the other stuff 1231 inside your box. Other bus systems are PCI, EISA, MicroChannel 1232 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1233 newer boards don't support it. If you have ISA, say Y, otherwise N. 1234 1235# Select ISA DMA controller support 1236config ISA_DMA 1237 bool 1238 select ISA_DMA_API 1239 1240# Select ISA DMA interface 1241config ISA_DMA_API 1242 bool 1243 1244config PCI_NANOENGINE 1245 bool "BSE nanoEngine PCI support" 1246 depends on SA1100_NANOENGINE 1247 help 1248 Enable PCI on the BSE nanoEngine board. 1249 1250config PCI_HOST_ITE8152 1251 bool 1252 depends on PCI && MACH_ARMCORE 1253 default y 1254 select DMABOUNCE 1255 1256config ARM_ERRATA_814220 1257 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1258 depends on CPU_V7 1259 help 1260 The v7 ARM states that all cache and branch predictor maintenance 1261 operations that do not specify an address execute, relative to 1262 each other, in program order. 1263 However, because of this erratum, an L2 set/way cache maintenance 1264 operation can overtake an L1 set/way cache maintenance operation. 1265 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1266 r0p4, r0p5. 1267 1268endmenu 1269 1270menu "Kernel Features" 1271 1272config HAVE_SMP 1273 bool 1274 help 1275 This option should be selected by machines which have an SMP- 1276 capable CPU. 1277 1278 The only effect of this option is to make the SMP-related 1279 options available to the user for configuration. 1280 1281config SMP 1282 bool "Symmetric Multi-Processing" 1283 depends on CPU_V6K || CPU_V7 1284 depends on GENERIC_CLOCKEVENTS 1285 depends on HAVE_SMP 1286 depends on MMU || ARM_MPU 1287 select IRQ_WORK 1288 help 1289 This enables support for systems with more than one CPU. If you have 1290 a system with only one CPU, say N. If you have a system with more 1291 than one CPU, say Y. 1292 1293 If you say N here, the kernel will run on uni- and multiprocessor 1294 machines, but will use only one CPU of a multiprocessor machine. If 1295 you say Y here, the kernel will run on many, but not all, 1296 uniprocessor machines. On a uniprocessor machine, the kernel 1297 will run faster if you say N here. 1298 1299 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1300 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1301 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1302 1303 If you don't know what to do here, say N. 1304 1305config SMP_ON_UP 1306 bool "Allow booting SMP kernel on uniprocessor systems" 1307 depends on SMP && !XIP_KERNEL && MMU 1308 default y 1309 help 1310 SMP kernels contain instructions which fail on non-SMP processors. 1311 Enabling this option allows the kernel to modify itself to make 1312 these instructions safe. Disabling it allows about 1K of space 1313 savings. 1314 1315 If you don't know what to do here, say Y. 1316 1317config ARM_CPU_TOPOLOGY 1318 bool "Support cpu topology definition" 1319 depends on SMP && CPU_V7 1320 default y 1321 help 1322 Support ARM cpu topology definition. The MPIDR register defines 1323 affinity between processors which is then used to describe the cpu 1324 topology of an ARM System. 1325 1326config SCHED_MC 1327 bool "Multi-core scheduler support" 1328 depends on ARM_CPU_TOPOLOGY 1329 help 1330 Multi-core scheduler support improves the CPU scheduler's decision 1331 making when dealing with multi-core CPU chips at a cost of slightly 1332 increased overhead in some places. If unsure say N here. 1333 1334config SCHED_SMT 1335 bool "SMT scheduler support" 1336 depends on ARM_CPU_TOPOLOGY 1337 help 1338 Improves the CPU scheduler's decision making when dealing with 1339 MultiThreading at a cost of slightly increased overhead in some 1340 places. If unsure say N here. 1341 1342config HAVE_ARM_SCU 1343 bool 1344 help 1345 This option enables support for the ARM snoop control unit 1346 1347config HAVE_ARM_ARCH_TIMER 1348 bool "Architected timer support" 1349 depends on CPU_V7 1350 select ARM_ARCH_TIMER 1351 select GENERIC_CLOCKEVENTS 1352 help 1353 This option enables support for the ARM architected timer 1354 1355config HAVE_ARM_TWD 1356 bool 1357 help 1358 This options enables support for the ARM timer and watchdog unit 1359 1360config MCPM 1361 bool "Multi-Cluster Power Management" 1362 depends on CPU_V7 && SMP 1363 help 1364 This option provides the common power management infrastructure 1365 for (multi-)cluster based systems, such as big.LITTLE based 1366 systems. 1367 1368config MCPM_QUAD_CLUSTER 1369 bool 1370 depends on MCPM 1371 help 1372 To avoid wasting resources unnecessarily, MCPM only supports up 1373 to 2 clusters by default. 1374 Platforms with 3 or 4 clusters that use MCPM must select this 1375 option to allow the additional clusters to be managed. 1376 1377config BIG_LITTLE 1378 bool "big.LITTLE support (Experimental)" 1379 depends on CPU_V7 && SMP 1380 select MCPM 1381 help 1382 This option enables support selections for the big.LITTLE 1383 system architecture. 1384 1385config BL_SWITCHER 1386 bool "big.LITTLE switcher support" 1387 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1388 select CPU_PM 1389 help 1390 The big.LITTLE "switcher" provides the core functionality to 1391 transparently handle transition between a cluster of A15's 1392 and a cluster of A7's in a big.LITTLE system. 1393 1394config BL_SWITCHER_DUMMY_IF 1395 tristate "Simple big.LITTLE switcher user interface" 1396 depends on BL_SWITCHER && DEBUG_KERNEL 1397 help 1398 This is a simple and dummy char dev interface to control 1399 the big.LITTLE switcher core code. It is meant for 1400 debugging purposes only. 1401 1402choice 1403 prompt "Memory split" 1404 depends on MMU 1405 default VMSPLIT_3G 1406 help 1407 Select the desired split between kernel and user memory. 1408 1409 If you are not absolutely sure what you are doing, leave this 1410 option alone! 1411 1412 config VMSPLIT_3G 1413 bool "3G/1G user/kernel split" 1414 config VMSPLIT_3G_OPT 1415 depends on !ARM_LPAE 1416 bool "3G/1G user/kernel split (for full 1G low memory)" 1417 config VMSPLIT_2G 1418 bool "2G/2G user/kernel split" 1419 config VMSPLIT_1G 1420 bool "1G/3G user/kernel split" 1421endchoice 1422 1423config PAGE_OFFSET 1424 hex 1425 default PHYS_OFFSET if !MMU 1426 default 0x40000000 if VMSPLIT_1G 1427 default 0x80000000 if VMSPLIT_2G 1428 default 0xB0000000 if VMSPLIT_3G_OPT 1429 default 0xC0000000 1430 1431config NR_CPUS 1432 int "Maximum number of CPUs (2-32)" 1433 range 2 32 1434 depends on SMP 1435 default "4" 1436 1437config HOTPLUG_CPU 1438 bool "Support for hot-pluggable CPUs" 1439 depends on SMP 1440 select GENERIC_IRQ_MIGRATION 1441 help 1442 Say Y here to experiment with turning CPUs off and on. CPUs 1443 can be controlled through /sys/devices/system/cpu. 1444 1445config ARM_PSCI 1446 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1447 depends on HAVE_ARM_SMCCC 1448 select ARM_PSCI_FW 1449 help 1450 Say Y here if you want Linux to communicate with system firmware 1451 implementing the PSCI specification for CPU-centric power 1452 management operations described in ARM document number ARM DEN 1453 0022A ("Power State Coordination Interface System Software on 1454 ARM processors"). 1455 1456# The GPIO number here must be sorted by descending number. In case of 1457# a multiplatform kernel, we just want the highest value required by the 1458# selected platforms. 1459config ARCH_NR_GPIO 1460 int 1461 default 2048 if ARCH_SOCFPGA 1462 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1463 ARCH_ZYNQ 1464 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1465 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1466 default 416 if ARCH_SUNXI 1467 default 392 if ARCH_U8500 1468 default 352 if ARCH_VT8500 1469 default 288 if ARCH_ROCKCHIP 1470 default 264 if MACH_H4700 1471 default 0 1472 help 1473 Maximum number of GPIOs in the system. 1474 1475 If unsure, leave the default value. 1476 1477config HZ_FIXED 1478 int 1479 default 200 if ARCH_EBSA110 1480 default 128 if SOC_AT91RM9200 1481 default 0 1482 1483choice 1484 depends on HZ_FIXED = 0 1485 prompt "Timer frequency" 1486 1487config HZ_100 1488 bool "100 Hz" 1489 1490config HZ_200 1491 bool "200 Hz" 1492 1493config HZ_250 1494 bool "250 Hz" 1495 1496config HZ_300 1497 bool "300 Hz" 1498 1499config HZ_500 1500 bool "500 Hz" 1501 1502config HZ_1000 1503 bool "1000 Hz" 1504 1505endchoice 1506 1507config HZ 1508 int 1509 default HZ_FIXED if HZ_FIXED != 0 1510 default 100 if HZ_100 1511 default 200 if HZ_200 1512 default 250 if HZ_250 1513 default 300 if HZ_300 1514 default 500 if HZ_500 1515 default 1000 1516 1517config SCHED_HRTICK 1518 def_bool HIGH_RES_TIMERS 1519 1520config THUMB2_KERNEL 1521 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1522 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1523 default y if CPU_THUMBONLY 1524 select ARM_UNWIND 1525 help 1526 By enabling this option, the kernel will be compiled in 1527 Thumb-2 mode. 1528 1529 If unsure, say N. 1530 1531config THUMB2_AVOID_R_ARM_THM_JUMP11 1532 bool "Work around buggy Thumb-2 short branch relocations in gas" 1533 depends on THUMB2_KERNEL && MODULES 1534 default y 1535 help 1536 Various binutils versions can resolve Thumb-2 branches to 1537 locally-defined, preemptible global symbols as short-range "b.n" 1538 branch instructions. 1539 1540 This is a problem, because there's no guarantee the final 1541 destination of the symbol, or any candidate locations for a 1542 trampoline, are within range of the branch. For this reason, the 1543 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1544 relocation in modules at all, and it makes little sense to add 1545 support. 1546 1547 The symptom is that the kernel fails with an "unsupported 1548 relocation" error when loading some modules. 1549 1550 Until fixed tools are available, passing 1551 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1552 code which hits this problem, at the cost of a bit of extra runtime 1553 stack usage in some cases. 1554 1555 The problem is described in more detail at: 1556 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1557 1558 Only Thumb-2 kernels are affected. 1559 1560 Unless you are sure your tools don't have this problem, say Y. 1561 1562config ARM_PATCH_IDIV 1563 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1564 depends on CPU_32v7 && !XIP_KERNEL 1565 default y 1566 help 1567 The ARM compiler inserts calls to __aeabi_idiv() and 1568 __aeabi_uidiv() when it needs to perform division on signed 1569 and unsigned integers. Some v7 CPUs have support for the sdiv 1570 and udiv instructions that can be used to implement those 1571 functions. 1572 1573 Enabling this option allows the kernel to modify itself to 1574 replace the first two instructions of these library functions 1575 with the sdiv or udiv plus "bx lr" instructions when the CPU 1576 it is running on supports them. Typically this will be faster 1577 and less power intensive than running the original library 1578 code to do integer division. 1579 1580config AEABI 1581 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1582 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1583 help 1584 This option allows for the kernel to be compiled using the latest 1585 ARM ABI (aka EABI). This is only useful if you are using a user 1586 space environment that is also compiled with EABI. 1587 1588 Since there are major incompatibilities between the legacy ABI and 1589 EABI, especially with regard to structure member alignment, this 1590 option also changes the kernel syscall calling convention to 1591 disambiguate both ABIs and allow for backward compatibility support 1592 (selected with CONFIG_OABI_COMPAT). 1593 1594 To use this you need GCC version 4.0.0 or later. 1595 1596config OABI_COMPAT 1597 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1598 depends on AEABI && !THUMB2_KERNEL 1599 help 1600 This option preserves the old syscall interface along with the 1601 new (ARM EABI) one. It also provides a compatibility layer to 1602 intercept syscalls that have structure arguments which layout 1603 in memory differs between the legacy ABI and the new ARM EABI 1604 (only for non "thumb" binaries). This option adds a tiny 1605 overhead to all syscalls and produces a slightly larger kernel. 1606 1607 The seccomp filter system will not be available when this is 1608 selected, since there is no way yet to sensibly distinguish 1609 between calling conventions during filtering. 1610 1611 If you know you'll be using only pure EABI user space then you 1612 can say N here. If this option is not selected and you attempt 1613 to execute a legacy ABI binary then the result will be 1614 UNPREDICTABLE (in fact it can be predicted that it won't work 1615 at all). If in doubt say N. 1616 1617config ARCH_HAS_HOLES_MEMORYMODEL 1618 bool 1619 1620config ARCH_SPARSEMEM_ENABLE 1621 bool 1622 1623config ARCH_SPARSEMEM_DEFAULT 1624 def_bool ARCH_SPARSEMEM_ENABLE 1625 1626config HAVE_ARCH_PFN_VALID 1627 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1628 1629config HIGHMEM 1630 bool "High Memory Support" 1631 depends on MMU 1632 help 1633 The address space of ARM processors is only 4 Gigabytes large 1634 and it has to accommodate user address space, kernel address 1635 space as well as some memory mapped IO. That means that, if you 1636 have a large amount of physical memory and/or IO, not all of the 1637 memory can be "permanently mapped" by the kernel. The physical 1638 memory that is not permanently mapped is called "high memory". 1639 1640 Depending on the selected kernel/user memory split, minimum 1641 vmalloc space and actual amount of RAM, you may not need this 1642 option which should result in a slightly faster kernel. 1643 1644 If unsure, say n. 1645 1646config HIGHPTE 1647 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1648 depends on HIGHMEM 1649 default y 1650 help 1651 The VM uses one page of physical memory for each page table. 1652 For systems with a lot of processes, this can use a lot of 1653 precious low memory, eventually leading to low memory being 1654 consumed by page tables. Setting this option will allow 1655 user-space 2nd level page tables to reside in high memory. 1656 1657config CPU_SW_DOMAIN_PAN 1658 bool "Enable use of CPU domains to implement privileged no-access" 1659 depends on MMU && !ARM_LPAE 1660 default y 1661 help 1662 Increase kernel security by ensuring that normal kernel accesses 1663 are unable to access userspace addresses. This can help prevent 1664 use-after-free bugs becoming an exploitable privilege escalation 1665 by ensuring that magic values (such as LIST_POISON) will always 1666 fault when dereferenced. 1667 1668 CPUs with low-vector mappings use a best-efforts implementation. 1669 Their lower 1MB needs to remain accessible for the vectors, but 1670 the remainder of userspace will become appropriately inaccessible. 1671 1672config HW_PERF_EVENTS 1673 def_bool y 1674 depends on ARM_PMU 1675 1676config SYS_SUPPORTS_HUGETLBFS 1677 def_bool y 1678 depends on ARM_LPAE 1679 1680config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1681 def_bool y 1682 depends on ARM_LPAE 1683 1684config ARCH_WANT_GENERAL_HUGETLB 1685 def_bool y 1686 1687config ARM_MODULE_PLTS 1688 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1689 depends on MODULES 1690 default y 1691 help 1692 Allocate PLTs when loading modules so that jumps and calls whose 1693 targets are too far away for their relative offsets to be encoded 1694 in the instructions themselves can be bounced via veneers in the 1695 module's PLT. This allows modules to be allocated in the generic 1696 vmalloc area after the dedicated module memory area has been 1697 exhausted. The modules will use slightly more memory, but after 1698 rounding up to page size, the actual memory footprint is usually 1699 the same. 1700 1701 Disabling this is usually safe for small single-platform 1702 configurations. If unsure, say y. 1703 1704config FORCE_MAX_ZONEORDER 1705 int "Maximum zone order" 1706 default "12" if SOC_AM33XX 1707 default "9" if SA1111 || ARCH_EFM32 1708 default "11" 1709 help 1710 The kernel memory allocator divides physically contiguous memory 1711 blocks into "zones", where each zone is a power of two number of 1712 pages. This option selects the largest power of two that the kernel 1713 keeps in the memory allocator. If you need to allocate very large 1714 blocks of physically contiguous memory, then you may need to 1715 increase this value. 1716 1717 This config option is actually maximum order plus one. For example, 1718 a value of 11 means that the largest free memory block is 2^10 pages. 1719 1720config ALIGNMENT_TRAP 1721 bool 1722 depends on CPU_CP15_MMU 1723 default y if !ARCH_EBSA110 1724 select HAVE_PROC_CPU if PROC_FS 1725 help 1726 ARM processors cannot fetch/store information which is not 1727 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1728 address divisible by 4. On 32-bit ARM processors, these non-aligned 1729 fetch/store instructions will be emulated in software if you say 1730 here, which has a severe performance impact. This is necessary for 1731 correct operation of some network protocols. With an IP-only 1732 configuration it is safe to say N, otherwise say Y. 1733 1734config UACCESS_WITH_MEMCPY 1735 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1736 depends on MMU 1737 default y if CPU_FEROCEON 1738 help 1739 Implement faster copy_to_user and clear_user methods for CPU 1740 cores where a 8-word STM instruction give significantly higher 1741 memory write throughput than a sequence of individual 32bit stores. 1742 1743 A possible side effect is a slight increase in scheduling latency 1744 between threads sharing the same address space if they invoke 1745 such copy operations with large buffers. 1746 1747 However, if the CPU data cache is using a write-allocate mode, 1748 this option is unlikely to provide any performance gain. 1749 1750config SECCOMP 1751 bool 1752 prompt "Enable seccomp to safely compute untrusted bytecode" 1753 ---help--- 1754 This kernel feature is useful for number crunching applications 1755 that may need to compute untrusted bytecode during their 1756 execution. By using pipes or other transports made available to 1757 the process as file descriptors supporting the read/write 1758 syscalls, it's possible to isolate those applications in 1759 their own address space using seccomp. Once seccomp is 1760 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1761 and the task is only allowed to execute a few safe syscalls 1762 defined by each seccomp mode. 1763 1764config PARAVIRT 1765 bool "Enable paravirtualization code" 1766 help 1767 This changes the kernel so it can modify itself when it is run 1768 under a hypervisor, potentially improving performance significantly 1769 over full virtualization. 1770 1771config PARAVIRT_TIME_ACCOUNTING 1772 bool "Paravirtual steal time accounting" 1773 select PARAVIRT 1774 help 1775 Select this option to enable fine granularity task steal time 1776 accounting. Time spent executing other tasks in parallel with 1777 the current vCPU is discounted from the vCPU power. To account for 1778 that, there can be a small performance impact. 1779 1780 If in doubt, say N here. 1781 1782config XEN_DOM0 1783 def_bool y 1784 depends on XEN 1785 1786config XEN 1787 bool "Xen guest support on ARM" 1788 depends on ARM && AEABI && OF 1789 depends on CPU_V7 && !CPU_V6 1790 depends on !GENERIC_ATOMIC64 1791 depends on MMU 1792 select ARCH_DMA_ADDR_T_64BIT 1793 select ARM_PSCI 1794 select SWIOTLB 1795 select SWIOTLB_XEN 1796 select PARAVIRT 1797 help 1798 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1799 1800config STACKPROTECTOR_PER_TASK 1801 bool "Use a unique stack canary value for each task" 1802 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1803 select GCC_PLUGIN_ARM_SSP_PER_TASK 1804 default y 1805 help 1806 Due to the fact that GCC uses an ordinary symbol reference from 1807 which to load the value of the stack canary, this value can only 1808 change at reboot time on SMP systems, and all tasks running in the 1809 kernel's address space are forced to use the same canary value for 1810 the entire duration that the system is up. 1811 1812 Enable this option to switch to a different method that uses a 1813 different canary value for each task. 1814 1815endmenu 1816 1817menu "Boot options" 1818 1819config USE_OF 1820 bool "Flattened Device Tree support" 1821 select IRQ_DOMAIN 1822 select OF 1823 help 1824 Include support for flattened device tree machine descriptions. 1825 1826config ATAGS 1827 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1828 default y 1829 help 1830 This is the traditional way of passing data to the kernel at boot 1831 time. If you are solely relying on the flattened device tree (or 1832 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1833 to remove ATAGS support from your kernel binary. If unsure, 1834 leave this to y. 1835 1836config DEPRECATED_PARAM_STRUCT 1837 bool "Provide old way to pass kernel parameters" 1838 depends on ATAGS 1839 help 1840 This was deprecated in 2001 and announced to live on for 5 years. 1841 Some old boot loaders still use this way. 1842 1843# Compressed boot loader in ROM. Yes, we really want to ask about 1844# TEXT and BSS so we preserve their values in the config files. 1845config ZBOOT_ROM_TEXT 1846 hex "Compressed ROM boot loader base address" 1847 default "0" 1848 help 1849 The physical address at which the ROM-able zImage is to be 1850 placed in the target. Platforms which normally make use of 1851 ROM-able zImage formats normally set this to a suitable 1852 value in their defconfig file. 1853 1854 If ZBOOT_ROM is not enabled, this has no effect. 1855 1856config ZBOOT_ROM_BSS 1857 hex "Compressed ROM boot loader BSS address" 1858 default "0" 1859 help 1860 The base address of an area of read/write memory in the target 1861 for the ROM-able zImage which must be available while the 1862 decompressor is running. It must be large enough to hold the 1863 entire decompressed kernel plus an additional 128 KiB. 1864 Platforms which normally make use of ROM-able zImage formats 1865 normally set this to a suitable value in their defconfig file. 1866 1867 If ZBOOT_ROM is not enabled, this has no effect. 1868 1869config ZBOOT_ROM 1870 bool "Compressed boot loader in ROM/flash" 1871 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1872 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1873 help 1874 Say Y here if you intend to execute your compressed kernel image 1875 (zImage) directly from ROM or flash. If unsure, say N. 1876 1877config ARM_APPENDED_DTB 1878 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1879 depends on OF 1880 help 1881 With this option, the boot code will look for a device tree binary 1882 (DTB) appended to zImage 1883 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1884 1885 This is meant as a backward compatibility convenience for those 1886 systems with a bootloader that can't be upgraded to accommodate 1887 the documented boot protocol using a device tree. 1888 1889 Beware that there is very little in terms of protection against 1890 this option being confused by leftover garbage in memory that might 1891 look like a DTB header after a reboot if no actual DTB is appended 1892 to zImage. Do not leave this option active in a production kernel 1893 if you don't intend to always append a DTB. Proper passing of the 1894 location into r2 of a bootloader provided DTB is always preferable 1895 to this option. 1896 1897config ARM_ATAG_DTB_COMPAT 1898 bool "Supplement the appended DTB with traditional ATAG information" 1899 depends on ARM_APPENDED_DTB 1900 help 1901 Some old bootloaders can't be updated to a DTB capable one, yet 1902 they provide ATAGs with memory configuration, the ramdisk address, 1903 the kernel cmdline string, etc. Such information is dynamically 1904 provided by the bootloader and can't always be stored in a static 1905 DTB. To allow a device tree enabled kernel to be used with such 1906 bootloaders, this option allows zImage to extract the information 1907 from the ATAG list and store it at run time into the appended DTB. 1908 1909choice 1910 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1911 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1912 1913config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1914 bool "Use bootloader kernel arguments if available" 1915 help 1916 Uses the command-line options passed by the boot loader instead of 1917 the device tree bootargs property. If the boot loader doesn't provide 1918 any, the device tree bootargs property will be used. 1919 1920config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1921 bool "Extend with bootloader kernel arguments" 1922 help 1923 The command-line arguments provided by the boot loader will be 1924 appended to the the device tree bootargs property. 1925 1926endchoice 1927 1928config CMDLINE 1929 string "Default kernel command string" 1930 default "" 1931 help 1932 On some architectures (EBSA110 and CATS), there is currently no way 1933 for the boot loader to pass arguments to the kernel. For these 1934 architectures, you should supply some command-line options at build 1935 time by entering them here. As a minimum, you should specify the 1936 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1937 1938choice 1939 prompt "Kernel command line type" if CMDLINE != "" 1940 default CMDLINE_FROM_BOOTLOADER 1941 depends on ATAGS 1942 1943config CMDLINE_FROM_BOOTLOADER 1944 bool "Use bootloader kernel arguments if available" 1945 help 1946 Uses the command-line options passed by the boot loader. If 1947 the boot loader doesn't provide any, the default kernel command 1948 string provided in CMDLINE will be used. 1949 1950config CMDLINE_EXTEND 1951 bool "Extend bootloader kernel arguments" 1952 help 1953 The command-line arguments provided by the boot loader will be 1954 appended to the default kernel command string. 1955 1956config CMDLINE_FORCE 1957 bool "Always use the default kernel command string" 1958 help 1959 Always use the default kernel command string, even if the boot 1960 loader passes other arguments to the kernel. 1961 This is useful if you cannot or don't want to change the 1962 command-line options your boot loader passes to the kernel. 1963endchoice 1964 1965config XIP_KERNEL 1966 bool "Kernel Execute-In-Place from ROM" 1967 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1968 help 1969 Execute-In-Place allows the kernel to run from non-volatile storage 1970 directly addressable by the CPU, such as NOR flash. This saves RAM 1971 space since the text section of the kernel is not loaded from flash 1972 to RAM. Read-write sections, such as the data section and stack, 1973 are still copied to RAM. The XIP kernel is not compressed since 1974 it has to run directly from flash, so it will take more space to 1975 store it. The flash address used to link the kernel object files, 1976 and for storing it, is configuration dependent. Therefore, if you 1977 say Y here, you must know the proper physical address where to 1978 store the kernel image depending on your own flash memory usage. 1979 1980 Also note that the make target becomes "make xipImage" rather than 1981 "make zImage" or "make Image". The final kernel binary to put in 1982 ROM memory will be arch/arm/boot/xipImage. 1983 1984 If unsure, say N. 1985 1986config XIP_PHYS_ADDR 1987 hex "XIP Kernel Physical Location" 1988 depends on XIP_KERNEL 1989 default "0x00080000" 1990 help 1991 This is the physical address in your flash memory the kernel will 1992 be linked for and stored to. This address is dependent on your 1993 own flash usage. 1994 1995config XIP_DEFLATED_DATA 1996 bool "Store kernel .data section compressed in ROM" 1997 depends on XIP_KERNEL 1998 select ZLIB_INFLATE 1999 help 2000 Before the kernel is actually executed, its .data section has to be 2001 copied to RAM from ROM. This option allows for storing that data 2002 in compressed form and decompressed to RAM rather than merely being 2003 copied, saving some precious ROM space. A possible drawback is a 2004 slightly longer boot delay. 2005 2006config KEXEC 2007 bool "Kexec system call (EXPERIMENTAL)" 2008 depends on (!SMP || PM_SLEEP_SMP) 2009 depends on !CPU_V7M 2010 select KEXEC_CORE 2011 help 2012 kexec is a system call that implements the ability to shutdown your 2013 current kernel, and to start another kernel. It is like a reboot 2014 but it is independent of the system firmware. And like a reboot 2015 you can start any kernel with it, not just Linux. 2016 2017 It is an ongoing process to be certain the hardware in a machine 2018 is properly shutdown, so do not be surprised if this code does not 2019 initially work for you. 2020 2021config ATAGS_PROC 2022 bool "Export atags in procfs" 2023 depends on ATAGS && KEXEC 2024 default y 2025 help 2026 Should the atags used to boot the kernel be exported in an "atags" 2027 file in procfs. Useful with kexec. 2028 2029config CRASH_DUMP 2030 bool "Build kdump crash kernel (EXPERIMENTAL)" 2031 help 2032 Generate crash dump after being started by kexec. This should 2033 be normally only set in special crash dump kernels which are 2034 loaded in the main kernel with kexec-tools into a specially 2035 reserved region and then later executed after a crash by 2036 kdump/kexec. The crash dump kernel must be compiled to a 2037 memory address not used by the main kernel 2038 2039 For more details see Documentation/admin-guide/kdump/kdump.rst 2040 2041config AUTO_ZRELADDR 2042 bool "Auto calculation of the decompressed kernel image address" 2043 help 2044 ZRELADDR is the physical address where the decompressed kernel 2045 image will be placed. If AUTO_ZRELADDR is selected, the address 2046 will be determined at run-time by masking the current IP with 2047 0xf8000000. This assumes the zImage being placed in the first 128MB 2048 from start of memory. 2049 2050config EFI_STUB 2051 bool 2052 2053config EFI 2054 bool "UEFI runtime support" 2055 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2056 select UCS2_STRING 2057 select EFI_PARAMS_FROM_FDT 2058 select EFI_STUB 2059 select EFI_ARMSTUB 2060 select EFI_RUNTIME_WRAPPERS 2061 ---help--- 2062 This option provides support for runtime services provided 2063 by UEFI firmware (such as non-volatile variables, realtime 2064 clock, and platform reset). A UEFI stub is also provided to 2065 allow the kernel to be booted as an EFI application. This 2066 is only useful for kernels that may run on systems that have 2067 UEFI firmware. 2068 2069config DMI 2070 bool "Enable support for SMBIOS (DMI) tables" 2071 depends on EFI 2072 default y 2073 help 2074 This enables SMBIOS/DMI feature for systems. 2075 2076 This option is only useful on systems that have UEFI firmware. 2077 However, even with this option, the resultant kernel should 2078 continue to boot on existing non-UEFI platforms. 2079 2080 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2081 i.e., the the practice of identifying the platform via DMI to 2082 decide whether certain workarounds for buggy hardware and/or 2083 firmware need to be enabled. This would require the DMI subsystem 2084 to be enabled much earlier than we do on ARM, which is non-trivial. 2085 2086endmenu 2087 2088menu "CPU Power Management" 2089 2090source "drivers/cpufreq/Kconfig" 2091 2092source "drivers/cpuidle/Kconfig" 2093 2094endmenu 2095 2096menu "Floating point emulation" 2097 2098comment "At least one emulation must be selected" 2099 2100config FPE_NWFPE 2101 bool "NWFPE math emulation" 2102 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2103 ---help--- 2104 Say Y to include the NWFPE floating point emulator in the kernel. 2105 This is necessary to run most binaries. Linux does not currently 2106 support floating point hardware so you need to say Y here even if 2107 your machine has an FPA or floating point co-processor podule. 2108 2109 You may say N here if you are going to load the Acorn FPEmulator 2110 early in the bootup. 2111 2112config FPE_NWFPE_XP 2113 bool "Support extended precision" 2114 depends on FPE_NWFPE 2115 help 2116 Say Y to include 80-bit support in the kernel floating-point 2117 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2118 Note that gcc does not generate 80-bit operations by default, 2119 so in most cases this option only enlarges the size of the 2120 floating point emulator without any good reason. 2121 2122 You almost surely want to say N here. 2123 2124config FPE_FASTFPE 2125 bool "FastFPE math emulation (EXPERIMENTAL)" 2126 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2127 ---help--- 2128 Say Y here to include the FAST floating point emulator in the kernel. 2129 This is an experimental much faster emulator which now also has full 2130 precision for the mantissa. It does not support any exceptions. 2131 It is very simple, and approximately 3-6 times faster than NWFPE. 2132 2133 It should be sufficient for most programs. It may be not suitable 2134 for scientific calculations, but you have to check this for yourself. 2135 If you do not feel you need a faster FP emulation you should better 2136 choose NWFPE. 2137 2138config VFP 2139 bool "VFP-format floating point maths" 2140 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2141 help 2142 Say Y to include VFP support code in the kernel. This is needed 2143 if your hardware includes a VFP unit. 2144 2145 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2146 release notes and additional status information. 2147 2148 Say N if your target does not have VFP hardware. 2149 2150config VFPv3 2151 bool 2152 depends on VFP 2153 default y if CPU_V7 2154 2155config NEON 2156 bool "Advanced SIMD (NEON) Extension support" 2157 depends on VFPv3 && CPU_V7 2158 help 2159 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2160 Extension. 2161 2162config KERNEL_MODE_NEON 2163 bool "Support for NEON in kernel mode" 2164 depends on NEON && AEABI 2165 help 2166 Say Y to include support for NEON in kernel mode. 2167 2168endmenu 2169 2170menu "Power management options" 2171 2172source "kernel/power/Kconfig" 2173 2174config ARCH_SUSPEND_POSSIBLE 2175 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2176 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2177 def_bool y 2178 2179config ARM_CPU_SUSPEND 2180 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2181 depends on ARCH_SUSPEND_POSSIBLE 2182 2183config ARCH_HIBERNATION_POSSIBLE 2184 bool 2185 depends on MMU 2186 default y if ARCH_SUSPEND_POSSIBLE 2187 2188endmenu 2189 2190source "drivers/firmware/Kconfig" 2191 2192if CRYPTO 2193source "arch/arm/crypto/Kconfig" 2194endif 2195 2196source "arch/arm/kvm/Kconfig" 2197