xref: /openbmc/linux/arch/arm/Kconfig (revision 08f3e087)
1# SPDX-License-Identifier: GPL-2.0
2config ARM
3	bool
4	default y
5	select ARCH_32BIT_OFF_T
6	select ARCH_HAS_BINFMT_FLAT
7	select ARCH_HAS_DEBUG_VIRTUAL if MMU
8	select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9	select ARCH_HAS_ELF_RANDOMIZE
10	select ARCH_HAS_FORTIFY_SOURCE
11	select ARCH_HAS_KEEPINITRD
12	select ARCH_HAS_KCOV
13	select ARCH_HAS_MEMBARRIER_SYNC_CORE
14	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16	select ARCH_HAS_PHYS_TO_DMA
17	select ARCH_HAS_SETUP_DMA_OPS
18	select ARCH_HAS_SET_MEMORY
19	select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20	select ARCH_HAS_STRICT_MODULE_RWX if MMU
21	select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
22	select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
23	select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25	select ARCH_HAVE_CUSTOM_GPIO_H
26	select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27	select ARCH_HAS_GCOV_PROFILE_ALL
28	select ARCH_KEEP_MEMBLOCK
29	select ARCH_MIGHT_HAVE_PC_PARPORT
30	select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33	select ARCH_SUPPORTS_ATOMIC_RMW
34	select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35	select ARCH_USE_BUILTIN_BSWAP
36	select ARCH_USE_CMPXCHG_LOCKREF
37	select ARCH_USE_MEMTEST
38	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39	select ARCH_WANT_IPC_PARSE_VERSION
40	select ARCH_WANT_LD_ORPHAN_WARN
41	select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42	select BUILDTIME_TABLE_SORT if MMU
43	select CLONE_BACKWARDS
44	select CPU_PM if SUSPEND || CPU_IDLE
45	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46	select DMA_DECLARE_COHERENT
47	select DMA_GLOBAL_POOL if !MMU
48	select DMA_OPS
49	select DMA_REMAP if MMU
50	select EDAC_SUPPORT
51	select EDAC_ATOMIC_SCRUB
52	select GENERIC_ALLOCATOR
53	select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
54	select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
55	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
56	select GENERIC_IRQ_IPI if SMP
57	select GENERIC_CPU_AUTOPROBE
58	select GENERIC_EARLY_IOREMAP
59	select GENERIC_IDLE_POLL_SETUP
60	select GENERIC_IRQ_PROBE
61	select GENERIC_IRQ_SHOW
62	select GENERIC_IRQ_SHOW_LEVEL
63	select GENERIC_LIB_DEVMEM_IS_ALLOWED
64	select GENERIC_PCI_IOMAP
65	select GENERIC_SCHED_CLOCK
66	select GENERIC_SMP_IDLE_THREAD
67	select HANDLE_DOMAIN_IRQ
68	select HARDIRQS_SW_RESEND
69	select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
70	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
71	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
72	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
73	select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
74	select HAVE_ARCH_MMAP_RND_BITS if MMU
75	select HAVE_ARCH_PFN_VALID
76	select HAVE_ARCH_SECCOMP
77	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
78	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
79	select HAVE_ARCH_TRACEHOOK
80	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
81	select HAVE_ARM_SMCCC if CPU_V7
82	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
83	select HAVE_CONTEXT_TRACKING
84	select HAVE_C_RECORDMCOUNT
85	select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
86	select HAVE_DMA_CONTIGUOUS if MMU
87	select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
88	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
89	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
90	select HAVE_EXIT_THREAD
91	select HAVE_FAST_GUP if ARM_LPAE
92	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
93	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
94	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
95	select HAVE_GCC_PLUGINS
96	select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
97	select HAVE_IRQ_TIME_ACCOUNTING
98	select HAVE_KERNEL_GZIP
99	select HAVE_KERNEL_LZ4
100	select HAVE_KERNEL_LZMA
101	select HAVE_KERNEL_LZO
102	select HAVE_KERNEL_XZ
103	select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
104	select HAVE_KRETPROBES if HAVE_KPROBES
105	select HAVE_MOD_ARCH_SPECIFIC
106	select HAVE_NMI
107	select HAVE_OPTPROBES if !THUMB2_KERNEL
108	select HAVE_PERF_EVENTS
109	select HAVE_PERF_REGS
110	select HAVE_PERF_USER_STACK_DUMP
111	select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
112	select HAVE_REGS_AND_STACK_ACCESS_API
113	select HAVE_RSEQ
114	select HAVE_STACKPROTECTOR
115	select HAVE_SYSCALL_TRACEPOINTS
116	select HAVE_UID16
117	select HAVE_VIRT_CPU_ACCOUNTING_GEN
118	select IRQ_FORCED_THREADING
119	select MODULES_USE_ELF_REL
120	select NEED_DMA_MAP_STATE
121	select OF_EARLY_FLATTREE if OF
122	select OLD_SIGACTION
123	select OLD_SIGSUSPEND3
124	select PCI_SYSCALL if PCI
125	select PERF_USE_VMALLOC
126	select RTC_LIB
127	select SYS_SUPPORTS_APM_EMULATION
128	select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
129	# Above selects are sorted alphabetically; please add new ones
130	# according to that.  Thanks.
131	help
132	  The ARM series is a line of low-power-consumption RISC chip designs
133	  licensed by ARM Ltd and targeted at embedded applications and
134	  handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
135	  manufactured, but legacy ARM-based PC hardware remains popular in
136	  Europe.  There is an ARM Linux project with a web page at
137	  <http://www.arm.linux.org.uk/>.
138
139config ARM_HAS_SG_CHAIN
140	bool
141
142config ARM_DMA_USE_IOMMU
143	bool
144	select ARM_HAS_SG_CHAIN
145	select NEED_SG_DMA_LENGTH
146
147if ARM_DMA_USE_IOMMU
148
149config ARM_DMA_IOMMU_ALIGNMENT
150	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
151	range 4 9
152	default 8
153	help
154	  DMA mapping framework by default aligns all buffers to the smallest
155	  PAGE_SIZE order which is greater than or equal to the requested buffer
156	  size. This works well for buffers up to a few hundreds kilobytes, but
157	  for larger buffers it just a waste of address space. Drivers which has
158	  relatively small addressing window (like 64Mib) might run out of
159	  virtual space with just a few allocations.
160
161	  With this parameter you can specify the maximum PAGE_SIZE order for
162	  DMA IOMMU buffers. Larger buffers will be aligned only to this
163	  specified order. The order is expressed as a power of two multiplied
164	  by the PAGE_SIZE.
165
166endif
167
168config SYS_SUPPORTS_APM_EMULATION
169	bool
170
171config HAVE_TCM
172	bool
173	select GENERIC_ALLOCATOR
174
175config HAVE_PROC_CPU
176	bool
177
178config NO_IOPORT_MAP
179	bool
180
181config SBUS
182	bool
183
184config STACKTRACE_SUPPORT
185	bool
186	default y
187
188config LOCKDEP_SUPPORT
189	bool
190	default y
191
192config ARCH_HAS_ILOG2_U32
193	bool
194
195config ARCH_HAS_ILOG2_U64
196	bool
197
198config ARCH_HAS_BANDGAP
199	bool
200
201config FIX_EARLYCON_MEM
202	def_bool y if MMU
203
204config GENERIC_HWEIGHT
205	bool
206	default y
207
208config GENERIC_CALIBRATE_DELAY
209	bool
210	default y
211
212config ARCH_MAY_HAVE_PC_FDC
213	bool
214
215config ARCH_SUPPORTS_UPROBES
216	def_bool y
217
218config ARCH_HAS_DMA_SET_COHERENT_MASK
219	bool
220
221config GENERIC_ISA_DMA
222	bool
223
224config FIQ
225	bool
226
227config NEED_RET_TO_USER
228	bool
229
230config ARCH_MTD_XIP
231	bool
232
233config ARM_PATCH_PHYS_VIRT
234	bool "Patch physical to virtual translations at runtime" if EMBEDDED
235	default y
236	depends on !XIP_KERNEL && MMU
237	help
238	  Patch phys-to-virt and virt-to-phys translation functions at
239	  boot and module load time according to the position of the
240	  kernel in system memory.
241
242	  This can only be used with non-XIP MMU kernels where the base
243	  of physical memory is at a 2 MiB boundary.
244
245	  Only disable this option if you know that you do not require
246	  this feature (eg, building a kernel for a single machine) and
247	  you need to shrink the kernel to the minimal size.
248
249config NEED_MACH_IO_H
250	bool
251	help
252	  Select this when mach/io.h is required to provide special
253	  definitions for this platform.  The need for mach/io.h should
254	  be avoided when possible.
255
256config NEED_MACH_MEMORY_H
257	bool
258	help
259	  Select this when mach/memory.h is required to provide special
260	  definitions for this platform.  The need for mach/memory.h should
261	  be avoided when possible.
262
263config PHYS_OFFSET
264	hex "Physical address of main memory" if MMU
265	depends on !ARM_PATCH_PHYS_VIRT
266	default DRAM_BASE if !MMU
267	default 0x00000000 if ARCH_FOOTBRIDGE
268	default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269	default 0x20000000 if ARCH_S5PV210
270	default 0xc0000000 if ARCH_SA1100
271	help
272	  Please provide the physical address corresponding to the
273	  location of main memory in your system.
274
275config GENERIC_BUG
276	def_bool y
277	depends on BUG
278
279config PGTABLE_LEVELS
280	int
281	default 3 if ARM_LPAE
282	default 2
283
284menu "System Type"
285
286config MMU
287	bool "MMU-based Paged Memory Management Support"
288	default y
289	help
290	  Select if you want MMU-based virtualised addressing space
291	  support by paged memory management. If unsure, say 'Y'.
292
293config ARCH_MMAP_RND_BITS_MIN
294	default 8
295
296config ARCH_MMAP_RND_BITS_MAX
297	default 14 if PAGE_OFFSET=0x40000000
298	default 15 if PAGE_OFFSET=0x80000000
299	default 16
300
301#
302# The "ARM system type" choice list is ordered alphabetically by option
303# text.  Please add new entries in the option alphabetic order.
304#
305choice
306	prompt "ARM system type"
307	default ARM_SINGLE_ARMV7M if !MMU
308	default ARCH_MULTIPLATFORM if MMU
309
310config ARCH_MULTIPLATFORM
311	bool "Allow multiple platforms to be selected"
312	depends on MMU
313	select ARCH_FLATMEM_ENABLE
314	select ARCH_SPARSEMEM_ENABLE
315	select ARCH_SELECT_MEMORY_MODEL
316	select ARM_HAS_SG_CHAIN
317	select ARM_PATCH_PHYS_VIRT
318	select AUTO_ZRELADDR
319	select TIMER_OF
320	select COMMON_CLK
321	select GENERIC_IRQ_MULTI_HANDLER
322	select HAVE_PCI
323	select PCI_DOMAINS_GENERIC if PCI
324	select SPARSE_IRQ
325	select USE_OF
326
327config ARM_SINGLE_ARMV7M
328	bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
329	depends on !MMU
330	select ARM_NVIC
331	select AUTO_ZRELADDR
332	select TIMER_OF
333	select COMMON_CLK
334	select CPU_V7M
335	select NO_IOPORT_MAP
336	select SPARSE_IRQ
337	select USE_OF
338
339config ARCH_EP93XX
340	bool "EP93xx-based"
341	select ARCH_SPARSEMEM_ENABLE
342	select ARM_AMBA
343	imply ARM_PATCH_PHYS_VIRT
344	select ARM_VIC
345	select GENERIC_IRQ_MULTI_HANDLER
346	select AUTO_ZRELADDR
347	select CLKSRC_MMIO
348	select CPU_ARM920T
349	select GPIOLIB
350	select HAVE_LEGACY_CLK
351	help
352	  This enables support for the Cirrus EP93xx series of CPUs.
353
354config ARCH_FOOTBRIDGE
355	bool "FootBridge"
356	select CPU_SA110
357	select FOOTBRIDGE
358	select NEED_MACH_IO_H if !MMU
359	select NEED_MACH_MEMORY_H
360	help
361	  Support for systems based on the DC21285 companion chip
362	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
363
364config ARCH_IOP32X
365	bool "IOP32x-based"
366	depends on MMU
367	select CPU_XSCALE
368	select GPIO_IOP
369	select GPIOLIB
370	select NEED_RET_TO_USER
371	select FORCE_PCI
372	select PLAT_IOP
373	help
374	  Support for Intel's 80219 and IOP32X (XScale) family of
375	  processors.
376
377config ARCH_IXP4XX
378	bool "IXP4xx-based"
379	depends on MMU
380	select ARCH_HAS_DMA_SET_COHERENT_MASK
381	select ARCH_SUPPORTS_BIG_ENDIAN
382	select CPU_XSCALE
383	select DMABOUNCE if PCI
384	select GENERIC_IRQ_MULTI_HANDLER
385	select GPIO_IXP4XX
386	select GPIOLIB
387	select HAVE_PCI
388	select IXP4XX_IRQ
389	select IXP4XX_TIMER
390	# With the new PCI driver this is not needed
391	select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
392	select USB_EHCI_BIG_ENDIAN_DESC
393	select USB_EHCI_BIG_ENDIAN_MMIO
394	help
395	  Support for Intel's IXP4XX (XScale) family of processors.
396
397config ARCH_DOVE
398	bool "Marvell Dove"
399	select CPU_PJ4
400	select GENERIC_IRQ_MULTI_HANDLER
401	select GPIOLIB
402	select HAVE_PCI
403	select MVEBU_MBUS
404	select PINCTRL
405	select PINCTRL_DOVE
406	select PLAT_ORION_LEGACY
407	select SPARSE_IRQ
408	select PM_GENERIC_DOMAINS if PM
409	help
410	  Support for the Marvell Dove SoC 88AP510
411
412config ARCH_PXA
413	bool "PXA2xx/PXA3xx-based"
414	depends on MMU
415	select ARCH_MTD_XIP
416	select ARM_CPU_SUSPEND if PM
417	select AUTO_ZRELADDR
418	select COMMON_CLK
419	select CLKSRC_PXA
420	select CLKSRC_MMIO
421	select TIMER_OF
422	select CPU_XSCALE if !CPU_XSC3
423	select GENERIC_IRQ_MULTI_HANDLER
424	select GPIO_PXA
425	select GPIOLIB
426	select IRQ_DOMAIN
427	select PLAT_PXA
428	select SPARSE_IRQ
429	help
430	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
431
432config ARCH_RPC
433	bool "RiscPC"
434	depends on MMU
435	select ARCH_ACORN
436	select ARCH_MAY_HAVE_PC_FDC
437	select ARCH_SPARSEMEM_ENABLE
438	select ARM_HAS_SG_CHAIN
439	select CPU_SA110
440	select FIQ
441	select HAVE_PATA_PLATFORM
442	select ISA_DMA_API
443	select LEGACY_TIMER_TICK
444	select NEED_MACH_IO_H
445	select NEED_MACH_MEMORY_H
446	select NO_IOPORT_MAP
447	help
448	  On the Acorn Risc-PC, Linux can support the internal IDE disk and
449	  CD-ROM interface, serial and parallel port, and the floppy drive.
450
451config ARCH_SA1100
452	bool "SA1100-based"
453	select ARCH_MTD_XIP
454	select ARCH_SPARSEMEM_ENABLE
455	select CLKSRC_MMIO
456	select CLKSRC_PXA
457	select TIMER_OF if OF
458	select COMMON_CLK
459	select CPU_FREQ
460	select CPU_SA1100
461	select GENERIC_IRQ_MULTI_HANDLER
462	select GPIOLIB
463	select IRQ_DOMAIN
464	select ISA
465	select NEED_MACH_MEMORY_H
466	select SPARSE_IRQ
467	help
468	  Support for StrongARM 11x0 based boards.
469
470config ARCH_S3C24XX
471	bool "Samsung S3C24XX SoCs"
472	select ATAGS
473	select CLKSRC_SAMSUNG_PWM
474	select GPIO_SAMSUNG
475	select GPIOLIB
476	select GENERIC_IRQ_MULTI_HANDLER
477	select HAVE_S3C2410_I2C if I2C
478	select HAVE_S3C_RTC if RTC_CLASS
479	select NEED_MACH_IO_H
480	select S3C2410_WATCHDOG
481	select SAMSUNG_ATAGS
482	select USE_OF
483	select WATCHDOG
484	help
485	  Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
486	  and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
487	  (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
488	  Samsung SMDK2410 development board (and derivatives).
489
490config ARCH_OMAP1
491	bool "TI OMAP1"
492	depends on MMU
493	select ARCH_OMAP
494	select CLKSRC_MMIO
495	select GENERIC_IRQ_CHIP
496	select GENERIC_IRQ_MULTI_HANDLER
497	select GPIOLIB
498	select HAVE_LEGACY_CLK
499	select IRQ_DOMAIN
500	select NEED_MACH_IO_H if PCCARD
501	select NEED_MACH_MEMORY_H
502	select SPARSE_IRQ
503	help
504	  Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
505
506endchoice
507
508menu "Multiple platform selection"
509	depends on ARCH_MULTIPLATFORM
510
511comment "CPU Core family selection"
512
513config ARCH_MULTI_V4
514	bool "ARMv4 based platforms (FA526)"
515	depends on !ARCH_MULTI_V6_V7
516	select ARCH_MULTI_V4_V5
517	select CPU_FA526
518
519config ARCH_MULTI_V4T
520	bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
521	depends on !ARCH_MULTI_V6_V7
522	select ARCH_MULTI_V4_V5
523	select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
524		CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
525		CPU_ARM925T || CPU_ARM940T)
526
527config ARCH_MULTI_V5
528	bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
529	depends on !ARCH_MULTI_V6_V7
530	select ARCH_MULTI_V4_V5
531	select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
532		CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
533		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
534
535config ARCH_MULTI_V4_V5
536	bool
537
538config ARCH_MULTI_V6
539	bool "ARMv6 based platforms (ARM11)"
540	select ARCH_MULTI_V6_V7
541	select CPU_V6K
542
543config ARCH_MULTI_V7
544	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
545	default y
546	select ARCH_MULTI_V6_V7
547	select CPU_V7
548	select HAVE_SMP
549
550config ARCH_MULTI_V6_V7
551	bool
552	select MIGHT_HAVE_CACHE_L2X0
553
554config ARCH_MULTI_CPU_AUTO
555	def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
556	select ARCH_MULTI_V5
557
558endmenu
559
560config ARCH_VIRT
561	bool "Dummy Virtual Machine"
562	depends on ARCH_MULTI_V7
563	select ARM_AMBA
564	select ARM_GIC
565	select ARM_GIC_V2M if PCI
566	select ARM_GIC_V3
567	select ARM_GIC_V3_ITS if PCI
568	select ARM_PSCI
569	select HAVE_ARM_ARCH_TIMER
570	select ARCH_SUPPORTS_BIG_ENDIAN
571
572#
573# This is sorted alphabetically by mach-* pathname.  However, plat-*
574# Kconfigs may be included either alphabetically (according to the
575# plat- suffix) or along side the corresponding mach-* source.
576#
577source "arch/arm/mach-actions/Kconfig"
578
579source "arch/arm/mach-alpine/Kconfig"
580
581source "arch/arm/mach-artpec/Kconfig"
582
583source "arch/arm/mach-asm9260/Kconfig"
584
585source "arch/arm/mach-aspeed/Kconfig"
586
587source "arch/arm/mach-at91/Kconfig"
588
589source "arch/arm/mach-axxia/Kconfig"
590
591source "arch/arm/mach-bcm/Kconfig"
592
593source "arch/arm/mach-berlin/Kconfig"
594
595source "arch/arm/mach-clps711x/Kconfig"
596
597source "arch/arm/mach-cns3xxx/Kconfig"
598
599source "arch/arm/mach-davinci/Kconfig"
600
601source "arch/arm/mach-digicolor/Kconfig"
602
603source "arch/arm/mach-dove/Kconfig"
604
605source "arch/arm/mach-ep93xx/Kconfig"
606
607source "arch/arm/mach-exynos/Kconfig"
608
609source "arch/arm/mach-footbridge/Kconfig"
610
611source "arch/arm/mach-gemini/Kconfig"
612
613source "arch/arm/mach-highbank/Kconfig"
614
615source "arch/arm/mach-hisi/Kconfig"
616
617source "arch/arm/mach-imx/Kconfig"
618
619source "arch/arm/mach-integrator/Kconfig"
620
621source "arch/arm/mach-iop32x/Kconfig"
622
623source "arch/arm/mach-ixp4xx/Kconfig"
624
625source "arch/arm/mach-keystone/Kconfig"
626
627source "arch/arm/mach-lpc32xx/Kconfig"
628
629source "arch/arm/mach-mediatek/Kconfig"
630
631source "arch/arm/mach-meson/Kconfig"
632
633source "arch/arm/mach-milbeaut/Kconfig"
634
635source "arch/arm/mach-mmp/Kconfig"
636
637source "arch/arm/mach-moxart/Kconfig"
638
639source "arch/arm/mach-mstar/Kconfig"
640
641source "arch/arm/mach-mv78xx0/Kconfig"
642
643source "arch/arm/mach-mvebu/Kconfig"
644
645source "arch/arm/mach-mxs/Kconfig"
646
647source "arch/arm/mach-nomadik/Kconfig"
648
649source "arch/arm/mach-npcm/Kconfig"
650
651source "arch/arm/mach-nspire/Kconfig"
652
653source "arch/arm/plat-omap/Kconfig"
654
655source "arch/arm/mach-omap1/Kconfig"
656
657source "arch/arm/mach-omap2/Kconfig"
658
659source "arch/arm/mach-orion5x/Kconfig"
660
661source "arch/arm/mach-oxnas/Kconfig"
662
663source "arch/arm/mach-pxa/Kconfig"
664source "arch/arm/plat-pxa/Kconfig"
665
666source "arch/arm/mach-qcom/Kconfig"
667
668source "arch/arm/mach-rda/Kconfig"
669
670source "arch/arm/mach-realtek/Kconfig"
671
672source "arch/arm/mach-realview/Kconfig"
673
674source "arch/arm/mach-rockchip/Kconfig"
675
676source "arch/arm/mach-s3c/Kconfig"
677
678source "arch/arm/mach-s5pv210/Kconfig"
679
680source "arch/arm/mach-sa1100/Kconfig"
681
682source "arch/arm/mach-shmobile/Kconfig"
683
684source "arch/arm/mach-socfpga/Kconfig"
685
686source "arch/arm/mach-spear/Kconfig"
687
688source "arch/arm/mach-sti/Kconfig"
689
690source "arch/arm/mach-stm32/Kconfig"
691
692source "arch/arm/mach-sunxi/Kconfig"
693
694source "arch/arm/mach-tegra/Kconfig"
695
696source "arch/arm/mach-uniphier/Kconfig"
697
698source "arch/arm/mach-ux500/Kconfig"
699
700source "arch/arm/mach-versatile/Kconfig"
701
702source "arch/arm/mach-vexpress/Kconfig"
703
704source "arch/arm/mach-vt8500/Kconfig"
705
706source "arch/arm/mach-zynq/Kconfig"
707
708# ARMv7-M architecture
709config ARCH_LPC18XX
710	bool "NXP LPC18xx/LPC43xx"
711	depends on ARM_SINGLE_ARMV7M
712	select ARCH_HAS_RESET_CONTROLLER
713	select ARM_AMBA
714	select CLKSRC_LPC32XX
715	select PINCTRL
716	help
717	  Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
718	  high performance microcontrollers.
719
720config ARCH_MPS2
721	bool "ARM MPS2 platform"
722	depends on ARM_SINGLE_ARMV7M
723	select ARM_AMBA
724	select CLKSRC_MPS2
725	help
726	  Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
727	  with a range of available cores like Cortex-M3/M4/M7.
728
729	  Please, note that depends which Application Note is used memory map
730	  for the platform may vary, so adjustment of RAM base might be needed.
731
732# Definitions to make life easier
733config ARCH_ACORN
734	bool
735
736config PLAT_IOP
737	bool
738
739config PLAT_ORION
740	bool
741	select CLKSRC_MMIO
742	select COMMON_CLK
743	select GENERIC_IRQ_CHIP
744	select IRQ_DOMAIN
745
746config PLAT_ORION_LEGACY
747	bool
748	select PLAT_ORION
749
750config PLAT_PXA
751	bool
752
753config PLAT_VERSATILE
754	bool
755
756source "arch/arm/mm/Kconfig"
757
758config IWMMXT
759	bool "Enable iWMMXt support"
760	depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
761	default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
762	help
763	  Enable support for iWMMXt context switching at run time if
764	  running on a CPU that supports it.
765
766if !MMU
767source "arch/arm/Kconfig-nommu"
768endif
769
770config PJ4B_ERRATA_4742
771	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
772	depends on CPU_PJ4B && MACH_ARMADA_370
773	default y
774	help
775	  When coming out of either a Wait for Interrupt (WFI) or a Wait for
776	  Event (WFE) IDLE states, a specific timing sensitivity exists between
777	  the retiring WFI/WFE instructions and the newly issued subsequent
778	  instructions.  This sensitivity can result in a CPU hang scenario.
779	  Workaround:
780	  The software must insert either a Data Synchronization Barrier (DSB)
781	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE
782	  instruction
783
784config ARM_ERRATA_326103
785	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
786	depends on CPU_V6
787	help
788	  Executing a SWP instruction to read-only memory does not set bit 11
789	  of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
790	  treat the access as a read, preventing a COW from occurring and
791	  causing the faulting task to livelock.
792
793config ARM_ERRATA_411920
794	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
795	depends on CPU_V6 || CPU_V6K
796	help
797	  Invalidation of the Instruction Cache operation can
798	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
799	  It does not affect the MPCore. This option enables the ARM Ltd.
800	  recommended workaround.
801
802config ARM_ERRATA_430973
803	bool "ARM errata: Stale prediction on replaced interworking branch"
804	depends on CPU_V7
805	help
806	  This option enables the workaround for the 430973 Cortex-A8
807	  r1p* erratum. If a code sequence containing an ARM/Thumb
808	  interworking branch is replaced with another code sequence at the
809	  same virtual address, whether due to self-modifying code or virtual
810	  to physical address re-mapping, Cortex-A8 does not recover from the
811	  stale interworking branch prediction. This results in Cortex-A8
812	  executing the new code sequence in the incorrect ARM or Thumb state.
813	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
814	  and also flushes the branch target cache at every context switch.
815	  Note that setting specific bits in the ACTLR register may not be
816	  available in non-secure mode.
817
818config ARM_ERRATA_458693
819	bool "ARM errata: Processor deadlock when a false hazard is created"
820	depends on CPU_V7
821	depends on !ARCH_MULTIPLATFORM
822	help
823	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)
824	  erratum. For very specific sequences of memory operations, it is
825	  possible for a hazard condition intended for a cache line to instead
826	  be incorrectly associated with a different cache line. This false
827	  hazard might then cause a processor deadlock. The workaround enables
828	  the L1 caching of the NEON accesses and disables the PLD instruction
829	  in the ACTLR register. Note that setting specific bits in the ACTLR
830	  register may not be available in non-secure mode.
831
832config ARM_ERRATA_460075
833	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
834	depends on CPU_V7
835	depends on !ARCH_MULTIPLATFORM
836	help
837	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)
838	  erratum. Any asynchronous access to the L2 cache may encounter a
839	  situation in which recent store transactions to the L2 cache are lost
840	  and overwritten with stale memory contents from external memory. The
841	  workaround disables the write-allocate mode for the L2 cache via the
842	  ACTLR register. Note that setting specific bits in the ACTLR register
843	  may not be available in non-secure mode.
844
845config ARM_ERRATA_742230
846	bool "ARM errata: DMB operation may be faulty"
847	depends on CPU_V7 && SMP
848	depends on !ARCH_MULTIPLATFORM
849	help
850	  This option enables the workaround for the 742230 Cortex-A9
851	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
852	  between two write operations may not ensure the correct visibility
853	  ordering of the two writes. This workaround sets a specific bit in
854	  the diagnostic register of the Cortex-A9 which causes the DMB
855	  instruction to behave as a DSB, ensuring the correct behaviour of
856	  the two writes.
857
858config ARM_ERRATA_742231
859	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
860	depends on CPU_V7 && SMP
861	depends on !ARCH_MULTIPLATFORM
862	help
863	  This option enables the workaround for the 742231 Cortex-A9
864	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
865	  Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
866	  accessing some data located in the same cache line, may get corrupted
867	  data due to bad handling of the address hazard when the line gets
868	  replaced from one of the CPUs at the same time as another CPU is
869	  accessing it. This workaround sets specific bits in the diagnostic
870	  register of the Cortex-A9 which reduces the linefill issuing
871	  capabilities of the processor.
872
873config ARM_ERRATA_643719
874	bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
875	depends on CPU_V7 && SMP
876	default y
877	help
878	  This option enables the workaround for the 643719 Cortex-A9 (prior to
879	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
880	  register returns zero when it should return one. The workaround
881	  corrects this value, ensuring cache maintenance operations which use
882	  it behave as intended and avoiding data corruption.
883
884config ARM_ERRATA_720789
885	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
886	depends on CPU_V7
887	help
888	  This option enables the workaround for the 720789 Cortex-A9 (prior to
889	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
890	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
891	  As a consequence of this erratum, some TLB entries which should be
892	  invalidated are not, resulting in an incoherency in the system page
893	  tables. The workaround changes the TLB flushing routines to invalidate
894	  entries regardless of the ASID.
895
896config ARM_ERRATA_743622
897	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
898	depends on CPU_V7
899	depends on !ARCH_MULTIPLATFORM
900	help
901	  This option enables the workaround for the 743622 Cortex-A9
902	  (r2p*) erratum. Under very rare conditions, a faulty
903	  optimisation in the Cortex-A9 Store Buffer may lead to data
904	  corruption. This workaround sets a specific bit in the diagnostic
905	  register of the Cortex-A9 which disables the Store Buffer
906	  optimisation, preventing the defect from occurring. This has no
907	  visible impact on the overall performance or power consumption of the
908	  processor.
909
910config ARM_ERRATA_751472
911	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
912	depends on CPU_V7
913	depends on !ARCH_MULTIPLATFORM
914	help
915	  This option enables the workaround for the 751472 Cortex-A9 (prior
916	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
917	  completion of a following broadcasted operation if the second
918	  operation is received by a CPU before the ICIALLUIS has completed,
919	  potentially leading to corrupted entries in the cache or TLB.
920
921config ARM_ERRATA_754322
922	bool "ARM errata: possible faulty MMU translations following an ASID switch"
923	depends on CPU_V7
924	help
925	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,
926	  r3p*) erratum. A speculative memory access may cause a page table walk
927	  which starts prior to an ASID switch but completes afterwards. This
928	  can populate the micro-TLB with a stale entry which may be hit with
929	  the new ASID. This workaround places two dsb instructions in the mm
930	  switching code so that no page table walks can cross the ASID switch.
931
932config ARM_ERRATA_754327
933	bool "ARM errata: no automatic Store Buffer drain"
934	depends on CPU_V7 && SMP
935	help
936	  This option enables the workaround for the 754327 Cortex-A9 (prior to
937	  r2p0) erratum. The Store Buffer does not have any automatic draining
938	  mechanism and therefore a livelock may occur if an external agent
939	  continuously polls a memory location waiting to observe an update.
940	  This workaround defines cpu_relax() as smp_mb(), preventing correctly
941	  written polling loops from denying visibility of updates to memory.
942
943config ARM_ERRATA_364296
944	bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
945	depends on CPU_V6
946	help
947	  This options enables the workaround for the 364296 ARM1136
948	  r0p2 erratum (possible cache data corruption with
949	  hit-under-miss enabled). It sets the undocumented bit 31 in
950	  the auxiliary control register and the FI bit in the control
951	  register, thus disabling hit-under-miss without putting the
952	  processor into full low interrupt latency mode. ARM11MPCore
953	  is not affected.
954
955config ARM_ERRATA_764369
956	bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
957	depends on CPU_V7 && SMP
958	help
959	  This option enables the workaround for erratum 764369
960	  affecting Cortex-A9 MPCore with two or more processors (all
961	  current revisions). Under certain timing circumstances, a data
962	  cache line maintenance operation by MVA targeting an Inner
963	  Shareable memory region may fail to proceed up to either the
964	  Point of Coherency or to the Point of Unification of the
965	  system. This workaround adds a DSB instruction before the
966	  relevant cache maintenance functions and sets a specific bit
967	  in the diagnostic control register of the SCU.
968
969config ARM_ERRATA_775420
970       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
971       depends on CPU_V7
972       help
973	 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
974	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
975	 operation aborts with MMU exception, it might cause the processor
976	 to deadlock. This workaround puts DSB before executing ISB if
977	 an abort may occur on cache maintenance.
978
979config ARM_ERRATA_798181
980	bool "ARM errata: TLBI/DSB failure on Cortex-A15"
981	depends on CPU_V7 && SMP
982	help
983	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
984	  adequately shooting down all use of the old entries. This
985	  option enables the Linux kernel workaround for this erratum
986	  which sends an IPI to the CPUs that are running the same ASID
987	  as the one being invalidated.
988
989config ARM_ERRATA_773022
990	bool "ARM errata: incorrect instructions may be executed from loop buffer"
991	depends on CPU_V7
992	help
993	  This option enables the workaround for the 773022 Cortex-A15
994	  (up to r0p4) erratum. In certain rare sequences of code, the
995	  loop buffer may deliver incorrect instructions. This
996	  workaround disables the loop buffer to avoid the erratum.
997
998config ARM_ERRATA_818325_852422
999	bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1000	depends on CPU_V7
1001	help
1002	  This option enables the workaround for:
1003	  - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1004	    instruction might deadlock.  Fixed in r0p1.
1005	  - Cortex-A12 852422: Execution of a sequence of instructions might
1006	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1007	    any Cortex-A12 cores yet.
1008	  This workaround for all both errata involves setting bit[12] of the
1009	  Feature Register. This bit disables an optimisation applied to a
1010	  sequence of 2 instructions that use opposing condition codes.
1011
1012config ARM_ERRATA_821420
1013	bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1014	depends on CPU_V7
1015	help
1016	  This option enables the workaround for the 821420 Cortex-A12
1017	  (all revs) erratum. In very rare timing conditions, a sequence
1018	  of VMOV to Core registers instructions, for which the second
1019	  one is in the shadow of a branch or abort, can lead to a
1020	  deadlock when the VMOV instructions are issued out-of-order.
1021
1022config ARM_ERRATA_825619
1023	bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1024	depends on CPU_V7
1025	help
1026	  This option enables the workaround for the 825619 Cortex-A12
1027	  (all revs) erratum. Within rare timing constraints, executing a
1028	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1029	  and Device/Strongly-Ordered loads and stores might cause deadlock
1030
1031config ARM_ERRATA_857271
1032	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1033	depends on CPU_V7
1034	help
1035	  This option enables the workaround for the 857271 Cortex-A12
1036	  (all revs) erratum. Under very rare timing conditions, the CPU might
1037	  hang. The workaround is expected to have a < 1% performance impact.
1038
1039config ARM_ERRATA_852421
1040	bool "ARM errata: A17: DMB ST might fail to create order between stores"
1041	depends on CPU_V7
1042	help
1043	  This option enables the workaround for the 852421 Cortex-A17
1044	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1045	  execution of a DMB ST instruction might fail to properly order
1046	  stores from GroupA and stores from GroupB.
1047
1048config ARM_ERRATA_852423
1049	bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1050	depends on CPU_V7
1051	help
1052	  This option enables the workaround for:
1053	  - Cortex-A17 852423: Execution of a sequence of instructions might
1054	    lead to either a data corruption or a CPU deadlock.  Not fixed in
1055	    any Cortex-A17 cores yet.
1056	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1057	  config option from the A12 erratum due to the way errata are checked
1058	  for and handled.
1059
1060config ARM_ERRATA_857272
1061	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1062	depends on CPU_V7
1063	help
1064	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1065	  This erratum is not known to be fixed in any A17 revision.
1066	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1067	  config option from the A12 erratum due to the way errata are checked
1068	  for and handled.
1069
1070endmenu
1071
1072source "arch/arm/common/Kconfig"
1073
1074menu "Bus support"
1075
1076config ISA
1077	bool
1078	help
1079	  Find out whether you have ISA slots on your motherboard.  ISA is the
1080	  name of a bus system, i.e. the way the CPU talks to the other stuff
1081	  inside your box.  Other bus systems are PCI, EISA, MicroChannel
1082	  (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1083	  newer boards don't support it.  If you have ISA, say Y, otherwise N.
1084
1085# Select ISA DMA controller support
1086config ISA_DMA
1087	bool
1088	select ISA_DMA_API
1089
1090# Select ISA DMA interface
1091config ISA_DMA_API
1092	bool
1093
1094config PCI_NANOENGINE
1095	bool "BSE nanoEngine PCI support"
1096	depends on SA1100_NANOENGINE
1097	help
1098	  Enable PCI on the BSE nanoEngine board.
1099
1100config ARM_ERRATA_814220
1101	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1102	depends on CPU_V7
1103	help
1104	  The v7 ARM states that all cache and branch predictor maintenance
1105	  operations that do not specify an address execute, relative to
1106	  each other, in program order.
1107	  However, because of this erratum, an L2 set/way cache maintenance
1108	  operation can overtake an L1 set/way cache maintenance operation.
1109	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1110	  r0p4, r0p5.
1111
1112endmenu
1113
1114menu "Kernel Features"
1115
1116config HAVE_SMP
1117	bool
1118	help
1119	  This option should be selected by machines which have an SMP-
1120	  capable CPU.
1121
1122	  The only effect of this option is to make the SMP-related
1123	  options available to the user for configuration.
1124
1125config SMP
1126	bool "Symmetric Multi-Processing"
1127	depends on CPU_V6K || CPU_V7
1128	depends on HAVE_SMP
1129	depends on MMU || ARM_MPU
1130	select IRQ_WORK
1131	help
1132	  This enables support for systems with more than one CPU. If you have
1133	  a system with only one CPU, say N. If you have a system with more
1134	  than one CPU, say Y.
1135
1136	  If you say N here, the kernel will run on uni- and multiprocessor
1137	  machines, but will use only one CPU of a multiprocessor machine. If
1138	  you say Y here, the kernel will run on many, but not all,
1139	  uniprocessor machines. On a uniprocessor machine, the kernel
1140	  will run faster if you say N here.
1141
1142	  See also <file:Documentation/x86/i386/IO-APIC.rst>,
1143	  <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1144	  <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1145
1146	  If you don't know what to do here, say N.
1147
1148config SMP_ON_UP
1149	bool "Allow booting SMP kernel on uniprocessor systems"
1150	depends on SMP && !XIP_KERNEL && MMU
1151	default y
1152	help
1153	  SMP kernels contain instructions which fail on non-SMP processors.
1154	  Enabling this option allows the kernel to modify itself to make
1155	  these instructions safe.  Disabling it allows about 1K of space
1156	  savings.
1157
1158	  If you don't know what to do here, say Y.
1159
1160config ARM_CPU_TOPOLOGY
1161	bool "Support cpu topology definition"
1162	depends on SMP && CPU_V7
1163	default y
1164	help
1165	  Support ARM cpu topology definition. The MPIDR register defines
1166	  affinity between processors which is then used to describe the cpu
1167	  topology of an ARM System.
1168
1169config SCHED_MC
1170	bool "Multi-core scheduler support"
1171	depends on ARM_CPU_TOPOLOGY
1172	help
1173	  Multi-core scheduler support improves the CPU scheduler's decision
1174	  making when dealing with multi-core CPU chips at a cost of slightly
1175	  increased overhead in some places. If unsure say N here.
1176
1177config SCHED_SMT
1178	bool "SMT scheduler support"
1179	depends on ARM_CPU_TOPOLOGY
1180	help
1181	  Improves the CPU scheduler's decision making when dealing with
1182	  MultiThreading at a cost of slightly increased overhead in some
1183	  places. If unsure say N here.
1184
1185config HAVE_ARM_SCU
1186	bool
1187	help
1188	  This option enables support for the ARM snoop control unit
1189
1190config HAVE_ARM_ARCH_TIMER
1191	bool "Architected timer support"
1192	depends on CPU_V7
1193	select ARM_ARCH_TIMER
1194	help
1195	  This option enables support for the ARM architected timer
1196
1197config HAVE_ARM_TWD
1198	bool
1199	help
1200	  This options enables support for the ARM timer and watchdog unit
1201
1202config MCPM
1203	bool "Multi-Cluster Power Management"
1204	depends on CPU_V7 && SMP
1205	help
1206	  This option provides the common power management infrastructure
1207	  for (multi-)cluster based systems, such as big.LITTLE based
1208	  systems.
1209
1210config MCPM_QUAD_CLUSTER
1211	bool
1212	depends on MCPM
1213	help
1214	  To avoid wasting resources unnecessarily, MCPM only supports up
1215	  to 2 clusters by default.
1216	  Platforms with 3 or 4 clusters that use MCPM must select this
1217	  option to allow the additional clusters to be managed.
1218
1219config BIG_LITTLE
1220	bool "big.LITTLE support (Experimental)"
1221	depends on CPU_V7 && SMP
1222	select MCPM
1223	help
1224	  This option enables support selections for the big.LITTLE
1225	  system architecture.
1226
1227config BL_SWITCHER
1228	bool "big.LITTLE switcher support"
1229	depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1230	select CPU_PM
1231	help
1232	  The big.LITTLE "switcher" provides the core functionality to
1233	  transparently handle transition between a cluster of A15's
1234	  and a cluster of A7's in a big.LITTLE system.
1235
1236config BL_SWITCHER_DUMMY_IF
1237	tristate "Simple big.LITTLE switcher user interface"
1238	depends on BL_SWITCHER && DEBUG_KERNEL
1239	help
1240	  This is a simple and dummy char dev interface to control
1241	  the big.LITTLE switcher core code.  It is meant for
1242	  debugging purposes only.
1243
1244choice
1245	prompt "Memory split"
1246	depends on MMU
1247	default VMSPLIT_3G
1248	help
1249	  Select the desired split between kernel and user memory.
1250
1251	  If you are not absolutely sure what you are doing, leave this
1252	  option alone!
1253
1254	config VMSPLIT_3G
1255		bool "3G/1G user/kernel split"
1256	config VMSPLIT_3G_OPT
1257		depends on !ARM_LPAE
1258		bool "3G/1G user/kernel split (for full 1G low memory)"
1259	config VMSPLIT_2G
1260		bool "2G/2G user/kernel split"
1261	config VMSPLIT_1G
1262		bool "1G/3G user/kernel split"
1263endchoice
1264
1265config PAGE_OFFSET
1266	hex
1267	default PHYS_OFFSET if !MMU
1268	default 0x40000000 if VMSPLIT_1G
1269	default 0x80000000 if VMSPLIT_2G
1270	default 0xB0000000 if VMSPLIT_3G_OPT
1271	default 0xC0000000
1272
1273config KASAN_SHADOW_OFFSET
1274	hex
1275	depends on KASAN
1276	default 0x1f000000 if PAGE_OFFSET=0x40000000
1277	default 0x5f000000 if PAGE_OFFSET=0x80000000
1278	default 0x9f000000 if PAGE_OFFSET=0xC0000000
1279	default 0x8f000000 if PAGE_OFFSET=0xB0000000
1280	default 0xffffffff
1281
1282config NR_CPUS
1283	int "Maximum number of CPUs (2-32)"
1284	range 2 16 if DEBUG_KMAP_LOCAL
1285	range 2 32 if !DEBUG_KMAP_LOCAL
1286	depends on SMP
1287	default "4"
1288	help
1289	  The maximum number of CPUs that the kernel can support.
1290	  Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1291	  debugging is enabled, which uses half of the per-CPU fixmap
1292	  slots as guard regions.
1293
1294config HOTPLUG_CPU
1295	bool "Support for hot-pluggable CPUs"
1296	depends on SMP
1297	select GENERIC_IRQ_MIGRATION
1298	help
1299	  Say Y here to experiment with turning CPUs off and on.  CPUs
1300	  can be controlled through /sys/devices/system/cpu.
1301
1302config ARM_PSCI
1303	bool "Support for the ARM Power State Coordination Interface (PSCI)"
1304	depends on HAVE_ARM_SMCCC
1305	select ARM_PSCI_FW
1306	help
1307	  Say Y here if you want Linux to communicate with system firmware
1308	  implementing the PSCI specification for CPU-centric power
1309	  management operations described in ARM document number ARM DEN
1310	  0022A ("Power State Coordination Interface System Software on
1311	  ARM processors").
1312
1313# The GPIO number here must be sorted by descending number. In case of
1314# a multiplatform kernel, we just want the highest value required by the
1315# selected platforms.
1316config ARCH_NR_GPIO
1317	int
1318	default 2048 if ARCH_INTEL_SOCFPGA
1319	default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1320		ARCH_ZYNQ || ARCH_ASPEED
1321	default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1322		SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1323	default 416 if ARCH_SUNXI
1324	default 392 if ARCH_U8500
1325	default 352 if ARCH_VT8500
1326	default 288 if ARCH_ROCKCHIP
1327	default 264 if MACH_H4700
1328	default 0
1329	help
1330	  Maximum number of GPIOs in the system.
1331
1332	  If unsure, leave the default value.
1333
1334config HZ_FIXED
1335	int
1336	default 128 if SOC_AT91RM9200
1337	default 0
1338
1339choice
1340	depends on HZ_FIXED = 0
1341	prompt "Timer frequency"
1342
1343config HZ_100
1344	bool "100 Hz"
1345
1346config HZ_200
1347	bool "200 Hz"
1348
1349config HZ_250
1350	bool "250 Hz"
1351
1352config HZ_300
1353	bool "300 Hz"
1354
1355config HZ_500
1356	bool "500 Hz"
1357
1358config HZ_1000
1359	bool "1000 Hz"
1360
1361endchoice
1362
1363config HZ
1364	int
1365	default HZ_FIXED if HZ_FIXED != 0
1366	default 100 if HZ_100
1367	default 200 if HZ_200
1368	default 250 if HZ_250
1369	default 300 if HZ_300
1370	default 500 if HZ_500
1371	default 1000
1372
1373config SCHED_HRTICK
1374	def_bool HIGH_RES_TIMERS
1375
1376config THUMB2_KERNEL
1377	bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1378	depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1379	default y if CPU_THUMBONLY
1380	select ARM_UNWIND
1381	help
1382	  By enabling this option, the kernel will be compiled in
1383	  Thumb-2 mode.
1384
1385	  If unsure, say N.
1386
1387config ARM_PATCH_IDIV
1388	bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1389	depends on CPU_32v7 && !XIP_KERNEL
1390	default y
1391	help
1392	  The ARM compiler inserts calls to __aeabi_idiv() and
1393	  __aeabi_uidiv() when it needs to perform division on signed
1394	  and unsigned integers. Some v7 CPUs have support for the sdiv
1395	  and udiv instructions that can be used to implement those
1396	  functions.
1397
1398	  Enabling this option allows the kernel to modify itself to
1399	  replace the first two instructions of these library functions
1400	  with the sdiv or udiv plus "bx lr" instructions when the CPU
1401	  it is running on supports them. Typically this will be faster
1402	  and less power intensive than running the original library
1403	  code to do integer division.
1404
1405config AEABI
1406	bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1407		!CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1408	default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1409	help
1410	  This option allows for the kernel to be compiled using the latest
1411	  ARM ABI (aka EABI).  This is only useful if you are using a user
1412	  space environment that is also compiled with EABI.
1413
1414	  Since there are major incompatibilities between the legacy ABI and
1415	  EABI, especially with regard to structure member alignment, this
1416	  option also changes the kernel syscall calling convention to
1417	  disambiguate both ABIs and allow for backward compatibility support
1418	  (selected with CONFIG_OABI_COMPAT).
1419
1420	  To use this you need GCC version 4.0.0 or later.
1421
1422config OABI_COMPAT
1423	bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1424	depends on AEABI && !THUMB2_KERNEL
1425	help
1426	  This option preserves the old syscall interface along with the
1427	  new (ARM EABI) one. It also provides a compatibility layer to
1428	  intercept syscalls that have structure arguments which layout
1429	  in memory differs between the legacy ABI and the new ARM EABI
1430	  (only for non "thumb" binaries). This option adds a tiny
1431	  overhead to all syscalls and produces a slightly larger kernel.
1432
1433	  The seccomp filter system will not be available when this is
1434	  selected, since there is no way yet to sensibly distinguish
1435	  between calling conventions during filtering.
1436
1437	  If you know you'll be using only pure EABI user space then you
1438	  can say N here. If this option is not selected and you attempt
1439	  to execute a legacy ABI binary then the result will be
1440	  UNPREDICTABLE (in fact it can be predicted that it won't work
1441	  at all). If in doubt say N.
1442
1443config ARCH_SELECT_MEMORY_MODEL
1444	bool
1445
1446config ARCH_FLATMEM_ENABLE
1447	bool
1448
1449config ARCH_SPARSEMEM_ENABLE
1450	bool
1451	select SPARSEMEM_STATIC if SPARSEMEM
1452
1453config HIGHMEM
1454	bool "High Memory Support"
1455	depends on MMU
1456	select KMAP_LOCAL
1457	help
1458	  The address space of ARM processors is only 4 Gigabytes large
1459	  and it has to accommodate user address space, kernel address
1460	  space as well as some memory mapped IO. That means that, if you
1461	  have a large amount of physical memory and/or IO, not all of the
1462	  memory can be "permanently mapped" by the kernel. The physical
1463	  memory that is not permanently mapped is called "high memory".
1464
1465	  Depending on the selected kernel/user memory split, minimum
1466	  vmalloc space and actual amount of RAM, you may not need this
1467	  option which should result in a slightly faster kernel.
1468
1469	  If unsure, say n.
1470
1471config HIGHPTE
1472	bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1473	depends on HIGHMEM
1474	default y
1475	help
1476	  The VM uses one page of physical memory for each page table.
1477	  For systems with a lot of processes, this can use a lot of
1478	  precious low memory, eventually leading to low memory being
1479	  consumed by page tables.  Setting this option will allow
1480	  user-space 2nd level page tables to reside in high memory.
1481
1482config CPU_SW_DOMAIN_PAN
1483	bool "Enable use of CPU domains to implement privileged no-access"
1484	depends on MMU && !ARM_LPAE
1485	default y
1486	help
1487	  Increase kernel security by ensuring that normal kernel accesses
1488	  are unable to access userspace addresses.  This can help prevent
1489	  use-after-free bugs becoming an exploitable privilege escalation
1490	  by ensuring that magic values (such as LIST_POISON) will always
1491	  fault when dereferenced.
1492
1493	  CPUs with low-vector mappings use a best-efforts implementation.
1494	  Their lower 1MB needs to remain accessible for the vectors, but
1495	  the remainder of userspace will become appropriately inaccessible.
1496
1497config HW_PERF_EVENTS
1498	def_bool y
1499	depends on ARM_PMU
1500
1501config ARCH_WANT_GENERAL_HUGETLB
1502	def_bool y
1503
1504config ARM_MODULE_PLTS
1505	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1506	depends on MODULES
1507	default y
1508	help
1509	  Allocate PLTs when loading modules so that jumps and calls whose
1510	  targets are too far away for their relative offsets to be encoded
1511	  in the instructions themselves can be bounced via veneers in the
1512	  module's PLT. This allows modules to be allocated in the generic
1513	  vmalloc area after the dedicated module memory area has been
1514	  exhausted. The modules will use slightly more memory, but after
1515	  rounding up to page size, the actual memory footprint is usually
1516	  the same.
1517
1518	  Disabling this is usually safe for small single-platform
1519	  configurations. If unsure, say y.
1520
1521config FORCE_MAX_ZONEORDER
1522	int "Maximum zone order"
1523	default "12" if SOC_AM33XX
1524	default "9" if SA1111
1525	default "11"
1526	help
1527	  The kernel memory allocator divides physically contiguous memory
1528	  blocks into "zones", where each zone is a power of two number of
1529	  pages.  This option selects the largest power of two that the kernel
1530	  keeps in the memory allocator.  If you need to allocate very large
1531	  blocks of physically contiguous memory, then you may need to
1532	  increase this value.
1533
1534	  This config option is actually maximum order plus one. For example,
1535	  a value of 11 means that the largest free memory block is 2^10 pages.
1536
1537config ALIGNMENT_TRAP
1538	def_bool CPU_CP15_MMU
1539	select HAVE_PROC_CPU if PROC_FS
1540	help
1541	  ARM processors cannot fetch/store information which is not
1542	  naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1543	  address divisible by 4. On 32-bit ARM processors, these non-aligned
1544	  fetch/store instructions will be emulated in software if you say
1545	  here, which has a severe performance impact. This is necessary for
1546	  correct operation of some network protocols. With an IP-only
1547	  configuration it is safe to say N, otherwise say Y.
1548
1549config UACCESS_WITH_MEMCPY
1550	bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1551	depends on MMU
1552	default y if CPU_FEROCEON
1553	help
1554	  Implement faster copy_to_user and clear_user methods for CPU
1555	  cores where a 8-word STM instruction give significantly higher
1556	  memory write throughput than a sequence of individual 32bit stores.
1557
1558	  A possible side effect is a slight increase in scheduling latency
1559	  between threads sharing the same address space if they invoke
1560	  such copy operations with large buffers.
1561
1562	  However, if the CPU data cache is using a write-allocate mode,
1563	  this option is unlikely to provide any performance gain.
1564
1565config PARAVIRT
1566	bool "Enable paravirtualization code"
1567	help
1568	  This changes the kernel so it can modify itself when it is run
1569	  under a hypervisor, potentially improving performance significantly
1570	  over full virtualization.
1571
1572config PARAVIRT_TIME_ACCOUNTING
1573	bool "Paravirtual steal time accounting"
1574	select PARAVIRT
1575	help
1576	  Select this option to enable fine granularity task steal time
1577	  accounting. Time spent executing other tasks in parallel with
1578	  the current vCPU is discounted from the vCPU power. To account for
1579	  that, there can be a small performance impact.
1580
1581	  If in doubt, say N here.
1582
1583config XEN_DOM0
1584	def_bool y
1585	depends on XEN
1586
1587config XEN
1588	bool "Xen guest support on ARM"
1589	depends on ARM && AEABI && OF
1590	depends on CPU_V7 && !CPU_V6
1591	depends on !GENERIC_ATOMIC64
1592	depends on MMU
1593	select ARCH_DMA_ADDR_T_64BIT
1594	select ARM_PSCI
1595	select SWIOTLB
1596	select SWIOTLB_XEN
1597	select PARAVIRT
1598	help
1599	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1600
1601config STACKPROTECTOR_PER_TASK
1602	bool "Use a unique stack canary value for each task"
1603	depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1604	select GCC_PLUGIN_ARM_SSP_PER_TASK
1605	default y
1606	help
1607	  Due to the fact that GCC uses an ordinary symbol reference from
1608	  which to load the value of the stack canary, this value can only
1609	  change at reboot time on SMP systems, and all tasks running in the
1610	  kernel's address space are forced to use the same canary value for
1611	  the entire duration that the system is up.
1612
1613	  Enable this option to switch to a different method that uses a
1614	  different canary value for each task.
1615
1616endmenu
1617
1618menu "Boot options"
1619
1620config USE_OF
1621	bool "Flattened Device Tree support"
1622	select IRQ_DOMAIN
1623	select OF
1624	help
1625	  Include support for flattened device tree machine descriptions.
1626
1627config ATAGS
1628	bool "Support for the traditional ATAGS boot data passing" if USE_OF
1629	default y
1630	help
1631	  This is the traditional way of passing data to the kernel at boot
1632	  time. If you are solely relying on the flattened device tree (or
1633	  the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1634	  to remove ATAGS support from your kernel binary.  If unsure,
1635	  leave this to y.
1636
1637config DEPRECATED_PARAM_STRUCT
1638	bool "Provide old way to pass kernel parameters"
1639	depends on ATAGS
1640	help
1641	  This was deprecated in 2001 and announced to live on for 5 years.
1642	  Some old boot loaders still use this way.
1643
1644# Compressed boot loader in ROM.  Yes, we really want to ask about
1645# TEXT and BSS so we preserve their values in the config files.
1646config ZBOOT_ROM_TEXT
1647	hex "Compressed ROM boot loader base address"
1648	default 0x0
1649	help
1650	  The physical address at which the ROM-able zImage is to be
1651	  placed in the target.  Platforms which normally make use of
1652	  ROM-able zImage formats normally set this to a suitable
1653	  value in their defconfig file.
1654
1655	  If ZBOOT_ROM is not enabled, this has no effect.
1656
1657config ZBOOT_ROM_BSS
1658	hex "Compressed ROM boot loader BSS address"
1659	default 0x0
1660	help
1661	  The base address of an area of read/write memory in the target
1662	  for the ROM-able zImage which must be available while the
1663	  decompressor is running. It must be large enough to hold the
1664	  entire decompressed kernel plus an additional 128 KiB.
1665	  Platforms which normally make use of ROM-able zImage formats
1666	  normally set this to a suitable value in their defconfig file.
1667
1668	  If ZBOOT_ROM is not enabled, this has no effect.
1669
1670config ZBOOT_ROM
1671	bool "Compressed boot loader in ROM/flash"
1672	depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1673	depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1674	help
1675	  Say Y here if you intend to execute your compressed kernel image
1676	  (zImage) directly from ROM or flash.  If unsure, say N.
1677
1678config ARM_APPENDED_DTB
1679	bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1680	depends on OF
1681	help
1682	  With this option, the boot code will look for a device tree binary
1683	  (DTB) appended to zImage
1684	  (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1685
1686	  This is meant as a backward compatibility convenience for those
1687	  systems with a bootloader that can't be upgraded to accommodate
1688	  the documented boot protocol using a device tree.
1689
1690	  Beware that there is very little in terms of protection against
1691	  this option being confused by leftover garbage in memory that might
1692	  look like a DTB header after a reboot if no actual DTB is appended
1693	  to zImage.  Do not leave this option active in a production kernel
1694	  if you don't intend to always append a DTB.  Proper passing of the
1695	  location into r2 of a bootloader provided DTB is always preferable
1696	  to this option.
1697
1698config ARM_ATAG_DTB_COMPAT
1699	bool "Supplement the appended DTB with traditional ATAG information"
1700	depends on ARM_APPENDED_DTB
1701	help
1702	  Some old bootloaders can't be updated to a DTB capable one, yet
1703	  they provide ATAGs with memory configuration, the ramdisk address,
1704	  the kernel cmdline string, etc.  Such information is dynamically
1705	  provided by the bootloader and can't always be stored in a static
1706	  DTB.  To allow a device tree enabled kernel to be used with such
1707	  bootloaders, this option allows zImage to extract the information
1708	  from the ATAG list and store it at run time into the appended DTB.
1709
1710choice
1711	prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1712	default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1713
1714config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1715	bool "Use bootloader kernel arguments if available"
1716	help
1717	  Uses the command-line options passed by the boot loader instead of
1718	  the device tree bootargs property. If the boot loader doesn't provide
1719	  any, the device tree bootargs property will be used.
1720
1721config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1722	bool "Extend with bootloader kernel arguments"
1723	help
1724	  The command-line arguments provided by the boot loader will be
1725	  appended to the the device tree bootargs property.
1726
1727endchoice
1728
1729config CMDLINE
1730	string "Default kernel command string"
1731	default ""
1732	help
1733	  On some architectures (e.g. CATS), there is currently no way
1734	  for the boot loader to pass arguments to the kernel. For these
1735	  architectures, you should supply some command-line options at build
1736	  time by entering them here. As a minimum, you should specify the
1737	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
1738
1739choice
1740	prompt "Kernel command line type" if CMDLINE != ""
1741	default CMDLINE_FROM_BOOTLOADER
1742	depends on ATAGS
1743
1744config CMDLINE_FROM_BOOTLOADER
1745	bool "Use bootloader kernel arguments if available"
1746	help
1747	  Uses the command-line options passed by the boot loader. If
1748	  the boot loader doesn't provide any, the default kernel command
1749	  string provided in CMDLINE will be used.
1750
1751config CMDLINE_EXTEND
1752	bool "Extend bootloader kernel arguments"
1753	help
1754	  The command-line arguments provided by the boot loader will be
1755	  appended to the default kernel command string.
1756
1757config CMDLINE_FORCE
1758	bool "Always use the default kernel command string"
1759	help
1760	  Always use the default kernel command string, even if the boot
1761	  loader passes other arguments to the kernel.
1762	  This is useful if you cannot or don't want to change the
1763	  command-line options your boot loader passes to the kernel.
1764endchoice
1765
1766config XIP_KERNEL
1767	bool "Kernel Execute-In-Place from ROM"
1768	depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1769	help
1770	  Execute-In-Place allows the kernel to run from non-volatile storage
1771	  directly addressable by the CPU, such as NOR flash. This saves RAM
1772	  space since the text section of the kernel is not loaded from flash
1773	  to RAM.  Read-write sections, such as the data section and stack,
1774	  are still copied to RAM.  The XIP kernel is not compressed since
1775	  it has to run directly from flash, so it will take more space to
1776	  store it.  The flash address used to link the kernel object files,
1777	  and for storing it, is configuration dependent. Therefore, if you
1778	  say Y here, you must know the proper physical address where to
1779	  store the kernel image depending on your own flash memory usage.
1780
1781	  Also note that the make target becomes "make xipImage" rather than
1782	  "make zImage" or "make Image".  The final kernel binary to put in
1783	  ROM memory will be arch/arm/boot/xipImage.
1784
1785	  If unsure, say N.
1786
1787config XIP_PHYS_ADDR
1788	hex "XIP Kernel Physical Location"
1789	depends on XIP_KERNEL
1790	default "0x00080000"
1791	help
1792	  This is the physical address in your flash memory the kernel will
1793	  be linked for and stored to.  This address is dependent on your
1794	  own flash usage.
1795
1796config XIP_DEFLATED_DATA
1797	bool "Store kernel .data section compressed in ROM"
1798	depends on XIP_KERNEL
1799	select ZLIB_INFLATE
1800	help
1801	  Before the kernel is actually executed, its .data section has to be
1802	  copied to RAM from ROM. This option allows for storing that data
1803	  in compressed form and decompressed to RAM rather than merely being
1804	  copied, saving some precious ROM space. A possible drawback is a
1805	  slightly longer boot delay.
1806
1807config KEXEC
1808	bool "Kexec system call (EXPERIMENTAL)"
1809	depends on (!SMP || PM_SLEEP_SMP)
1810	depends on MMU
1811	select KEXEC_CORE
1812	help
1813	  kexec is a system call that implements the ability to shutdown your
1814	  current kernel, and to start another kernel.  It is like a reboot
1815	  but it is independent of the system firmware.   And like a reboot
1816	  you can start any kernel with it, not just Linux.
1817
1818	  It is an ongoing process to be certain the hardware in a machine
1819	  is properly shutdown, so do not be surprised if this code does not
1820	  initially work for you.
1821
1822config ATAGS_PROC
1823	bool "Export atags in procfs"
1824	depends on ATAGS && KEXEC
1825	default y
1826	help
1827	  Should the atags used to boot the kernel be exported in an "atags"
1828	  file in procfs. Useful with kexec.
1829
1830config CRASH_DUMP
1831	bool "Build kdump crash kernel (EXPERIMENTAL)"
1832	help
1833	  Generate crash dump after being started by kexec. This should
1834	  be normally only set in special crash dump kernels which are
1835	  loaded in the main kernel with kexec-tools into a specially
1836	  reserved region and then later executed after a crash by
1837	  kdump/kexec. The crash dump kernel must be compiled to a
1838	  memory address not used by the main kernel
1839
1840	  For more details see Documentation/admin-guide/kdump/kdump.rst
1841
1842config AUTO_ZRELADDR
1843	bool "Auto calculation of the decompressed kernel image address"
1844	help
1845	  ZRELADDR is the physical address where the decompressed kernel
1846	  image will be placed. If AUTO_ZRELADDR is selected, the address
1847	  will be determined at run-time, either by masking the current IP
1848	  with 0xf8000000, or, if invalid, from the DTB passed in r2.
1849	  This assumes the zImage being placed in the first 128MB from
1850	  start of memory.
1851
1852config EFI_STUB
1853	bool
1854
1855config EFI
1856	bool "UEFI runtime support"
1857	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1858	select UCS2_STRING
1859	select EFI_PARAMS_FROM_FDT
1860	select EFI_STUB
1861	select EFI_GENERIC_STUB
1862	select EFI_RUNTIME_WRAPPERS
1863	help
1864	  This option provides support for runtime services provided
1865	  by UEFI firmware (such as non-volatile variables, realtime
1866	  clock, and platform reset). A UEFI stub is also provided to
1867	  allow the kernel to be booted as an EFI application. This
1868	  is only useful for kernels that may run on systems that have
1869	  UEFI firmware.
1870
1871config DMI
1872	bool "Enable support for SMBIOS (DMI) tables"
1873	depends on EFI
1874	default y
1875	help
1876	  This enables SMBIOS/DMI feature for systems.
1877
1878	  This option is only useful on systems that have UEFI firmware.
1879	  However, even with this option, the resultant kernel should
1880	  continue to boot on existing non-UEFI platforms.
1881
1882	  NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1883	  i.e., the the practice of identifying the platform via DMI to
1884	  decide whether certain workarounds for buggy hardware and/or
1885	  firmware need to be enabled. This would require the DMI subsystem
1886	  to be enabled much earlier than we do on ARM, which is non-trivial.
1887
1888endmenu
1889
1890menu "CPU Power Management"
1891
1892source "drivers/cpufreq/Kconfig"
1893
1894source "drivers/cpuidle/Kconfig"
1895
1896endmenu
1897
1898menu "Floating point emulation"
1899
1900comment "At least one emulation must be selected"
1901
1902config FPE_NWFPE
1903	bool "NWFPE math emulation"
1904	depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1905	help
1906	  Say Y to include the NWFPE floating point emulator in the kernel.
1907	  This is necessary to run most binaries. Linux does not currently
1908	  support floating point hardware so you need to say Y here even if
1909	  your machine has an FPA or floating point co-processor podule.
1910
1911	  You may say N here if you are going to load the Acorn FPEmulator
1912	  early in the bootup.
1913
1914config FPE_NWFPE_XP
1915	bool "Support extended precision"
1916	depends on FPE_NWFPE
1917	help
1918	  Say Y to include 80-bit support in the kernel floating-point
1919	  emulator.  Otherwise, only 32 and 64-bit support is compiled in.
1920	  Note that gcc does not generate 80-bit operations by default,
1921	  so in most cases this option only enlarges the size of the
1922	  floating point emulator without any good reason.
1923
1924	  You almost surely want to say N here.
1925
1926config FPE_FASTFPE
1927	bool "FastFPE math emulation (EXPERIMENTAL)"
1928	depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1929	help
1930	  Say Y here to include the FAST floating point emulator in the kernel.
1931	  This is an experimental much faster emulator which now also has full
1932	  precision for the mantissa.  It does not support any exceptions.
1933	  It is very simple, and approximately 3-6 times faster than NWFPE.
1934
1935	  It should be sufficient for most programs.  It may be not suitable
1936	  for scientific calculations, but you have to check this for yourself.
1937	  If you do not feel you need a faster FP emulation you should better
1938	  choose NWFPE.
1939
1940config VFP
1941	bool "VFP-format floating point maths"
1942	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1943	help
1944	  Say Y to include VFP support code in the kernel. This is needed
1945	  if your hardware includes a VFP unit.
1946
1947	  Please see <file:Documentation/arm/vfp/release-notes.rst> for
1948	  release notes and additional status information.
1949
1950	  Say N if your target does not have VFP hardware.
1951
1952config VFPv3
1953	bool
1954	depends on VFP
1955	default y if CPU_V7
1956
1957config NEON
1958	bool "Advanced SIMD (NEON) Extension support"
1959	depends on VFPv3 && CPU_V7
1960	help
1961	  Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1962	  Extension.
1963
1964config KERNEL_MODE_NEON
1965	bool "Support for NEON in kernel mode"
1966	depends on NEON && AEABI
1967	help
1968	  Say Y to include support for NEON in kernel mode.
1969
1970endmenu
1971
1972menu "Power management options"
1973
1974source "kernel/power/Kconfig"
1975
1976config ARCH_SUSPEND_POSSIBLE
1977	depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1978		CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1979	def_bool y
1980
1981config ARM_CPU_SUSPEND
1982	def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1983	depends on ARCH_SUSPEND_POSSIBLE
1984
1985config ARCH_HIBERNATION_POSSIBLE
1986	bool
1987	depends on MMU
1988	default y if ARCH_SUSPEND_POSSIBLE
1989
1990endmenu
1991
1992source "drivers/firmware/Kconfig"
1993
1994if CRYPTO
1995source "arch/arm/crypto/Kconfig"
1996endif
1997
1998source "arch/arm/Kconfig.assembler"
1999