xref: /openbmc/linux/arch/arc/kernel/head.S (revision 5f32c314)
1/*
2 * ARC CPU startup Code
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Vineetg: Dec 2007
11 *  -Check if we are running on Simulator or on real hardware
12 *      to skip certain things during boot on simulator
13 */
14
15#include <asm/asm-offsets.h>
16#include <asm/entry.h>
17#include <linux/linkage.h>
18#include <asm/arcregs.h>
19
20	.cpu A7
21
22	.section .init.text, "ax",@progbits
23	.type stext, @function
24	.globl stext
25stext:
26	;-------------------------------------------------------------------
27	; Don't clobber r0-r4 yet. It might have bootloader provided info
28	;-------------------------------------------------------------------
29
30	sr	@_int_vec_base_lds, [AUX_INTR_VEC_BASE]
31
32#ifdef CONFIG_SMP
33	; Only Boot (Master) proceeds. Others wait in platform dependent way
34	;	IDENTITY Reg [ 3  2  1  0 ]
35	;	(cpu-id)             ^^^	=> Zero for UP ARC700
36	;					=> #Core-ID if SMP (Master 0)
37	; Note that non-boot CPUs might not land here if halt-on-reset and
38	; instead breath life from @first_lines_of_secondary, but we still
39	; need to make sure only boot cpu takes this path.
40	GET_CPU_ID  r5
41	cmp	r5, 0
42	jnz	arc_platform_smp_wait_to_boot
43#endif
44	; Clear BSS before updating any globals
45	; XXX: use ZOL here
46	mov	r5, __bss_start
47	mov	r6, __bss_stop
481:
49	st.ab   0, [r5,4]
50	brlt    r5, r6, 1b
51
52	; Uboot - kernel ABI
53	;    r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
54	;    r1 = magic number (board identity, unused as of now
55	;    r2 = pointer to uboot provided cmdline or external DTB in mem
56	; These are handled later in setup_arch()
57	st	r0, [@uboot_tag]
58	st	r2, [@uboot_arg]
59
60	; Identify if running on ISS vs Silicon
61	; 	IDENTITY Reg [ 3  2  1  0 ]
62	;	(chip-id)      ^^^^^		==> 0xffff for ISS
63	lr	r0, [identity]
64	lsr	r3, r0, 16
65	cmp	r3, 0xffff
66	mov.z	r4, 0
67	mov.nz	r4, 1
68	st	r4, [@running_on_hw]
69
70	; setup "current" tsk and optionally cache it in dedicated r25
71	mov	r9, @init_task
72	SET_CURR_TASK_ON_CPU  r9, r0	; r9 = tsk, r0 = scratch
73
74	; setup stack (fp, sp)
75	mov	fp, 0
76
77	; tsk->thread_info is really a PAGE, whose bottom hoists stack
78	GET_TSK_STACK_BASE r9, sp	; r9 = tsk, sp = stack base(output)
79
80	j	start_kernel	; "C" entry point
81
82#ifdef CONFIG_SMP
83;----------------------------------------------------------------
84;     First lines of code run by secondary before jumping to 'C'
85;----------------------------------------------------------------
86	.section .text, "ax",@progbits
87	.type first_lines_of_secondary, @function
88	.globl first_lines_of_secondary
89
90first_lines_of_secondary:
91
92	sr	@_int_vec_base_lds, [AUX_INTR_VEC_BASE]
93
94	; setup per-cpu idle task as "current" on this CPU
95	ld	r0, [@secondary_idle_tsk]
96	SET_CURR_TASK_ON_CPU  r0, r1
97
98	; setup stack (fp, sp)
99	mov	fp, 0
100
101	; set it's stack base to tsk->thread_info bottom
102	GET_TSK_STACK_BASE r0, sp
103
104	j	start_kernel_secondary
105
106#endif
107