1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * ARC CPU startup Code 4 * 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 6 * 7 * Vineetg: Dec 2007 8 * -Check if we are running on Simulator or on real hardware 9 * to skip certain things during boot on simulator 10 */ 11 12#include <linux/linkage.h> 13#include <asm/asm-offsets.h> 14#include <asm/entry.h> 15#include <asm/arcregs.h> 16#include <asm/cache.h> 17#include <asm/dsp-impl.h> 18#include <asm/irqflags.h> 19 20.macro CPU_EARLY_SETUP 21 22 ; Setting up Vectror Table (in case exception happens in early boot 23 sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 24 25 ; Disable I-cache/D-cache if kernel so configured 26 lr r5, [ARC_REG_IC_BCR] 27 breq r5, 0, 1f ; I$ doesn't exist 28 lr r5, [ARC_REG_IC_CTRL] 29#ifdef CONFIG_ARC_HAS_ICACHE 30 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable 31#else 32 bset r5, r5, 0 ; I$ exists, but is not used 33#endif 34 sr r5, [ARC_REG_IC_CTRL] 35 361: 37 lr r5, [ARC_REG_DC_BCR] 38 breq r5, 0, 1f ; D$ doesn't exist 39 lr r5, [ARC_REG_DC_CTRL] 40 bclr r5, r5, 6 ; Invalidate (discard w/o wback) 41#ifdef CONFIG_ARC_HAS_DCACHE 42 bclr r5, r5, 0 ; Enable (+Inv) 43#else 44 bset r5, r5, 0 ; Disable (+Inv) 45#endif 46 sr r5, [ARC_REG_DC_CTRL] 47 481: 49 50#ifdef CONFIG_ISA_ARCV2 51 ; Unaligned access is disabled at reset, so re-enable early as 52 ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access 53 ; by default 54 lr r5, [status32] 55#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS 56 bset r5, r5, STATUS_AD_BIT 57#else 58 ; Although disabled at reset, bootloader might have enabled it 59 bclr r5, r5, STATUS_AD_BIT 60#endif 61 kflag r5 62#endif 63 ; Config DSP_CTRL properly, so kernel may use integer multiply, 64 ; multiply-accumulate, and divide operations 65 DSP_EARLY_INIT 66.endm 67 68 .section .init.text, "ax",@progbits 69 70;---------------------------------------------------------------- 71; Default Reset Handler (jumped into from Reset vector) 72; - Don't clobber r0,r1,r2 as they might have u-boot provided args 73; - Platforms can override this weak version if needed 74;---------------------------------------------------------------- 75WEAK(res_service) 76 j stext 77END(res_service) 78 79;---------------------------------------------------------------- 80; Kernel Entry point 81;---------------------------------------------------------------- 82ENTRY(stext) 83 84 CPU_EARLY_SETUP 85 86#ifdef CONFIG_SMP 87 GET_CPU_ID r5 88 cmp r5, 0 89 mov.nz r0, r5 90 bz .Lmaster_proceed 91 92 ; Non-Masters wait for Master to boot enough and bring them up 93 ; when they resume, tail-call to entry point 94 mov blink, @first_lines_of_secondary 95 j arc_platform_smp_wait_to_boot 96 97.Lmaster_proceed: 98#endif 99 100 ; Clear BSS before updating any globals 101 ; XXX: use ZOL here 102 mov r5, __bss_start 103 sub r6, __bss_stop, r5 104 lsr.f lp_count, r6, 2 105 lpnz 1f 106 st.ab 0, [r5, 4] 1071: 108 109 ; Uboot - kernel ABI 110 ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2 111 ; r1 = magic number (always zero as of now) 112 ; r2 = pointer to uboot provided cmdline or external DTB in mem 113 ; These are handled later in handle_uboot_args() 114 st r0, [@uboot_tag] 115 st r1, [@uboot_magic] 116 st r2, [@uboot_arg] 117 118 ; setup "current" tsk and optionally cache it in dedicated r25 119 mov r9, @init_task 120 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch 121 122 ; setup stack (fp, sp) 123 mov fp, 0 124 125 ; tsk->thread_info is really a PAGE, whose bottom hoists stack 126 GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output) 127 128 j start_kernel ; "C" entry point 129END(stext) 130 131#ifdef CONFIG_SMP 132;---------------------------------------------------------------- 133; First lines of code run by secondary before jumping to 'C' 134;---------------------------------------------------------------- 135 .section .text, "ax",@progbits 136ENTRY(first_lines_of_secondary) 137 138 ; setup per-cpu idle task as "current" on this CPU 139 ld r0, [@secondary_idle_tsk] 140 SET_CURR_TASK_ON_CPU r0, r1 141 142 ; setup stack (fp, sp) 143 mov fp, 0 144 145 ; set it's stack base to tsk->thread_info bottom 146 GET_TSK_STACK_BASE r0, sp 147 148 j start_kernel_secondary 149END(first_lines_of_secondary) 150#endif 151