1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12description: 13 The common content of the node is defined in snps,dwc3.yaml. 14 15 Phy documentation is provided in the following places. 16 17 USB2.0 PHY 18 Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml 19 20 Type-C PHY 21 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt 22 23allOf: 24 - $ref: snps,dwc3.yaml# 25 26select: 27 properties: 28 compatible: 29 contains: 30 enum: 31 - rockchip,rk3399-dwc3 32 required: 33 - compatible 34 35properties: 36 compatible: 37 items: 38 - enum: 39 - rockchip,rk3399-dwc3 40 - const: snps,dwc3 41 42 reg: 43 maxItems: 1 44 45 interrupts: 46 maxItems: 1 47 48 clocks: 49 items: 50 - description: 51 Controller reference clock, must to be 24 MHz 52 - description: 53 Controller suspend clock, must to be 24 MHz or 32 KHz 54 - description: 55 Master/Core clock, must to be >= 62.5 MHz for SS 56 operation and >= 30MHz for HS operation 57 - description: 58 Controller grf clock 59 60 clock-names: 61 items: 62 - const: ref_clk 63 - const: suspend_clk 64 - const: bus_clk 65 - const: grf_clk 66 67 power-domains: 68 maxItems: 1 69 70 resets: 71 maxItems: 1 72 73 reset-names: 74 const: usb3-otg 75 76unevaluatedProperties: false 77 78required: 79 - compatible 80 - reg 81 - interrupts 82 - clocks 83 - clock-names 84 85examples: 86 - | 87 #include <dt-bindings/clock/rk3399-cru.h> 88 #include <dt-bindings/interrupt-controller/arm-gic.h> 89 90 bus { 91 #address-cells = <2>; 92 #size-cells = <2>; 93 94 usbdrd3_0: usb@fe800000 { 95 compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; 96 reg = <0x0 0xfe800000 0x0 0x100000>; 97 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 99 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; 100 clock-names = "ref_clk", "suspend_clk", 101 "bus_clk", "grf_clk"; 102 dr_mode = "otg"; 103 }; 104 }; 105