1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8226-tsens 33 - qcom,msm8916-tsens 34 - qcom,msm8939-tsens 35 - qcom,msm8974-tsens 36 - const: qcom,tsens-v0_1 37 38 - description: v1 of TSENS 39 items: 40 - enum: 41 - qcom,msm8956-tsens 42 - qcom,msm8976-tsens 43 - qcom,qcs404-tsens 44 - const: qcom,tsens-v1 45 46 - description: v2 of TSENS 47 items: 48 - enum: 49 - qcom,msm8953-tsens 50 - qcom,msm8996-tsens 51 - qcom,msm8998-tsens 52 - qcom,qcm2290-tsens 53 - qcom,sc7180-tsens 54 - qcom,sc7280-tsens 55 - qcom,sc8180x-tsens 56 - qcom,sc8280xp-tsens 57 - qcom,sdm630-tsens 58 - qcom,sdm845-tsens 59 - qcom,sm6115-tsens 60 - qcom,sm6350-tsens 61 - qcom,sm6375-tsens 62 - qcom,sm8150-tsens 63 - qcom,sm8250-tsens 64 - qcom,sm8350-tsens 65 - qcom,sm8450-tsens 66 - qcom,sm8550-tsens 67 - const: qcom,tsens-v2 68 69 - description: v2 of TSENS with combined interrupt 70 enum: 71 - qcom,ipq8074-tsens 72 73 - description: v2 of TSENS with combined interrupt 74 items: 75 - enum: 76 - qcom,ipq9574-tsens 77 - const: qcom,ipq8074-tsens 78 79 reg: 80 items: 81 - description: TM registers 82 - description: SROT registers 83 84 interrupts: 85 minItems: 1 86 maxItems: 2 87 88 interrupt-names: 89 minItems: 1 90 maxItems: 2 91 92 nvmem-cells: 93 oneOf: 94 - minItems: 1 95 maxItems: 2 96 description: 97 Reference to an nvmem node for the calibration data 98 - minItems: 5 99 maxItems: 35 100 description: | 101 Reference to nvmem cells for the calibration mode, two calibration 102 bases and two cells per each sensor 103 # special case for msm8974 / apq8084 104 - maxItems: 51 105 description: | 106 Reference to nvmem cells for the calibration mode, two calibration 107 bases and two cells per each sensor, main and backup copies, plus use_backup cell 108 109 nvmem-cell-names: 110 oneOf: 111 - minItems: 1 112 items: 113 - const: calib 114 - enum: 115 - calib_backup 116 - calib_sel 117 - minItems: 5 118 items: 119 - const: mode 120 - const: base1 121 - const: base2 122 - pattern: '^s[0-9]+_p1$' 123 - pattern: '^s[0-9]+_p2$' 124 - pattern: '^s[0-9]+_p1$' 125 - pattern: '^s[0-9]+_p2$' 126 - pattern: '^s[0-9]+_p1$' 127 - pattern: '^s[0-9]+_p2$' 128 - pattern: '^s[0-9]+_p1$' 129 - pattern: '^s[0-9]+_p2$' 130 - pattern: '^s[0-9]+_p1$' 131 - pattern: '^s[0-9]+_p2$' 132 - pattern: '^s[0-9]+_p1$' 133 - pattern: '^s[0-9]+_p2$' 134 - pattern: '^s[0-9]+_p1$' 135 - pattern: '^s[0-9]+_p2$' 136 - pattern: '^s[0-9]+_p1$' 137 - pattern: '^s[0-9]+_p2$' 138 - pattern: '^s[0-9]+_p1$' 139 - pattern: '^s[0-9]+_p2$' 140 - pattern: '^s[0-9]+_p1$' 141 - pattern: '^s[0-9]+_p2$' 142 - pattern: '^s[0-9]+_p1$' 143 - pattern: '^s[0-9]+_p2$' 144 - pattern: '^s[0-9]+_p1$' 145 - pattern: '^s[0-9]+_p2$' 146 - pattern: '^s[0-9]+_p1$' 147 - pattern: '^s[0-9]+_p2$' 148 - pattern: '^s[0-9]+_p1$' 149 - pattern: '^s[0-9]+_p2$' 150 - pattern: '^s[0-9]+_p1$' 151 - pattern: '^s[0-9]+_p2$' 152 - pattern: '^s[0-9]+_p1$' 153 - pattern: '^s[0-9]+_p2$' 154 # special case for msm8974 / apq8084 155 - items: 156 - const: mode 157 - const: base1 158 - const: base2 159 - const: use_backup 160 - const: mode_backup 161 - const: base1_backup 162 - const: base2_backup 163 - const: s0_p1 164 - const: s0_p2 165 - const: s1_p1 166 - const: s1_p2 167 - const: s2_p1 168 - const: s2_p2 169 - const: s3_p1 170 - const: s3_p2 171 - const: s4_p1 172 - const: s4_p2 173 - const: s5_p1 174 - const: s5_p2 175 - const: s6_p1 176 - const: s6_p2 177 - const: s7_p1 178 - const: s7_p2 179 - const: s8_p1 180 - const: s8_p2 181 - const: s9_p1 182 - const: s9_p2 183 - const: s10_p1 184 - const: s10_p2 185 - const: s0_p1_backup 186 - const: s0_p2_backup 187 - const: s1_p1_backup 188 - const: s1_p2_backup 189 - const: s2_p1_backup 190 - const: s2_p2_backup 191 - const: s3_p1_backup 192 - const: s3_p2_backup 193 - const: s4_p1_backup 194 - const: s4_p2_backup 195 - const: s5_p1_backup 196 - const: s5_p2_backup 197 - const: s6_p1_backup 198 - const: s6_p2_backup 199 - const: s7_p1_backup 200 - const: s7_p2_backup 201 - const: s8_p1_backup 202 - const: s8_p2_backup 203 - const: s9_p1_backup 204 - const: s9_p2_backup 205 - const: s10_p1_backup 206 - const: s10_p2_backup 207 208 "#qcom,sensors": 209 description: 210 Number of sensors enabled on this platform 211 $ref: /schemas/types.yaml#/definitions/uint32 212 minimum: 1 213 maximum: 16 214 215 "#thermal-sensor-cells": 216 const: 1 217 description: 218 Number of cells required to uniquely identify the thermal sensors. Since 219 we have multiple sensors this is set to 1 220 221required: 222 - compatible 223 - interrupts 224 - interrupt-names 225 - "#thermal-sensor-cells" 226 - "#qcom,sensors" 227 228allOf: 229 - if: 230 properties: 231 compatible: 232 contains: 233 enum: 234 - qcom,ipq8064-tsens 235 - qcom,msm8960-tsens 236 - qcom,tsens-v0_1 237 - qcom,tsens-v1 238 then: 239 properties: 240 interrupts: 241 items: 242 - description: Combined interrupt if upper or lower threshold crossed 243 interrupt-names: 244 items: 245 - const: uplow 246 247 - if: 248 properties: 249 compatible: 250 contains: 251 const: qcom,tsens-v2 252 then: 253 properties: 254 interrupts: 255 items: 256 - description: Combined interrupt if upper or lower threshold crossed 257 - description: Interrupt if critical threshold crossed 258 interrupt-names: 259 items: 260 - const: uplow 261 - const: critical 262 263 - if: 264 properties: 265 compatible: 266 contains: 267 enum: 268 - qcom,ipq8074-tsens 269 then: 270 properties: 271 interrupts: 272 items: 273 - description: Combined interrupt if upper, lower or critical thresholds crossed 274 interrupt-names: 275 items: 276 - const: combined 277 278 - if: 279 properties: 280 compatible: 281 contains: 282 enum: 283 - qcom,ipq8074-tsens 284 - qcom,tsens-v0_1 285 - qcom,tsens-v1 286 - qcom,tsens-v2 287 288 then: 289 required: 290 - reg 291 292additionalProperties: false 293 294examples: 295 - | 296 #include <dt-bindings/interrupt-controller/arm-gic.h> 297 // Example msm9860 based SoC (ipq8064): 298 gcc: clock-controller { 299 300 /* ... */ 301 302 tsens: thermal-sensor { 303 compatible = "qcom,ipq8064-tsens"; 304 305 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 306 nvmem-cell-names = "calib", "calib_backup"; 307 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "uplow"; 309 310 #qcom,sensors = <11>; 311 #thermal-sensor-cells = <1>; 312 }; 313 }; 314 315 - | 316 #include <dt-bindings/interrupt-controller/arm-gic.h> 317 // Example 1 (new calbiration data: for pre v1 IP): 318 thermal-sensor@4a9000 { 319 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 320 reg = <0x4a9000 0x1000>, /* TM */ 321 <0x4a8000 0x1000>; /* SROT */ 322 323 nvmem-cells = <&tsens_mode>, 324 <&tsens_base1>, <&tsens_base2>, 325 <&tsens_s0_p1>, <&tsens_s0_p2>, 326 <&tsens_s1_p1>, <&tsens_s1_p2>, 327 <&tsens_s2_p1>, <&tsens_s2_p2>, 328 <&tsens_s4_p1>, <&tsens_s4_p2>, 329 <&tsens_s5_p1>, <&tsens_s5_p2>; 330 nvmem-cell-names = "mode", 331 "base1", "base2", 332 "s0_p1", "s0_p2", 333 "s1_p1", "s1_p2", 334 "s2_p1", "s2_p2", 335 "s4_p1", "s4_p2", 336 "s5_p1", "s5_p2"; 337 338 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 339 interrupt-names = "uplow"; 340 341 #qcom,sensors = <5>; 342 #thermal-sensor-cells = <1>; 343 }; 344 345 - | 346 #include <dt-bindings/interrupt-controller/arm-gic.h> 347 // Example 1 (legacy: for pre v1 IP): 348 tsens1: thermal-sensor@4a9000 { 349 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 350 reg = <0x4a9000 0x1000>, /* TM */ 351 <0x4a8000 0x1000>; /* SROT */ 352 353 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 354 nvmem-cell-names = "calib", "calib_sel"; 355 356 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "uplow"; 358 359 #qcom,sensors = <5>; 360 #thermal-sensor-cells = <1>; 361 }; 362 363 - | 364 #include <dt-bindings/interrupt-controller/arm-gic.h> 365 // Example 2 (for any platform containing v1 of the TSENS IP): 366 tsens2: thermal-sensor@4a9000 { 367 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 368 reg = <0x004a9000 0x1000>, /* TM */ 369 <0x004a8000 0x1000>; /* SROT */ 370 371 nvmem-cells = <&tsens_caldata>; 372 nvmem-cell-names = "calib"; 373 374 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "uplow"; 376 377 #qcom,sensors = <10>; 378 #thermal-sensor-cells = <1>; 379 }; 380 381 - | 382 #include <dt-bindings/interrupt-controller/arm-gic.h> 383 // Example 3 (for any platform containing v2 of the TSENS IP): 384 tsens3: thermal-sensor@c263000 { 385 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 386 reg = <0xc263000 0x1ff>, 387 <0xc222000 0x1ff>; 388 389 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 391 interrupt-names = "uplow", "critical"; 392 393 #qcom,sensors = <13>; 394 #thermal-sensor-cells = <1>; 395 }; 396 397 - | 398 #include <dt-bindings/interrupt-controller/arm-gic.h> 399 // Example 4 (for any IPQ8074 based SoC-s): 400 tsens4: thermal-sensor@4a9000 { 401 compatible = "qcom,ipq8074-tsens"; 402 reg = <0x4a9000 0x1000>, 403 <0x4a8000 0x1000>; 404 405 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "combined"; 407 408 #qcom,sensors = <16>; 409 #thermal-sensor-cells = <1>; 410 }; 411... 412