1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8916-tsens 33 - qcom,msm8939-tsens 34 - qcom,msm8974-tsens 35 - const: qcom,tsens-v0_1 36 37 - description: v1 of TSENS 38 items: 39 - enum: 40 - qcom,msm8976-tsens 41 - qcom,qcs404-tsens 42 - const: qcom,tsens-v1 43 44 - description: v2 of TSENS 45 items: 46 - enum: 47 - qcom,msm8953-tsens 48 - qcom,msm8996-tsens 49 - qcom,msm8998-tsens 50 - qcom,sc7180-tsens 51 - qcom,sc7280-tsens 52 - qcom,sc8180x-tsens 53 - qcom,sc8280xp-tsens 54 - qcom,sdm630-tsens 55 - qcom,sdm845-tsens 56 - qcom,sm6350-tsens 57 - qcom,sm8150-tsens 58 - qcom,sm8250-tsens 59 - qcom,sm8350-tsens 60 - const: qcom,tsens-v2 61 62 reg: 63 items: 64 - description: TM registers 65 - description: SROT registers 66 67 interrupts: 68 minItems: 1 69 items: 70 - description: Combined interrupt if upper or lower threshold crossed 71 - description: Interrupt if critical threshold crossed 72 73 interrupt-names: 74 minItems: 1 75 items: 76 - const: uplow 77 - const: critical 78 79 nvmem-cells: 80 minItems: 1 81 maxItems: 2 82 description: 83 Reference to an nvmem node for the calibration data 84 85 nvmem-cell-names: 86 minItems: 1 87 items: 88 - const: calib 89 - enum: 90 - calib_backup 91 - calib_sel 92 93 "#qcom,sensors": 94 description: 95 Number of sensors enabled on this platform 96 $ref: /schemas/types.yaml#/definitions/uint32 97 minimum: 1 98 maximum: 16 99 100 "#thermal-sensor-cells": 101 const: 1 102 description: 103 Number of cells required to uniquely identify the thermal sensors. Since 104 we have multiple sensors this is set to 1 105 106required: 107 - compatible 108 - interrupts 109 - interrupt-names 110 - "#thermal-sensor-cells" 111 - "#qcom,sensors" 112 113allOf: 114 - if: 115 properties: 116 compatible: 117 contains: 118 enum: 119 - qcom,ipq8064-tsens 120 - qcom,mdm9607-tsens 121 - qcom,msm8916-tsens 122 - qcom,msm8960-tsens 123 - qcom,msm8974-tsens 124 - qcom,msm8976-tsens 125 - qcom,qcs404-tsens 126 - qcom,tsens-v0_1 127 - qcom,tsens-v1 128 then: 129 properties: 130 interrupts: 131 maxItems: 1 132 interrupt-names: 133 maxItems: 1 134 135 else: 136 properties: 137 interrupts: 138 minItems: 2 139 interrupt-names: 140 minItems: 2 141 142 - if: 143 properties: 144 compatible: 145 contains: 146 enum: 147 - qcom,tsens-v0_1 148 - qcom,tsens-v1 149 - qcom,tsens-v2 150 151 then: 152 required: 153 - reg 154 155additionalProperties: false 156 157examples: 158 - | 159 #include <dt-bindings/interrupt-controller/arm-gic.h> 160 // Example msm9860 based SoC (ipq8064): 161 gcc: clock-controller { 162 163 /* ... */ 164 165 tsens: thermal-sensor { 166 compatible = "qcom,ipq8064-tsens"; 167 168 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 169 nvmem-cell-names = "calib", "calib_backup"; 170 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-names = "uplow"; 172 173 #qcom,sensors = <11>; 174 #thermal-sensor-cells = <1>; 175 }; 176 }; 177 178 - | 179 #include <dt-bindings/interrupt-controller/arm-gic.h> 180 // Example 1 (legacy: for pre v1 IP): 181 tsens1: thermal-sensor@900000 { 182 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 183 reg = <0x4a9000 0x1000>, /* TM */ 184 <0x4a8000 0x1000>; /* SROT */ 185 186 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 187 nvmem-cell-names = "calib", "calib_sel"; 188 189 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 190 interrupt-names = "uplow"; 191 192 #qcom,sensors = <5>; 193 #thermal-sensor-cells = <1>; 194 }; 195 196 - | 197 #include <dt-bindings/interrupt-controller/arm-gic.h> 198 // Example 2 (for any platform containing v1 of the TSENS IP): 199 tsens2: thermal-sensor@4a9000 { 200 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 201 reg = <0x004a9000 0x1000>, /* TM */ 202 <0x004a8000 0x1000>; /* SROT */ 203 204 nvmem-cells = <&tsens_caldata>; 205 nvmem-cell-names = "calib"; 206 207 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-names = "uplow"; 209 210 #qcom,sensors = <10>; 211 #thermal-sensor-cells = <1>; 212 }; 213 214 - | 215 #include <dt-bindings/interrupt-controller/arm-gic.h> 216 // Example 3 (for any platform containing v2 of the TSENS IP): 217 tsens3: thermal-sensor@c263000 { 218 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 219 reg = <0xc263000 0x1ff>, 220 <0xc222000 0x1ff>; 221 222 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 224 interrupt-names = "uplow", "critical"; 225 226 #qcom,sensors = <13>; 227 #thermal-sensor-cells = <1>; 228 }; 229... 230