1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm9860 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 27 - description: v0.1 of TSENS 28 items: 29 - enum: 30 - qcom,mdm9607-tsens 31 - qcom,msm8916-tsens 32 - qcom,msm8939-tsens 33 - qcom,msm8974-tsens 34 - const: qcom,tsens-v0_1 35 36 - description: v1 of TSENS 37 items: 38 - enum: 39 - qcom,msm8976-tsens 40 - qcom,qcs404-tsens 41 - const: qcom,tsens-v1 42 43 - description: v2 of TSENS 44 items: 45 - enum: 46 - qcom,msm8996-tsens 47 - qcom,msm8998-tsens 48 - qcom,sc7180-tsens 49 - qcom,sdm845-tsens 50 - qcom,sm8150-tsens 51 - qcom,sm8250-tsens 52 - qcom,sm8350-tsens 53 - const: qcom,tsens-v2 54 55 reg: 56 items: 57 - description: TM registers 58 - description: SROT registers 59 60 interrupts: 61 minItems: 1 62 items: 63 - description: Combined interrupt if upper or lower threshold crossed 64 - description: Interrupt if critical threshold crossed 65 66 interrupt-names: 67 minItems: 1 68 items: 69 - const: uplow 70 - const: critical 71 72 nvmem-cells: 73 minItems: 1 74 maxItems: 2 75 description: 76 Reference to an nvmem node for the calibration data 77 78 nvmem-cell-names: 79 minItems: 1 80 items: 81 - const: calib 82 - enum: 83 - calib_backup 84 - calib_sel 85 86 "#qcom,sensors": 87 description: 88 Number of sensors enabled on this platform 89 $ref: /schemas/types.yaml#/definitions/uint32 90 minimum: 1 91 maximum: 16 92 93 "#thermal-sensor-cells": 94 const: 1 95 description: 96 Number of cells required to uniquely identify the thermal sensors. Since 97 we have multiple sensors this is set to 1 98 99required: 100 - compatible 101 - interrupts 102 - interrupt-names 103 - "#thermal-sensor-cells" 104 - "#qcom,sensors" 105 106allOf: 107 - if: 108 properties: 109 compatible: 110 contains: 111 enum: 112 - qcom,ipq8064-tsens 113 - qcom,mdm9607-tsens 114 - qcom,msm8916-tsens 115 - qcom,msm8974-tsens 116 - qcom,msm8976-tsens 117 - qcom,qcs404-tsens 118 - qcom,tsens-v0_1 119 - qcom,tsens-v1 120 then: 121 properties: 122 interrupts: 123 maxItems: 1 124 interrupt-names: 125 maxItems: 1 126 127 else: 128 properties: 129 interrupts: 130 minItems: 2 131 interrupt-names: 132 minItems: 2 133 134 - if: 135 properties: 136 compatible: 137 contains: 138 enum: 139 - qcom,tsens-v0_1 140 - qcom,tsens-v1 141 - qcom,tsens-v2 142 143 then: 144 required: 145 - reg 146 147additionalProperties: false 148 149examples: 150 - | 151 #include <dt-bindings/interrupt-controller/arm-gic.h> 152 // Example msm9860 based SoC (ipq8064): 153 gcc: clock-controller { 154 155 /* ... */ 156 157 tsens: thermal-sensor { 158 compatible = "qcom,ipq8064-tsens"; 159 160 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 161 nvmem-cell-names = "calib", "calib_backup"; 162 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "uplow"; 164 165 #qcom,sensors = <11>; 166 #thermal-sensor-cells = <1>; 167 }; 168 }; 169 170 - | 171 #include <dt-bindings/interrupt-controller/arm-gic.h> 172 // Example 1 (legacy: for pre v1 IP): 173 tsens1: thermal-sensor@900000 { 174 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 175 reg = <0x4a9000 0x1000>, /* TM */ 176 <0x4a8000 0x1000>; /* SROT */ 177 178 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 179 nvmem-cell-names = "calib", "calib_sel"; 180 181 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 182 interrupt-names = "uplow"; 183 184 #qcom,sensors = <5>; 185 #thermal-sensor-cells = <1>; 186 }; 187 188 - | 189 #include <dt-bindings/interrupt-controller/arm-gic.h> 190 // Example 2 (for any platform containing v1 of the TSENS IP): 191 tsens2: thermal-sensor@4a9000 { 192 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 193 reg = <0x004a9000 0x1000>, /* TM */ 194 <0x004a8000 0x1000>; /* SROT */ 195 196 nvmem-cells = <&tsens_caldata>; 197 nvmem-cell-names = "calib"; 198 199 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-names = "uplow"; 201 202 #qcom,sensors = <10>; 203 #thermal-sensor-cells = <1>; 204 }; 205 206 - | 207 #include <dt-bindings/interrupt-controller/arm-gic.h> 208 // Example 3 (for any platform containing v2 of the TSENS IP): 209 tsens3: thermal-sensor@c263000 { 210 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 211 reg = <0xc263000 0x1ff>, 212 <0xc222000 0x1ff>; 213 214 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "uplow", "critical"; 217 218 #qcom,sensors = <13>; 219 #thermal-sensor-cells = <1>; 220 }; 221... 222