1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11  - Amit Kucheria <amitk@kernel.org>
12
13description: |
14  QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15  three distinct major versions of the IP that is supported by a single driver.
16  The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17  everything before v1 when there was no versioning information.
18
19properties:
20  compatible:
21    oneOf:
22      - description: msm9860 TSENS based
23        items:
24          - enum:
25              - qcom,ipq8064-tsens
26
27      - description: v0.1 of TSENS
28        items:
29          - enum:
30              - qcom,mdm9607-tsens
31              - qcom,msm8916-tsens
32              - qcom,msm8939-tsens
33              - qcom,msm8974-tsens
34          - const: qcom,tsens-v0_1
35
36      - description: v1 of TSENS
37        items:
38          - enum:
39              - qcom,msm8976-tsens
40              - qcom,qcs404-tsens
41          - const: qcom,tsens-v1
42
43      - description: v2 of TSENS
44        items:
45          - enum:
46              - qcom,msm8996-tsens
47              - qcom,msm8998-tsens
48              - qcom,sc7180-tsens
49              - qcom,sc7280-tsens
50              - qcom,sc8180x-tsens
51              - qcom,sdm630-tsens
52              - qcom,sdm845-tsens
53              - qcom,sm8150-tsens
54              - qcom,sm8250-tsens
55              - qcom,sm8350-tsens
56          - const: qcom,tsens-v2
57
58  reg:
59    items:
60      - description: TM registers
61      - description: SROT registers
62
63  interrupts:
64    minItems: 1
65    items:
66      - description: Combined interrupt if upper or lower threshold crossed
67      - description: Interrupt if critical threshold crossed
68
69  interrupt-names:
70    minItems: 1
71    items:
72      - const: uplow
73      - const: critical
74
75  nvmem-cells:
76    minItems: 1
77    maxItems: 2
78    description:
79      Reference to an nvmem node for the calibration data
80
81  nvmem-cell-names:
82    minItems: 1
83    items:
84      - const: calib
85      - enum:
86          - calib_backup
87          - calib_sel
88
89  "#qcom,sensors":
90    description:
91      Number of sensors enabled on this platform
92    $ref: /schemas/types.yaml#/definitions/uint32
93    minimum: 1
94    maximum: 16
95
96  "#thermal-sensor-cells":
97    const: 1
98    description:
99      Number of cells required to uniquely identify the thermal sensors. Since
100      we have multiple sensors this is set to 1
101
102required:
103  - compatible
104  - interrupts
105  - interrupt-names
106  - "#thermal-sensor-cells"
107  - "#qcom,sensors"
108
109allOf:
110  - if:
111      properties:
112        compatible:
113          contains:
114            enum:
115              - qcom,ipq8064-tsens
116              - qcom,mdm9607-tsens
117              - qcom,msm8916-tsens
118              - qcom,msm8974-tsens
119              - qcom,msm8976-tsens
120              - qcom,qcs404-tsens
121              - qcom,tsens-v0_1
122              - qcom,tsens-v1
123    then:
124      properties:
125        interrupts:
126          maxItems: 1
127        interrupt-names:
128          maxItems: 1
129
130    else:
131      properties:
132        interrupts:
133          minItems: 2
134        interrupt-names:
135          minItems: 2
136
137  - if:
138      properties:
139        compatible:
140          contains:
141            enum:
142              - qcom,tsens-v0_1
143              - qcom,tsens-v1
144              - qcom,tsens-v2
145
146    then:
147      required:
148        - reg
149
150additionalProperties: false
151
152examples:
153  - |
154    #include <dt-bindings/interrupt-controller/arm-gic.h>
155    // Example msm9860 based SoC (ipq8064):
156    gcc: clock-controller {
157
158           /* ... */
159
160           tsens: thermal-sensor {
161                compatible = "qcom,ipq8064-tsens";
162
163                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
164                 nvmem-cell-names = "calib", "calib_backup";
165                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
166                 interrupt-names = "uplow";
167
168                 #qcom,sensors = <11>;
169                 #thermal-sensor-cells = <1>;
170          };
171    };
172
173  - |
174    #include <dt-bindings/interrupt-controller/arm-gic.h>
175    // Example 1 (legacy: for pre v1 IP):
176    tsens1: thermal-sensor@900000 {
177           compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
178           reg = <0x4a9000 0x1000>, /* TM */
179                 <0x4a8000 0x1000>; /* SROT */
180
181           nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
182           nvmem-cell-names = "calib", "calib_sel";
183
184           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
185           interrupt-names = "uplow";
186
187           #qcom,sensors = <5>;
188           #thermal-sensor-cells = <1>;
189    };
190
191  - |
192    #include <dt-bindings/interrupt-controller/arm-gic.h>
193    // Example 2 (for any platform containing v1 of the TSENS IP):
194    tsens2: thermal-sensor@4a9000 {
195          compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
196          reg = <0x004a9000 0x1000>, /* TM */
197                <0x004a8000 0x1000>; /* SROT */
198
199          nvmem-cells = <&tsens_caldata>;
200          nvmem-cell-names = "calib";
201
202          interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
203          interrupt-names = "uplow";
204
205          #qcom,sensors = <10>;
206          #thermal-sensor-cells = <1>;
207    };
208
209  - |
210    #include <dt-bindings/interrupt-controller/arm-gic.h>
211    // Example 3 (for any platform containing v2 of the TSENS IP):
212    tsens3: thermal-sensor@c263000 {
213           compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
214           reg = <0xc263000 0x1ff>,
215                 <0xc222000 0x1ff>;
216
217           interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
218                        <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
219           interrupt-names = "uplow", "critical";
220
221           #qcom,sensors = <13>;
222           #thermal-sensor-cells = <1>;
223    };
224...
225