1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2# Copyright 2019 Linaro Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: QCOM SoC Temperature Sensor (TSENS) 9 10maintainers: 11 - Amit Kucheria <amitk@kernel.org> 12 13description: | 14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently 15 three distinct major versions of the IP that is supported by a single driver. 16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures 17 everything before v1 when there was no versioning information. 18 19properties: 20 compatible: 21 oneOf: 22 - description: msm8960 TSENS based 23 items: 24 - enum: 25 - qcom,ipq8064-tsens 26 - qcom,msm8960-tsens 27 28 - description: v0.1 of TSENS 29 items: 30 - enum: 31 - qcom,mdm9607-tsens 32 - qcom,msm8916-tsens 33 - qcom,msm8939-tsens 34 - qcom,msm8974-tsens 35 - const: qcom,tsens-v0_1 36 37 - description: v1 of TSENS 38 items: 39 - enum: 40 - qcom,msm8976-tsens 41 - qcom,qcs404-tsens 42 - const: qcom,tsens-v1 43 44 - description: v2 of TSENS 45 items: 46 - enum: 47 - qcom,msm8953-tsens 48 - qcom,msm8996-tsens 49 - qcom,msm8998-tsens 50 - qcom,sc7180-tsens 51 - qcom,sc7280-tsens 52 - qcom,sc8180x-tsens 53 - qcom,sc8280xp-tsens 54 - qcom,sdm630-tsens 55 - qcom,sdm845-tsens 56 - qcom,sm6115-tsens 57 - qcom,sm6350-tsens 58 - qcom,sm8150-tsens 59 - qcom,sm8250-tsens 60 - qcom,sm8350-tsens 61 - qcom,sm8450-tsens 62 - qcom,sm8550-tsens 63 - const: qcom,tsens-v2 64 65 - description: v2 of TSENS with combined interrupt 66 enum: 67 - qcom,ipq8074-tsens 68 69 reg: 70 items: 71 - description: TM registers 72 - description: SROT registers 73 74 interrupts: 75 minItems: 1 76 maxItems: 2 77 78 interrupt-names: 79 minItems: 1 80 maxItems: 2 81 82 nvmem-cells: 83 minItems: 1 84 maxItems: 2 85 description: 86 Reference to an nvmem node for the calibration data 87 88 nvmem-cell-names: 89 minItems: 1 90 items: 91 - const: calib 92 - enum: 93 - calib_backup 94 - calib_sel 95 96 "#qcom,sensors": 97 description: 98 Number of sensors enabled on this platform 99 $ref: /schemas/types.yaml#/definitions/uint32 100 minimum: 1 101 maximum: 16 102 103 "#thermal-sensor-cells": 104 const: 1 105 description: 106 Number of cells required to uniquely identify the thermal sensors. Since 107 we have multiple sensors this is set to 1 108 109required: 110 - compatible 111 - interrupts 112 - interrupt-names 113 - "#thermal-sensor-cells" 114 - "#qcom,sensors" 115 116allOf: 117 - if: 118 properties: 119 compatible: 120 contains: 121 enum: 122 - qcom,ipq8064-tsens 123 - qcom,mdm9607-tsens 124 - qcom,msm8916-tsens 125 - qcom,msm8960-tsens 126 - qcom,msm8974-tsens 127 - qcom,msm8976-tsens 128 - qcom,qcs404-tsens 129 - qcom,tsens-v0_1 130 - qcom,tsens-v1 131 then: 132 properties: 133 interrupts: 134 items: 135 - description: Combined interrupt if upper or lower threshold crossed 136 interrupt-names: 137 items: 138 - const: uplow 139 140 - if: 141 properties: 142 compatible: 143 contains: 144 enum: 145 - qcom,msm8953-tsens 146 - qcom,msm8996-tsens 147 - qcom,msm8998-tsens 148 - qcom,sc7180-tsens 149 - qcom,sc7280-tsens 150 - qcom,sc8180x-tsens 151 - qcom,sc8280xp-tsens 152 - qcom,sdm630-tsens 153 - qcom,sdm845-tsens 154 - qcom,sm6350-tsens 155 - qcom,sm8150-tsens 156 - qcom,sm8250-tsens 157 - qcom,sm8350-tsens 158 - qcom,sm8450-tsens 159 - qcom,tsens-v2 160 then: 161 properties: 162 interrupts: 163 items: 164 - description: Combined interrupt if upper or lower threshold crossed 165 - description: Interrupt if critical threshold crossed 166 interrupt-names: 167 items: 168 - const: uplow 169 - const: critical 170 171 - if: 172 properties: 173 compatible: 174 contains: 175 enum: 176 - qcom,ipq8074-tsens 177 then: 178 properties: 179 interrupts: 180 items: 181 - description: Combined interrupt if upper, lower or critical thresholds crossed 182 interrupt-names: 183 items: 184 - const: combined 185 186 - if: 187 properties: 188 compatible: 189 contains: 190 enum: 191 - qcom,ipq8074-tsens 192 - qcom,tsens-v0_1 193 - qcom,tsens-v1 194 - qcom,tsens-v2 195 196 then: 197 required: 198 - reg 199 200additionalProperties: false 201 202examples: 203 - | 204 #include <dt-bindings/interrupt-controller/arm-gic.h> 205 // Example msm9860 based SoC (ipq8064): 206 gcc: clock-controller { 207 208 /* ... */ 209 210 tsens: thermal-sensor { 211 compatible = "qcom,ipq8064-tsens"; 212 213 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 214 nvmem-cell-names = "calib", "calib_backup"; 215 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "uplow"; 217 218 #qcom,sensors = <11>; 219 #thermal-sensor-cells = <1>; 220 }; 221 }; 222 223 - | 224 #include <dt-bindings/interrupt-controller/arm-gic.h> 225 // Example 1 (legacy: for pre v1 IP): 226 tsens1: thermal-sensor@900000 { 227 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 228 reg = <0x4a9000 0x1000>, /* TM */ 229 <0x4a8000 0x1000>; /* SROT */ 230 231 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 232 nvmem-cell-names = "calib", "calib_sel"; 233 234 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "uplow"; 236 237 #qcom,sensors = <5>; 238 #thermal-sensor-cells = <1>; 239 }; 240 241 - | 242 #include <dt-bindings/interrupt-controller/arm-gic.h> 243 // Example 2 (for any platform containing v1 of the TSENS IP): 244 tsens2: thermal-sensor@4a9000 { 245 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 246 reg = <0x004a9000 0x1000>, /* TM */ 247 <0x004a8000 0x1000>; /* SROT */ 248 249 nvmem-cells = <&tsens_caldata>; 250 nvmem-cell-names = "calib"; 251 252 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "uplow"; 254 255 #qcom,sensors = <10>; 256 #thermal-sensor-cells = <1>; 257 }; 258 259 - | 260 #include <dt-bindings/interrupt-controller/arm-gic.h> 261 // Example 3 (for any platform containing v2 of the TSENS IP): 262 tsens3: thermal-sensor@c263000 { 263 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 264 reg = <0xc263000 0x1ff>, 265 <0xc222000 0x1ff>; 266 267 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-names = "uplow", "critical"; 270 271 #qcom,sensors = <13>; 272 #thermal-sensor-cells = <1>; 273 }; 274 275 - | 276 #include <dt-bindings/interrupt-controller/arm-gic.h> 277 // Example 4 (for any IPQ8074 based SoC-s): 278 tsens4: thermal-sensor@4a9000 { 279 compatible = "qcom,ipq8074-tsens"; 280 reg = <0x4a9000 0x1000>, 281 <0x4a8000 0x1000>; 282 283 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-names = "combined"; 285 286 #qcom,sensors = <16>; 287 #thermal-sensor-cells = <1>; 288 }; 289... 290