1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11  - Amit Kucheria <amitk@kernel.org>
12
13description: |
14  QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15  three distinct major versions of the IP that is supported by a single driver.
16  The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17  everything before v1 when there was no versioning information.
18
19properties:
20  compatible:
21    oneOf:
22      - description: msm8960 TSENS based
23        items:
24          - enum:
25              - qcom,ipq8064-tsens
26              - qcom,msm8960-tsens
27
28      - description: v0.1 of TSENS
29        items:
30          - enum:
31              - qcom,mdm9607-tsens
32              - qcom,msm8916-tsens
33              - qcom,msm8939-tsens
34              - qcom,msm8974-tsens
35          - const: qcom,tsens-v0_1
36
37      - description: v1 of TSENS
38        items:
39          - enum:
40              - qcom,msm8956-tsens
41              - qcom,msm8976-tsens
42              - qcom,qcs404-tsens
43          - const: qcom,tsens-v1
44
45      - description: v2 of TSENS
46        items:
47          - enum:
48              - qcom,msm8953-tsens
49              - qcom,msm8996-tsens
50              - qcom,msm8998-tsens
51              - qcom,qcm2290-tsens
52              - qcom,sc7180-tsens
53              - qcom,sc7280-tsens
54              - qcom,sc8180x-tsens
55              - qcom,sc8280xp-tsens
56              - qcom,sdm630-tsens
57              - qcom,sdm845-tsens
58              - qcom,sm6115-tsens
59              - qcom,sm6350-tsens
60              - qcom,sm6375-tsens
61              - qcom,sm8150-tsens
62              - qcom,sm8250-tsens
63              - qcom,sm8350-tsens
64              - qcom,sm8450-tsens
65              - qcom,sm8550-tsens
66          - const: qcom,tsens-v2
67
68      - description: v2 of TSENS with combined interrupt
69        enum:
70          - qcom,ipq8074-tsens
71
72  reg:
73    items:
74      - description: TM registers
75      - description: SROT registers
76
77  interrupts:
78    minItems: 1
79    maxItems: 2
80
81  interrupt-names:
82    minItems: 1
83    maxItems: 2
84
85  nvmem-cells:
86    oneOf:
87      - minItems: 1
88        maxItems: 2
89        description:
90          Reference to an nvmem node for the calibration data
91      - minItems: 5
92        maxItems: 35
93        description: |
94          Reference to nvmem cells for the calibration mode, two calibration
95          bases and two cells per each sensor
96        # special case for msm8974 / apq8084
97      - maxItems: 51
98        description: |
99          Reference to nvmem cells for the calibration mode, two calibration
100          bases and two cells per each sensor, main and backup copies, plus use_backup cell
101
102  nvmem-cell-names:
103    oneOf:
104      - minItems: 1
105        items:
106          - const: calib
107          - enum:
108              - calib_backup
109              - calib_sel
110      - minItems: 5
111        items:
112          - const: mode
113          - const: base1
114          - const: base2
115          - pattern: '^s[0-9]+_p1$'
116          - pattern: '^s[0-9]+_p2$'
117          - pattern: '^s[0-9]+_p1$'
118          - pattern: '^s[0-9]+_p2$'
119          - pattern: '^s[0-9]+_p1$'
120          - pattern: '^s[0-9]+_p2$'
121          - pattern: '^s[0-9]+_p1$'
122          - pattern: '^s[0-9]+_p2$'
123          - pattern: '^s[0-9]+_p1$'
124          - pattern: '^s[0-9]+_p2$'
125          - pattern: '^s[0-9]+_p1$'
126          - pattern: '^s[0-9]+_p2$'
127          - pattern: '^s[0-9]+_p1$'
128          - pattern: '^s[0-9]+_p2$'
129          - pattern: '^s[0-9]+_p1$'
130          - pattern: '^s[0-9]+_p2$'
131          - pattern: '^s[0-9]+_p1$'
132          - pattern: '^s[0-9]+_p2$'
133          - pattern: '^s[0-9]+_p1$'
134          - pattern: '^s[0-9]+_p2$'
135          - pattern: '^s[0-9]+_p1$'
136          - pattern: '^s[0-9]+_p2$'
137          - pattern: '^s[0-9]+_p1$'
138          - pattern: '^s[0-9]+_p2$'
139          - pattern: '^s[0-9]+_p1$'
140          - pattern: '^s[0-9]+_p2$'
141          - pattern: '^s[0-9]+_p1$'
142          - pattern: '^s[0-9]+_p2$'
143          - pattern: '^s[0-9]+_p1$'
144          - pattern: '^s[0-9]+_p2$'
145          - pattern: '^s[0-9]+_p1$'
146          - pattern: '^s[0-9]+_p2$'
147        # special case for msm8974 / apq8084
148      - items:
149          - const: mode
150          - const: base1
151          - const: base2
152          - const: use_backup
153          - const: mode_backup
154          - const: base1_backup
155          - const: base2_backup
156          - const: s0_p1
157          - const: s0_p2
158          - const: s1_p1
159          - const: s1_p2
160          - const: s2_p1
161          - const: s2_p2
162          - const: s3_p1
163          - const: s3_p2
164          - const: s4_p1
165          - const: s4_p2
166          - const: s5_p1
167          - const: s5_p2
168          - const: s6_p1
169          - const: s6_p2
170          - const: s7_p1
171          - const: s7_p2
172          - const: s8_p1
173          - const: s8_p2
174          - const: s9_p1
175          - const: s9_p2
176          - const: s10_p1
177          - const: s10_p2
178          - const: s0_p1_backup
179          - const: s0_p2_backup
180          - const: s1_p1_backup
181          - const: s1_p2_backup
182          - const: s2_p1_backup
183          - const: s2_p2_backup
184          - const: s3_p1_backup
185          - const: s3_p2_backup
186          - const: s4_p1_backup
187          - const: s4_p2_backup
188          - const: s5_p1_backup
189          - const: s5_p2_backup
190          - const: s6_p1_backup
191          - const: s6_p2_backup
192          - const: s7_p1_backup
193          - const: s7_p2_backup
194          - const: s8_p1_backup
195          - const: s8_p2_backup
196          - const: s9_p1_backup
197          - const: s9_p2_backup
198          - const: s10_p1_backup
199          - const: s10_p2_backup
200
201  "#qcom,sensors":
202    description:
203      Number of sensors enabled on this platform
204    $ref: /schemas/types.yaml#/definitions/uint32
205    minimum: 1
206    maximum: 16
207
208  "#thermal-sensor-cells":
209    const: 1
210    description:
211      Number of cells required to uniquely identify the thermal sensors. Since
212      we have multiple sensors this is set to 1
213
214required:
215  - compatible
216  - interrupts
217  - interrupt-names
218  - "#thermal-sensor-cells"
219  - "#qcom,sensors"
220
221allOf:
222  - if:
223      properties:
224        compatible:
225          contains:
226            enum:
227              - qcom,ipq8064-tsens
228              - qcom,mdm9607-tsens
229              - qcom,msm8916-tsens
230              - qcom,msm8960-tsens
231              - qcom,msm8974-tsens
232              - qcom,msm8976-tsens
233              - qcom,qcs404-tsens
234              - qcom,tsens-v0_1
235              - qcom,tsens-v1
236    then:
237      properties:
238        interrupts:
239          items:
240            - description: Combined interrupt if upper or lower threshold crossed
241        interrupt-names:
242          items:
243            - const: uplow
244
245  - if:
246      properties:
247        compatible:
248          contains:
249            enum:
250              - qcom,msm8953-tsens
251              - qcom,msm8996-tsens
252              - qcom,msm8998-tsens
253              - qcom,sc7180-tsens
254              - qcom,sc7280-tsens
255              - qcom,sc8180x-tsens
256              - qcom,sc8280xp-tsens
257              - qcom,sdm630-tsens
258              - qcom,sdm845-tsens
259              - qcom,sm6350-tsens
260              - qcom,sm8150-tsens
261              - qcom,sm8250-tsens
262              - qcom,sm8350-tsens
263              - qcom,sm8450-tsens
264              - qcom,tsens-v2
265    then:
266      properties:
267        interrupts:
268          items:
269            - description: Combined interrupt if upper or lower threshold crossed
270            - description: Interrupt if critical threshold crossed
271        interrupt-names:
272          items:
273            - const: uplow
274            - const: critical
275
276  - if:
277      properties:
278        compatible:
279          contains:
280            enum:
281              - qcom,ipq8074-tsens
282    then:
283      properties:
284        interrupts:
285          items:
286            - description: Combined interrupt if upper, lower or critical thresholds crossed
287        interrupt-names:
288          items:
289            - const: combined
290
291  - if:
292      properties:
293        compatible:
294          contains:
295            enum:
296              - qcom,ipq8074-tsens
297              - qcom,tsens-v0_1
298              - qcom,tsens-v1
299              - qcom,tsens-v2
300
301    then:
302      required:
303        - reg
304
305additionalProperties: false
306
307examples:
308  - |
309    #include <dt-bindings/interrupt-controller/arm-gic.h>
310    // Example msm9860 based SoC (ipq8064):
311    gcc: clock-controller {
312
313           /* ... */
314
315           tsens: thermal-sensor {
316                compatible = "qcom,ipq8064-tsens";
317
318                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
319                 nvmem-cell-names = "calib", "calib_backup";
320                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
321                 interrupt-names = "uplow";
322
323                 #qcom,sensors = <11>;
324                 #thermal-sensor-cells = <1>;
325          };
326    };
327
328  - |
329    #include <dt-bindings/interrupt-controller/arm-gic.h>
330    // Example 1 (new calbiration data: for pre v1 IP):
331    thermal-sensor@4a9000 {
332        compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
333        reg = <0x4a9000 0x1000>, /* TM */
334              <0x4a8000 0x1000>; /* SROT */
335
336        nvmem-cells = <&tsens_mode>,
337                      <&tsens_base1>, <&tsens_base2>,
338                      <&tsens_s0_p1>, <&tsens_s0_p2>,
339                      <&tsens_s1_p1>, <&tsens_s1_p2>,
340                      <&tsens_s2_p1>, <&tsens_s2_p2>,
341                      <&tsens_s4_p1>, <&tsens_s4_p2>,
342                      <&tsens_s5_p1>, <&tsens_s5_p2>;
343        nvmem-cell-names = "mode",
344                           "base1", "base2",
345                           "s0_p1", "s0_p2",
346                           "s1_p1", "s1_p2",
347                           "s2_p1", "s2_p2",
348                           "s4_p1", "s4_p2",
349                           "s5_p1", "s5_p2";
350
351        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
352        interrupt-names = "uplow";
353
354        #qcom,sensors = <5>;
355        #thermal-sensor-cells = <1>;
356    };
357
358  - |
359    #include <dt-bindings/interrupt-controller/arm-gic.h>
360    // Example 1 (legacy: for pre v1 IP):
361    tsens1: thermal-sensor@4a9000 {
362           compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
363           reg = <0x4a9000 0x1000>, /* TM */
364                 <0x4a8000 0x1000>; /* SROT */
365
366           nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
367           nvmem-cell-names = "calib", "calib_sel";
368
369           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
370           interrupt-names = "uplow";
371
372           #qcom,sensors = <5>;
373           #thermal-sensor-cells = <1>;
374    };
375
376  - |
377    #include <dt-bindings/interrupt-controller/arm-gic.h>
378    // Example 2 (for any platform containing v1 of the TSENS IP):
379    tsens2: thermal-sensor@4a9000 {
380          compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
381          reg = <0x004a9000 0x1000>, /* TM */
382                <0x004a8000 0x1000>; /* SROT */
383
384          nvmem-cells = <&tsens_caldata>;
385          nvmem-cell-names = "calib";
386
387          interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
388          interrupt-names = "uplow";
389
390          #qcom,sensors = <10>;
391          #thermal-sensor-cells = <1>;
392    };
393
394  - |
395    #include <dt-bindings/interrupt-controller/arm-gic.h>
396    // Example 3 (for any platform containing v2 of the TSENS IP):
397    tsens3: thermal-sensor@c263000 {
398           compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
399           reg = <0xc263000 0x1ff>,
400                 <0xc222000 0x1ff>;
401
402           interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
403                        <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
404           interrupt-names = "uplow", "critical";
405
406           #qcom,sensors = <13>;
407           #thermal-sensor-cells = <1>;
408    };
409
410  - |
411    #include <dt-bindings/interrupt-controller/arm-gic.h>
412    // Example 4 (for any IPQ8074 based SoC-s):
413    tsens4: thermal-sensor@4a9000 {
414           compatible = "qcom,ipq8074-tsens";
415           reg = <0x4a9000 0x1000>,
416                 <0x4a8000 0x1000>;
417
418           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
419           interrupt-names = "combined";
420
421           #qcom,sensors = <16>;
422           #thermal-sensor-cells = <1>;
423    };
424...
425