1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11  - Amit Kucheria <amitk@kernel.org>
12
13description: |
14  QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15  three distinct major versions of the IP that is supported by a single driver.
16  The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17  everything before v1 when there was no versioning information.
18
19properties:
20  compatible:
21    oneOf:
22      - description: msm8960 TSENS based
23        items:
24          - enum:
25              - qcom,ipq8064-tsens
26              - qcom,msm8960-tsens
27
28      - description: v0.1 of TSENS
29        items:
30          - enum:
31              - qcom,mdm9607-tsens
32              - qcom,msm8916-tsens
33              - qcom,msm8939-tsens
34              - qcom,msm8974-tsens
35          - const: qcom,tsens-v0_1
36
37      - description: v1 of TSENS
38        items:
39          - enum:
40              - qcom,msm8956-tsens
41              - qcom,msm8976-tsens
42              - qcom,qcs404-tsens
43          - const: qcom,tsens-v1
44
45      - description: v2 of TSENS
46        items:
47          - enum:
48              - qcom,msm8953-tsens
49              - qcom,msm8996-tsens
50              - qcom,msm8998-tsens
51              - qcom,qcm2290-tsens
52              - qcom,sc7180-tsens
53              - qcom,sc7280-tsens
54              - qcom,sc8180x-tsens
55              - qcom,sc8280xp-tsens
56              - qcom,sdm630-tsens
57              - qcom,sdm845-tsens
58              - qcom,sm6115-tsens
59              - qcom,sm6350-tsens
60              - qcom,sm8150-tsens
61              - qcom,sm8250-tsens
62              - qcom,sm8350-tsens
63              - qcom,sm8450-tsens
64              - qcom,sm8550-tsens
65          - const: qcom,tsens-v2
66
67      - description: v2 of TSENS with combined interrupt
68        enum:
69          - qcom,ipq8074-tsens
70
71  reg:
72    items:
73      - description: TM registers
74      - description: SROT registers
75
76  interrupts:
77    minItems: 1
78    maxItems: 2
79
80  interrupt-names:
81    minItems: 1
82    maxItems: 2
83
84  nvmem-cells:
85    oneOf:
86      - minItems: 1
87        maxItems: 2
88        description:
89          Reference to an nvmem node for the calibration data
90      - minItems: 5
91        maxItems: 35
92        description: |
93          Reference to nvmem cells for the calibration mode, two calibration
94          bases and two cells per each sensor
95        # special case for msm8974 / apq8084
96      - maxItems: 51
97        description: |
98          Reference to nvmem cells for the calibration mode, two calibration
99          bases and two cells per each sensor, main and backup copies, plus use_backup cell
100
101  nvmem-cell-names:
102    oneOf:
103      - minItems: 1
104        items:
105          - const: calib
106          - enum:
107              - calib_backup
108              - calib_sel
109      - minItems: 5
110        items:
111          - const: mode
112          - const: base1
113          - const: base2
114          - pattern: '^s[0-9]+_p1$'
115          - pattern: '^s[0-9]+_p2$'
116          - pattern: '^s[0-9]+_p1$'
117          - pattern: '^s[0-9]+_p2$'
118          - pattern: '^s[0-9]+_p1$'
119          - pattern: '^s[0-9]+_p2$'
120          - pattern: '^s[0-9]+_p1$'
121          - pattern: '^s[0-9]+_p2$'
122          - pattern: '^s[0-9]+_p1$'
123          - pattern: '^s[0-9]+_p2$'
124          - pattern: '^s[0-9]+_p1$'
125          - pattern: '^s[0-9]+_p2$'
126          - pattern: '^s[0-9]+_p1$'
127          - pattern: '^s[0-9]+_p2$'
128          - pattern: '^s[0-9]+_p1$'
129          - pattern: '^s[0-9]+_p2$'
130          - pattern: '^s[0-9]+_p1$'
131          - pattern: '^s[0-9]+_p2$'
132          - pattern: '^s[0-9]+_p1$'
133          - pattern: '^s[0-9]+_p2$'
134          - pattern: '^s[0-9]+_p1$'
135          - pattern: '^s[0-9]+_p2$'
136          - pattern: '^s[0-9]+_p1$'
137          - pattern: '^s[0-9]+_p2$'
138          - pattern: '^s[0-9]+_p1$'
139          - pattern: '^s[0-9]+_p2$'
140          - pattern: '^s[0-9]+_p1$'
141          - pattern: '^s[0-9]+_p2$'
142          - pattern: '^s[0-9]+_p1$'
143          - pattern: '^s[0-9]+_p2$'
144          - pattern: '^s[0-9]+_p1$'
145          - pattern: '^s[0-9]+_p2$'
146        # special case for msm8974 / apq8084
147      - items:
148          - const: mode
149          - const: base1
150          - const: base2
151          - const: use_backup
152          - const: mode_backup
153          - const: base1_backup
154          - const: base2_backup
155          - const: s0_p1
156          - const: s0_p2
157          - const: s1_p1
158          - const: s1_p2
159          - const: s2_p1
160          - const: s2_p2
161          - const: s3_p1
162          - const: s3_p2
163          - const: s4_p1
164          - const: s4_p2
165          - const: s5_p1
166          - const: s5_p2
167          - const: s6_p1
168          - const: s6_p2
169          - const: s7_p1
170          - const: s7_p2
171          - const: s8_p1
172          - const: s8_p2
173          - const: s9_p1
174          - const: s9_p2
175          - const: s10_p1
176          - const: s10_p2
177          - const: s0_p1_backup
178          - const: s0_p2_backup
179          - const: s1_p1_backup
180          - const: s1_p2_backup
181          - const: s2_p1_backup
182          - const: s2_p2_backup
183          - const: s3_p1_backup
184          - const: s3_p2_backup
185          - const: s4_p1_backup
186          - const: s4_p2_backup
187          - const: s5_p1_backup
188          - const: s5_p2_backup
189          - const: s6_p1_backup
190          - const: s6_p2_backup
191          - const: s7_p1_backup
192          - const: s7_p2_backup
193          - const: s8_p1_backup
194          - const: s8_p2_backup
195          - const: s9_p1_backup
196          - const: s9_p2_backup
197          - const: s10_p1_backup
198          - const: s10_p2_backup
199
200  "#qcom,sensors":
201    description:
202      Number of sensors enabled on this platform
203    $ref: /schemas/types.yaml#/definitions/uint32
204    minimum: 1
205    maximum: 16
206
207  "#thermal-sensor-cells":
208    const: 1
209    description:
210      Number of cells required to uniquely identify the thermal sensors. Since
211      we have multiple sensors this is set to 1
212
213required:
214  - compatible
215  - interrupts
216  - interrupt-names
217  - "#thermal-sensor-cells"
218  - "#qcom,sensors"
219
220allOf:
221  - if:
222      properties:
223        compatible:
224          contains:
225            enum:
226              - qcom,ipq8064-tsens
227              - qcom,mdm9607-tsens
228              - qcom,msm8916-tsens
229              - qcom,msm8960-tsens
230              - qcom,msm8974-tsens
231              - qcom,msm8976-tsens
232              - qcom,qcs404-tsens
233              - qcom,tsens-v0_1
234              - qcom,tsens-v1
235    then:
236      properties:
237        interrupts:
238          items:
239            - description: Combined interrupt if upper or lower threshold crossed
240        interrupt-names:
241          items:
242            - const: uplow
243
244  - if:
245      properties:
246        compatible:
247          contains:
248            enum:
249              - qcom,msm8953-tsens
250              - qcom,msm8996-tsens
251              - qcom,msm8998-tsens
252              - qcom,sc7180-tsens
253              - qcom,sc7280-tsens
254              - qcom,sc8180x-tsens
255              - qcom,sc8280xp-tsens
256              - qcom,sdm630-tsens
257              - qcom,sdm845-tsens
258              - qcom,sm6350-tsens
259              - qcom,sm8150-tsens
260              - qcom,sm8250-tsens
261              - qcom,sm8350-tsens
262              - qcom,sm8450-tsens
263              - qcom,tsens-v2
264    then:
265      properties:
266        interrupts:
267          items:
268            - description: Combined interrupt if upper or lower threshold crossed
269            - description: Interrupt if critical threshold crossed
270        interrupt-names:
271          items:
272            - const: uplow
273            - const: critical
274
275  - if:
276      properties:
277        compatible:
278          contains:
279            enum:
280              - qcom,ipq8074-tsens
281    then:
282      properties:
283        interrupts:
284          items:
285            - description: Combined interrupt if upper, lower or critical thresholds crossed
286        interrupt-names:
287          items:
288            - const: combined
289
290  - if:
291      properties:
292        compatible:
293          contains:
294            enum:
295              - qcom,ipq8074-tsens
296              - qcom,tsens-v0_1
297              - qcom,tsens-v1
298              - qcom,tsens-v2
299
300    then:
301      required:
302        - reg
303
304additionalProperties: false
305
306examples:
307  - |
308    #include <dt-bindings/interrupt-controller/arm-gic.h>
309    // Example msm9860 based SoC (ipq8064):
310    gcc: clock-controller {
311
312           /* ... */
313
314           tsens: thermal-sensor {
315                compatible = "qcom,ipq8064-tsens";
316
317                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
318                 nvmem-cell-names = "calib", "calib_backup";
319                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
320                 interrupt-names = "uplow";
321
322                 #qcom,sensors = <11>;
323                 #thermal-sensor-cells = <1>;
324          };
325    };
326
327  - |
328    #include <dt-bindings/interrupt-controller/arm-gic.h>
329    // Example 1 (new calbiration data: for pre v1 IP):
330    thermal-sensor@4a9000 {
331        compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
332        reg = <0x4a9000 0x1000>, /* TM */
333              <0x4a8000 0x1000>; /* SROT */
334
335        nvmem-cells = <&tsens_mode>,
336                      <&tsens_base1>, <&tsens_base2>,
337                      <&tsens_s0_p1>, <&tsens_s0_p2>,
338                      <&tsens_s1_p1>, <&tsens_s1_p2>,
339                      <&tsens_s2_p1>, <&tsens_s2_p2>,
340                      <&tsens_s4_p1>, <&tsens_s4_p2>,
341                      <&tsens_s5_p1>, <&tsens_s5_p2>;
342        nvmem-cell-names = "mode",
343                           "base1", "base2",
344                           "s0_p1", "s0_p2",
345                           "s1_p1", "s1_p2",
346                           "s2_p1", "s2_p2",
347                           "s4_p1", "s4_p2",
348                           "s5_p1", "s5_p2";
349
350        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
351        interrupt-names = "uplow";
352
353        #qcom,sensors = <5>;
354        #thermal-sensor-cells = <1>;
355    };
356
357  - |
358    #include <dt-bindings/interrupt-controller/arm-gic.h>
359    // Example 1 (legacy: for pre v1 IP):
360    tsens1: thermal-sensor@4a9000 {
361           compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
362           reg = <0x4a9000 0x1000>, /* TM */
363                 <0x4a8000 0x1000>; /* SROT */
364
365           nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
366           nvmem-cell-names = "calib", "calib_sel";
367
368           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
369           interrupt-names = "uplow";
370
371           #qcom,sensors = <5>;
372           #thermal-sensor-cells = <1>;
373    };
374
375  - |
376    #include <dt-bindings/interrupt-controller/arm-gic.h>
377    // Example 2 (for any platform containing v1 of the TSENS IP):
378    tsens2: thermal-sensor@4a9000 {
379          compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
380          reg = <0x004a9000 0x1000>, /* TM */
381                <0x004a8000 0x1000>; /* SROT */
382
383          nvmem-cells = <&tsens_caldata>;
384          nvmem-cell-names = "calib";
385
386          interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
387          interrupt-names = "uplow";
388
389          #qcom,sensors = <10>;
390          #thermal-sensor-cells = <1>;
391    };
392
393  - |
394    #include <dt-bindings/interrupt-controller/arm-gic.h>
395    // Example 3 (for any platform containing v2 of the TSENS IP):
396    tsens3: thermal-sensor@c263000 {
397           compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
398           reg = <0xc263000 0x1ff>,
399                 <0xc222000 0x1ff>;
400
401           interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
402                        <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
403           interrupt-names = "uplow", "critical";
404
405           #qcom,sensors = <13>;
406           #thermal-sensor-cells = <1>;
407    };
408
409  - |
410    #include <dt-bindings/interrupt-controller/arm-gic.h>
411    // Example 4 (for any IPQ8074 based SoC-s):
412    tsens4: thermal-sensor@4a9000 {
413           compatible = "qcom,ipq8074-tsens";
414           reg = <0x4a9000 0x1000>,
415                 <0x4a8000 0x1000>;
416
417           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
418           interrupt-names = "combined";
419
420           #qcom,sensors = <16>;
421           #thermal-sensor-cells = <1>;
422    };
423...
424