1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MDM9607 TLMM block
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@somainline.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,mdm9607-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts: true
26  interrupt-controller: true
27  "#interrupt-cells": true
28  gpio-controller: true
29  gpio-reserved-ranges: true
30  "#gpio-cells": true
31  gpio-ranges: true
32  wakeup-parent: true
33
34required:
35  - compatible
36  - reg
37
38additionalProperties: false
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
44      - patternProperties:
45          ".*":
46            $ref: "#/$defs/qcom-mdm9607-tlmm-state"
47
48$defs:
49  qcom-mdm9607-tlmm-state:
50    type: object
51    description:
52      Pinctrl node's client devices use subnodes for desired pin configuration.
53      Client device subnodes use below standard properties.
54    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55
56    properties:
57      pins:
58        description:
59          List of gpio pins affected by the properties specified in this
60          subnode.
61        items:
62          oneOf:
63            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
64            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
65                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
66                      qdsd_data3 ]
67        minItems: 1
68        maxItems: 16
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
76                atest_char1, atest_char2, atest_char3,
77                atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
78                atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
79                bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
80                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
81                blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
82                blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
83                blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
84                codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
85                cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
86                ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
87                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
88                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
89                gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
90                nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
91                nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
92                pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
93                pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
94                ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
95                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
96                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
97                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
98                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
99                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
100                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
101                rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
102                sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
103                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
104                uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
105
106      bias-disable: true
107      bias-pull-down: true
108      bias-pull-up: true
109      drive-strength: true
110      input-enable: true
111      output-high: true
112      output-low: true
113
114    required:
115      - pins
116
117    additionalProperties: false
118
119examples:
120  - |
121    #include <dt-bindings/interrupt-controller/arm-gic.h>
122    tlmm: pinctrl@1000000 {
123        compatible = "qcom,mdm9607-tlmm";
124        reg = <0x01000000 0x300000>;
125        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
126        gpio-controller;
127        gpio-ranges = <&msmgpio 0 0 80>;
128        #gpio-cells = <2>;
129        interrupt-controller;
130        #interrupt-cells = <2>;
131    };
132