1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. MDM9607 TLMM block
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@somainline.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,mdm9607-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31  gpio-reserved-ranges: true
32  "#gpio-cells": true
33  gpio-ranges: true
34  wakeup-parent: true
35
36required:
37  - compatible
38  - reg
39
40additionalProperties: false
41
42patternProperties:
43  "-state$":
44    oneOf:
45      - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
46      - patternProperties:
47          ".*":
48            $ref: "#/$defs/qcom-mdm9607-tlmm-state"
49
50$defs:
51  qcom-mdm9607-tlmm-state:
52    type: object
53    description:
54      Pinctrl node's client devices use subnodes for desired pin configuration.
55      Client device subnodes use below standard properties.
56    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
57    unevaluatedProperties: false
58
59    properties:
60      pins:
61        description:
62          List of gpio pins affected by the properties specified in this
63          subnode.
64        items:
65          oneOf:
66            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
67            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
68                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
69                      qdsd_data3 ]
70        minItems: 1
71        maxItems: 16
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77
78        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
79                atest_char1, atest_char2, atest_char3,
80                atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
81                atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
82                bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
83                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
84                blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
85                blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
86                blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
87                codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
88                cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
89                ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
90                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
91                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
92                gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
93                nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
94                nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
95                pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
96                pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
97                ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
98                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
99                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
100                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
101                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
102                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
103                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
104                rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
105                sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
106                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
107                uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]
108
109    required:
110      - pins
111
112examples:
113  - |
114    #include <dt-bindings/interrupt-controller/arm-gic.h>
115    tlmm: pinctrl@1000000 {
116        compatible = "qcom,mdm9607-tlmm";
117        reg = <0x01000000 0x300000>;
118        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
119        gpio-controller;
120        gpio-ranges = <&msmgpio 0 0 80>;
121        #gpio-cells = <2>;
122        interrupt-controller;
123        #interrupt-cells = <2>;
124    };
125