1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-ufs-phy
20      - qcom,sm6125-qmp-ufs-phy
21      - qcom,sm8550-qmp-ufs-phy
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    maxItems: 2
28
29  clock-names:
30    items:
31      - const: ref
32      - const: ref_aux
33
34  power-domains:
35    maxItems: 1
36
37  resets:
38    maxItems: 1
39
40  reset-names:
41    items:
42      - const: ufsphy
43
44  vdda-phy-supply: true
45
46  vdda-pll-supply: true
47
48  "#clock-cells":
49    const: 1
50
51  "#phy-cells":
52    const: 0
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - power-domains
60  - resets
61  - reset-names
62  - vdda-phy-supply
63  - vdda-pll-supply
64  - "#phy-cells"
65
66additionalProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
71
72    ufs_mem_phy: phy@1d87000 {
73        compatible = "qcom,sc8280xp-qmp-ufs-phy";
74        reg = <0x01d87000 0x1000>;
75
76        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
77        clock-names = "ref", "ref_aux";
78
79        power-domains = <&gcc UFS_PHY_GDSC>;
80
81        resets = <&ufs_mem_hc 0>;
82        reset-names = "ufsphy";
83
84        vdda-phy-supply = <&vreg_l6b>;
85        vdda-pll-supply = <&vreg_l3b>;
86
87        #phy-cells = <0>;
88    };
89