1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
20      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
21      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
22
23  reg:
24    minItems: 1
25    maxItems: 2
26
27  clocks:
28    maxItems: 6
29
30  clock-names:
31    items:
32      - const: aux
33      - const: cfg_ahb
34      - const: ref
35      - const: rchng
36      - const: pipe
37      - const: pipediv2
38
39  power-domains:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45  reset-names:
46    items:
47      - const: phy
48
49  vdda-phy-supply: true
50
51  vdda-pll-supply: true
52
53  qcom,4ln-config-sel:
54    description: PCIe 4-lane configuration
55    $ref: /schemas/types.yaml#/definitions/phandle-array
56    items:
57      - items:
58          - description: phandle of TCSR syscon
59          - description: offset of PCIe 4-lane configuration register
60          - description: offset of configuration bit for this PHY
61
62  "#clock-cells":
63    const: 0
64
65  clock-output-names:
66    maxItems: 1
67
68  "#phy-cells":
69    const: 0
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-names
76  - power-domains
77  - resets
78  - reset-names
79  - vdda-phy-supply
80  - vdda-pll-supply
81  - "#clock-cells"
82  - clock-output-names
83  - "#phy-cells"
84
85additionalProperties: false
86
87allOf:
88  - if:
89      properties:
90        compatible:
91          contains:
92            enum:
93              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
94    then:
95      properties:
96        reg:
97          items:
98            - description: port a
99            - description: port b
100      required:
101        - qcom,4ln-config-sel
102    else:
103      properties:
104        reg:
105          maxItems: 1
106
107examples:
108  - |
109    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
110
111    pcie2b_phy: phy@1c18000 {
112      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
113      reg = <0x01c18000 0x2000>;
114
115      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
116               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
117               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
118               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
119               <&gcc GCC_PCIE_2B_PIPE_CLK>,
120               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
121      clock-names = "aux", "cfg_ahb", "ref", "rchng",
122                    "pipe", "pipediv2";
123
124      power-domains = <&gcc PCIE_2B_GDSC>;
125
126      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
127      reset-names = "phy";
128
129      vdda-phy-supply = <&vreg_l6d>;
130      vdda-pll-supply = <&vreg_l4d>;
131
132      #clock-cells = <0>;
133      clock-output-names = "pcie_2b_pipe_clk";
134
135      #phy-cells = <0>;
136    };
137
138    pcie2a_phy: phy@1c24000 {
139      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
140      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
141
142      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
143               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
144               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
145               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
146               <&gcc GCC_PCIE_2A_PIPE_CLK>,
147               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
148      clock-names = "aux", "cfg_ahb", "ref", "rchng",
149                    "pipe", "pipediv2";
150
151      power-domains = <&gcc PCIE_2A_GDSC>;
152
153      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
154      reset-names = "phy";
155
156      vdda-phy-supply = <&vreg_l6d>;
157      vdda-pll-supply = <&vreg_l4d>;
158
159      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
160
161      #clock-cells = <0>;
162      clock-output-names = "pcie_2a_pipe_clk";
163
164      #phy-cells = <0>;
165    };
166