1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-gen3x1-pcie-phy
20      - qcom,sc8280xp-qmp-gen3x2-pcie-phy
21      - qcom,sc8280xp-qmp-gen3x4-pcie-phy
22      - qcom,sm8350-qmp-gen3x1-pcie-phy
23      - qcom,sm8550-qmp-gen3x2-pcie-phy
24      - qcom,sm8550-qmp-gen4x2-pcie-phy
25
26  reg:
27    minItems: 1
28    maxItems: 2
29
30  clocks:
31    minItems: 5
32    maxItems: 6
33
34  clock-names:
35    minItems: 5
36    items:
37      - const: aux
38      - const: cfg_ahb
39      - const: ref
40      - const: rchng
41      - const: pipe
42      - const: pipediv2
43
44  power-domains:
45    maxItems: 1
46
47  resets:
48    minItems: 1
49    maxItems: 2
50
51  reset-names:
52    minItems: 1
53    items:
54      - const: phy
55      - const: phy_nocsr
56
57  vdda-phy-supply: true
58
59  vdda-pll-supply: true
60
61  vdda-qref-supply: true
62
63  qcom,4ln-config-sel:
64    description: PCIe 4-lane configuration
65    $ref: /schemas/types.yaml#/definitions/phandle-array
66    items:
67      - items:
68          - description: phandle of TCSR syscon
69          - description: offset of PCIe 4-lane configuration register
70          - description: offset of configuration bit for this PHY
71
72  "#clock-cells":
73    const: 0
74
75  clock-output-names:
76    maxItems: 1
77
78  "#phy-cells":
79    const: 0
80
81required:
82  - compatible
83  - reg
84  - clocks
85  - clock-names
86  - power-domains
87  - resets
88  - reset-names
89  - vdda-phy-supply
90  - vdda-pll-supply
91  - "#clock-cells"
92  - clock-output-names
93  - "#phy-cells"
94
95additionalProperties: false
96
97allOf:
98  - if:
99      properties:
100        compatible:
101          contains:
102            enum:
103              - qcom,sc8280xp-qmp-gen3x4-pcie-phy
104    then:
105      properties:
106        reg:
107          items:
108            - description: port a
109            - description: port b
110      required:
111        - qcom,4ln-config-sel
112    else:
113      properties:
114        reg:
115          maxItems: 1
116
117  - if:
118      properties:
119        compatible:
120          contains:
121            enum:
122              - qcom,sm8350-qmp-gen3x1-pcie-phy
123              - qcom,sm8550-qmp-gen3x2-pcie-phy
124              - qcom,sm8550-qmp-gen4x2-pcie-phy
125    then:
126      properties:
127        clocks:
128          maxItems: 5
129        clock-names:
130          maxItems: 5
131    else:
132      properties:
133        clocks:
134          minItems: 6
135        clock-names:
136          minItems: 6
137
138  - if:
139      properties:
140        compatible:
141          contains:
142            enum:
143              - qcom,sm8550-qmp-gen4x2-pcie-phy
144    then:
145      properties:
146        resets:
147          minItems: 2
148        reset-names:
149          minItems: 2
150    else:
151      properties:
152        resets:
153          maxItems: 1
154        reset-names:
155          maxItems: 1
156
157examples:
158  - |
159    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
160
161    pcie2b_phy: phy@1c18000 {
162      compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
163      reg = <0x01c18000 0x2000>;
164
165      clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
166               <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
167               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
168               <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
169               <&gcc GCC_PCIE_2B_PIPE_CLK>,
170               <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
171      clock-names = "aux", "cfg_ahb", "ref", "rchng",
172                    "pipe", "pipediv2";
173
174      power-domains = <&gcc PCIE_2B_GDSC>;
175
176      resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
177      reset-names = "phy";
178
179      vdda-phy-supply = <&vreg_l6d>;
180      vdda-pll-supply = <&vreg_l4d>;
181
182      #clock-cells = <0>;
183      clock-output-names = "pcie_2b_pipe_clk";
184
185      #phy-cells = <0>;
186    };
187
188    pcie2a_phy: phy@1c24000 {
189      compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
190      reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
191
192      clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
193               <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
194               <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
195               <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
196               <&gcc GCC_PCIE_2A_PIPE_CLK>,
197               <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
198      clock-names = "aux", "cfg_ahb", "ref", "rchng",
199                    "pipe", "pipediv2";
200
201      power-domains = <&gcc PCIE_2A_GDSC>;
202
203      resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
204      reset-names = "phy";
205
206      vdda-phy-supply = <&vreg_l6d>;
207      vdda-pll-supply = <&vreg_l4d>;
208
209      qcom,4ln-config-sel = <&tcsr 0xa044 0>;
210
211      #clock-cells = <0>;
212      clock-output-names = "pcie_2a_pipe_clk";
213
214      #phy-cells = <0>;
215    };
216