1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sa8775p-qmp-ufs-phy
20      - qcom,sc8280xp-qmp-ufs-phy
21      - qcom,sm6125-qmp-ufs-phy
22      - qcom,sm7150-qmp-ufs-phy
23      - qcom,sm8550-qmp-ufs-phy
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    minItems: 2
30    maxItems: 3
31
32  clock-names:
33    minItems: 2
34    items:
35      - const: ref
36      - const: ref_aux
37      - const: qref
38
39  power-domains:
40    maxItems: 1
41
42  resets:
43    maxItems: 1
44
45  reset-names:
46    items:
47      - const: ufsphy
48
49  vdda-phy-supply: true
50
51  vdda-pll-supply: true
52
53  "#clock-cells":
54    const: 1
55
56  "#phy-cells":
57    const: 0
58
59required:
60  - compatible
61  - reg
62  - clocks
63  - clock-names
64  - power-domains
65  - resets
66  - reset-names
67  - vdda-phy-supply
68  - vdda-pll-supply
69  - "#phy-cells"
70
71allOf:
72  - if:
73      properties:
74        compatible:
75          contains:
76            enum:
77              - qcom,sa8775p-qmp-ufs-phy
78    then:
79      properties:
80        clocks:
81          minItems: 3
82        clock-names:
83          minItems: 3
84    else:
85      properties:
86        clocks:
87          maxItems: 2
88        clock-names:
89          maxItems: 2
90
91additionalProperties: false
92
93examples:
94  - |
95    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
96
97    ufs_mem_phy: phy@1d87000 {
98        compatible = "qcom,sc8280xp-qmp-ufs-phy";
99        reg = <0x01d87000 0x1000>;
100
101        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
102        clock-names = "ref", "ref_aux";
103
104        power-domains = <&gcc UFS_PHY_GDSC>;
105
106        resets = <&ufs_mem_hc 0>;
107        reset-names = "ufsphy";
108
109        vdda-phy-supply = <&vreg_l6b>;
110        vdda-pll-supply = <&vreg_l3b>;
111
112        #phy-cells = <0>;
113    };
114