1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-ufs-phy
20
21  reg:
22    maxItems: 1
23
24  clocks:
25    maxItems: 2
26
27  clock-names:
28    items:
29      - const: ref
30      - const: ref_aux
31
32  power-domains:
33    maxItems: 1
34
35  resets:
36    maxItems: 1
37
38  reset-names:
39    items:
40      - const: ufsphy
41
42  vdda-phy-supply: true
43
44  vdda-pll-supply: true
45
46  "#phy-cells":
47    const: 0
48
49required:
50  - compatible
51  - reg
52  - clocks
53  - clock-names
54  - power-domains
55  - resets
56  - reset-names
57  - vdda-phy-supply
58  - vdda-pll-supply
59  - "#phy-cells"
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
66
67    ufs_mem_phy: phy@1d87000 {
68        compatible = "qcom,sc8280xp-qmp-ufs-phy";
69        reg = <0x01d87000 0x1000>;
70
71        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
72        clock-names = "ref", "ref_aux";
73
74        power-domains = <&gcc UFS_PHY_GDSC>;
75
76        resets = <&ufs_mem_hc 0>;
77        reset-names = "ufsphy";
78
79        vdda-phy-supply = <&vreg_l6b>;
80        vdda-pll-supply = <&vreg_l3b>;
81
82        #phy-cells = <0>;
83    };
84