1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc8280xp-qmp-ufs-phy
20      - qcom,sm6125-qmp-ufs-phy
21      - qcom,sm7150-qmp-ufs-phy
22      - qcom,sm8550-qmp-ufs-phy
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    maxItems: 2
29
30  clock-names:
31    items:
32      - const: ref
33      - const: ref_aux
34
35  power-domains:
36    maxItems: 1
37
38  resets:
39    maxItems: 1
40
41  reset-names:
42    items:
43      - const: ufsphy
44
45  vdda-phy-supply: true
46
47  vdda-pll-supply: true
48
49  "#clock-cells":
50    const: 1
51
52  "#phy-cells":
53    const: 0
54
55required:
56  - compatible
57  - reg
58  - clocks
59  - clock-names
60  - power-domains
61  - resets
62  - reset-names
63  - vdda-phy-supply
64  - vdda-pll-supply
65  - "#phy-cells"
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
72
73    ufs_mem_phy: phy@1d87000 {
74        compatible = "qcom,sc8280xp-qmp-ufs-phy";
75        reg = <0x01d87000 0x1000>;
76
77        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
78        clock-names = "ref", "ref_aux";
79
80        power-domains = <&gcc UFS_PHY_GDSC>;
81
82        resets = <&ufs_mem_hc 0>;
83        reset-names = "ufsphy";
84
85        vdda-phy-supply = <&vreg_l6b>;
86        vdda-pll-supply = <&vreg_l3b>;
87
88        #phy-cells = <0>;
89    };
90