1NVIDIA Tegra PCIe controller 2 3Required properties: 4- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie" 5- device_type: Must be "pci" 6- reg: A list of physical base address and length for each set of controller 7 registers. Must contain an entry for each entry in the reg-names property. 8- reg-names: Must include the following entries: 9 "pads": PADS registers 10 "afi": AFI registers 11 "cs": configuration space region 12- interrupts: A list of interrupt outputs of the controller. Must contain an 13 entry for each entry in the interrupt-names property. 14- interrupt-names: Must include the following entries: 15 "intr": The Tegra interrupt that is asserted for controller interrupts 16 "msi": The Tegra interrupt that is asserted when an MSI is received 17- pex-clk-supply: Supply voltage for internal reference clock 18- vdd-supply: Power supply for controller (1.05V) 19- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) 20- bus-range: Range of bus numbers associated with this controller 21- #address-cells: Address representation for root ports (must be 3) 22 - cell 0 specifies the bus and device numbers of the root port: 23 [23:16]: bus number 24 [15:11]: device number 25 - cell 1 denotes the upper 32 address bits and should be 0 26 - cell 2 contains the lower 32 address bits and is used to translate to the 27 CPU address space 28- #size-cells: Size representation for root ports (must be 2) 29- ranges: Describes the translation of addresses for root ports and standard 30 PCI regions. The entries must be 6 cells each, where the first three cells 31 correspond to the address as described for the #address-cells property 32 above, the fourth cell is the physical CPU address to translate to and the 33 fifth and six cells are as described for the #size-cells property above. 34 - The first two entries are expected to translate the addresses for the root 35 port registers, which are referenced by the assigned-addresses property of 36 the root port nodes (see below). 37 - The remaining entries setup the mapping for the standard I/O, memory and 38 prefetchable PCI regions. The first cell determines the type of region 39 that is setup: 40 - 0x81000000: I/O memory region 41 - 0x82000000: non-prefetchable memory region 42 - 0xc2000000: prefetchable memory region 43 Please refer to the standard PCI bus binding document for a more detailed 44 explanation. 45- #interrupt-cells: Size representation for interrupts (must be 1) 46- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 47 Please refer to the standard PCI bus binding document for a more detailed 48 explanation. 49- clocks: Must contain an entry for each entry in clock-names. 50 See ../clocks/clock-bindings.txt for details. 51- clock-names: Must include the following entries: 52 - pex 53 - afi 54 - pll_e 55 - cml (not required for Tegra20) 56- resets: Must contain an entry for each entry in reset-names. 57 See ../reset/reset.txt for details. 58- reset-names: Must include the following entries: 59 - pex 60 - afi 61 - pcie_x 62 63Root ports are defined as subnodes of the PCIe controller node. 64 65Required properties: 66- device_type: Must be "pci" 67- assigned-addresses: Address and size of the port configuration registers 68- reg: PCI bus address of the root port 69- #address-cells: Must be 3 70- #size-cells: Must be 2 71- ranges: Sub-ranges distributed from the PCIe controller node. An empty 72 property is sufficient. 73- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations 74 are: 75 - Root port 0 uses 4 lanes, root port 1 is unused. 76 - Both root ports use 2 lanes. 77 78Example: 79 80SoC DTSI: 81 82 pcie-controller { 83 compatible = "nvidia,tegra20-pcie"; 84 device_type = "pci"; 85 reg = <0x80003000 0x00000800 /* PADS registers */ 86 0x80003800 0x00000200 /* AFI registers */ 87 0x90000000 0x10000000>; /* configuration space */ 88 reg-names = "pads", "afi", "cs"; 89 interrupts = <0 98 0x04 /* controller interrupt */ 90 0 99 0x04>; /* MSI interrupt */ 91 interrupt-names = "intr", "msi"; 92 93 #interrupt-cells = <1>; 94 interrupt-map-mask = <0 0 0 0>; 95 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 96 97 bus-range = <0x00 0xff>; 98 #address-cells = <3>; 99 #size-cells = <2>; 100 101 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 102 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 103 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 104 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ 105 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ 106 107 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; 108 clock-names = "pex", "afi", "pll_e"; 109 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; 110 reset-names = "pex", "afi", "pcie_x"; 111 status = "disabled"; 112 113 pci@1,0 { 114 device_type = "pci"; 115 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 116 reg = <0x000800 0 0 0 0>; 117 status = "disabled"; 118 119 #address-cells = <3>; 120 #size-cells = <2>; 121 122 ranges; 123 124 nvidia,num-lanes = <2>; 125 }; 126 127 pci@2,0 { 128 device_type = "pci"; 129 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 130 reg = <0x001000 0 0 0 0>; 131 status = "disabled"; 132 133 #address-cells = <3>; 134 #size-cells = <2>; 135 136 ranges; 137 138 nvidia,num-lanes = <2>; 139 }; 140 }; 141 142 143Board DTS: 144 145 pcie-controller { 146 status = "okay"; 147 148 vdd-supply = <&pci_vdd_reg>; 149 pex-clk-supply = <&pci_clk_reg>; 150 151 /* root port 00:01.0 */ 152 pci@1,0 { 153 status = "okay"; 154 155 /* bridge 01:00.0 (optional) */ 156 pci@0,0 { 157 reg = <0x010000 0 0 0 0>; 158 159 #address-cells = <3>; 160 #size-cells = <2>; 161 162 device_type = "pci"; 163 164 /* endpoint 02:00.0 */ 165 pci@0,0 { 166 reg = <0x020000 0 0 0 0>; 167 }; 168 }; 169 }; 170 }; 171 172Note that devices on the PCI bus are dynamically discovered using PCI's bus 173enumeration and therefore don't need corresponding device nodes in DT. However 174if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, 175device nodes need to be added in order to allow the bus' children to be 176instantiated at the proper location in the operating system's device tree (as 177illustrated by the optional nodes in the example above). 178