1NVIDIA Tegra PCIe controller 2 3Required properties: 4- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie" 5- device_type: Must be "pci" 6- reg: A list of physical base address and length for each set of controller 7 registers. Must contain an entry for each entry in the reg-names property. 8- reg-names: Must include the following entries: 9 "pads": PADS registers 10 "afi": AFI registers 11 "cs": configuration space region 12- interrupts: A list of interrupt outputs of the controller. Must contain an 13 entry for each entry in the interrupt-names property. 14- interrupt-names: Must include the following entries: 15 "intr": The Tegra interrupt that is asserted for controller interrupts 16 "msi": The Tegra interrupt that is asserted when an MSI is received 17- bus-range: Range of bus numbers associated with this controller 18- #address-cells: Address representation for root ports (must be 3) 19 - cell 0 specifies the bus and device numbers of the root port: 20 [23:16]: bus number 21 [15:11]: device number 22 - cell 1 denotes the upper 32 address bits and should be 0 23 - cell 2 contains the lower 32 address bits and is used to translate to the 24 CPU address space 25- #size-cells: Size representation for root ports (must be 2) 26- ranges: Describes the translation of addresses for root ports and standard 27 PCI regions. The entries must be 6 cells each, where the first three cells 28 correspond to the address as described for the #address-cells property 29 above, the fourth cell is the physical CPU address to translate to and the 30 fifth and six cells are as described for the #size-cells property above. 31 - The first two entries are expected to translate the addresses for the root 32 port registers, which are referenced by the assigned-addresses property of 33 the root port nodes (see below). 34 - The remaining entries setup the mapping for the standard I/O, memory and 35 prefetchable PCI regions. The first cell determines the type of region 36 that is setup: 37 - 0x81000000: I/O memory region 38 - 0x82000000: non-prefetchable memory region 39 - 0xc2000000: prefetchable memory region 40 Please refer to the standard PCI bus binding document for a more detailed 41 explanation. 42- #interrupt-cells: Size representation for interrupts (must be 1) 43- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 44 Please refer to the standard PCI bus binding document for a more detailed 45 explanation. 46- clocks: Must contain an entry for each entry in clock-names. 47 See ../clocks/clock-bindings.txt for details. 48- clock-names: Must include the following entries: 49 - pex 50 - afi 51 - pll_e 52 - cml (not required for Tegra20) 53- resets: Must contain an entry for each entry in reset-names. 54 See ../reset/reset.txt for details. 55- reset-names: Must include the following entries: 56 - pex 57 - afi 58 - pcie_x 59 60Power supplies for Tegra20: 61- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 62- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 63- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 64 supply 1.05 V. 65- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must 66 supply 1.05 V. 67- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. 68 69Power supplies for Tegra30: 70- Required: 71 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 72 supply 1.05 V. 73 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must 74 supply 1.05 V. 75 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must 76 supply 1.8 V. 77 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. 78 Must supply 3.3 V. 79- Optional: 80 - If lanes 0 to 3 are used: 81 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 82 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 83 - If lanes 4 or 5 are used: 84 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 85 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 86 87Root ports are defined as subnodes of the PCIe controller node. 88 89Required properties: 90- device_type: Must be "pci" 91- assigned-addresses: Address and size of the port configuration registers 92- reg: PCI bus address of the root port 93- #address-cells: Must be 3 94- #size-cells: Must be 2 95- ranges: Sub-ranges distributed from the PCIe controller node. An empty 96 property is sufficient. 97- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations 98 are: 99 - Root port 0 uses 4 lanes, root port 1 is unused. 100 - Both root ports use 2 lanes. 101 102Example: 103 104SoC DTSI: 105 106 pcie-controller { 107 compatible = "nvidia,tegra20-pcie"; 108 device_type = "pci"; 109 reg = <0x80003000 0x00000800 /* PADS registers */ 110 0x80003800 0x00000200 /* AFI registers */ 111 0x90000000 0x10000000>; /* configuration space */ 112 reg-names = "pads", "afi", "cs"; 113 interrupts = <0 98 0x04 /* controller interrupt */ 114 0 99 0x04>; /* MSI interrupt */ 115 interrupt-names = "intr", "msi"; 116 117 #interrupt-cells = <1>; 118 interrupt-map-mask = <0 0 0 0>; 119 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 120 121 bus-range = <0x00 0xff>; 122 #address-cells = <3>; 123 #size-cells = <2>; 124 125 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 126 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 127 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 128 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ 129 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ 130 131 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; 132 clock-names = "pex", "afi", "pll_e"; 133 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; 134 reset-names = "pex", "afi", "pcie_x"; 135 status = "disabled"; 136 137 pci@1,0 { 138 device_type = "pci"; 139 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 140 reg = <0x000800 0 0 0 0>; 141 status = "disabled"; 142 143 #address-cells = <3>; 144 #size-cells = <2>; 145 146 ranges; 147 148 nvidia,num-lanes = <2>; 149 }; 150 151 pci@2,0 { 152 device_type = "pci"; 153 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 154 reg = <0x001000 0 0 0 0>; 155 status = "disabled"; 156 157 #address-cells = <3>; 158 #size-cells = <2>; 159 160 ranges; 161 162 nvidia,num-lanes = <2>; 163 }; 164 }; 165 166 167Board DTS: 168 169 pcie-controller { 170 status = "okay"; 171 172 vdd-supply = <&pci_vdd_reg>; 173 pex-clk-supply = <&pci_clk_reg>; 174 175 /* root port 00:01.0 */ 176 pci@1,0 { 177 status = "okay"; 178 179 /* bridge 01:00.0 (optional) */ 180 pci@0,0 { 181 reg = <0x010000 0 0 0 0>; 182 183 #address-cells = <3>; 184 #size-cells = <2>; 185 186 device_type = "pci"; 187 188 /* endpoint 02:00.0 */ 189 pci@0,0 { 190 reg = <0x020000 0 0 0 0>; 191 }; 192 }; 193 }; 194 }; 195 196Note that devices on the PCI bus are dynamically discovered using PCI's bus 197enumeration and therefore don't need corresponding device nodes in DT. However 198if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, 199device nodes need to be added in order to allow the bus' children to be 200instantiated at the proper location in the operating system's device tree (as 201illustrated by the optional nodes in the example above). 202