1NVIDIA Tegra PCIe controller
2
3Required properties:
4- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
5- device_type: Must be "pci"
6- reg: A list of physical base address and length for each set of controller
7  registers. Must contain an entry for each entry in the reg-names property.
8- reg-names: Must include the following entries:
9  "pads": PADS registers
10  "afi": AFI registers
11  "cs": configuration space region
12- interrupts: A list of interrupt outputs of the controller. Must contain an
13  entry for each entry in the interrupt-names property.
14- interrupt-names: Must include the following entries:
15  "intr": The Tegra interrupt that is asserted for controller interrupts
16  "msi": The Tegra interrupt that is asserted when an MSI is received
17- pex-clk-supply: Supply voltage for internal reference clock
18- vdd-supply: Power supply for controller (1.05V)
19- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
20- bus-range: Range of bus numbers associated with this controller
21- #address-cells: Address representation for root ports (must be 3)
22  - cell 0 specifies the bus and device numbers of the root port:
23    [23:16]: bus number
24    [15:11]: device number
25  - cell 1 denotes the upper 32 address bits and should be 0
26  - cell 2 contains the lower 32 address bits and is used to translate to the
27    CPU address space
28- #size-cells: Size representation for root ports (must be 2)
29- ranges: Describes the translation of addresses for root ports and standard
30  PCI regions. The entries must be 6 cells each, where the first three cells
31  correspond to the address as described for the #address-cells property
32  above, the fourth cell is the physical CPU address to translate to and the
33  fifth and six cells are as described for the #size-cells property above.
34  - The first two entries are expected to translate the addresses for the root
35    port registers, which are referenced by the assigned-addresses property of
36    the root port nodes (see below).
37  - The remaining entries setup the mapping for the standard I/O, memory and
38    prefetchable PCI regions. The first cell determines the type of region
39    that is setup:
40    - 0x81000000: I/O memory region
41    - 0x82000000: non-prefetchable memory region
42    - 0xc2000000: prefetchable memory region
43  Please refer to the standard PCI bus binding document for a more detailed
44  explanation.
45- clocks: List of clock inputs of the controller. Must contain an entry for
46  each entry in the clock-names property.
47- clock-names: Must include the following entries:
48  "pex": The Tegra clock of that name
49  "afi": The Tegra clock of that name
50  "pcie_xclk": The Tegra clock of that name
51  "pll_e": The Tegra clock of that name
52  "cml": The Tegra clock of that name (not required for Tegra20)
53
54Root ports are defined as subnodes of the PCIe controller node.
55
56Required properties:
57- device_type: Must be "pci"
58- assigned-addresses: Address and size of the port configuration registers
59- reg: PCI bus address of the root port
60- #address-cells: Must be 3
61- #size-cells: Must be 2
62- ranges: Sub-ranges distributed from the PCIe controller node. An empty
63  property is sufficient.
64- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
65  are:
66  - Root port 0 uses 4 lanes, root port 1 is unused.
67  - Both root ports use 2 lanes.
68
69Example:
70
71SoC DTSI:
72
73	pcie-controller {
74		compatible = "nvidia,tegra20-pcie";
75		device_type = "pci";
76		reg = <0x80003000 0x00000800   /* PADS registers */
77		       0x80003800 0x00000200   /* AFI registers */
78		       0x90000000 0x10000000>; /* configuration space */
79		reg-names = "pads", "afi", "cs";
80		interrupts = <0 98 0x04   /* controller interrupt */
81		              0 99 0x04>; /* MSI interrupt */
82		interrupt-names = "intr", "msi";
83
84		bus-range = <0x00 0xff>;
85		#address-cells = <3>;
86		#size-cells = <2>;
87
88		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
89			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
90			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
91			  0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
92			  0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
93
94		clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
95			 <&tegra_car 118>;
96		clock-names = "pex", "afi", "pcie_xclk", "pll_e";
97		status = "disabled";
98
99		pci@1,0 {
100			device_type = "pci";
101			assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
102			reg = <0x000800 0 0 0 0>;
103			status = "disabled";
104
105			#address-cells = <3>;
106			#size-cells = <2>;
107
108			ranges;
109
110			nvidia,num-lanes = <2>;
111		};
112
113		pci@2,0 {
114			device_type = "pci";
115			assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
116			reg = <0x001000 0 0 0 0>;
117			status = "disabled";
118
119			#address-cells = <3>;
120			#size-cells = <2>;
121
122			ranges;
123
124			nvidia,num-lanes = <2>;
125		};
126	};
127
128
129Board DTS:
130
131	pcie-controller {
132		status = "okay";
133
134		vdd-supply = <&pci_vdd_reg>;
135		pex-clk-supply = <&pci_clk_reg>;
136
137		/* root port 00:01.0 */
138		pci@1,0 {
139			status = "okay";
140
141			/* bridge 01:00.0 (optional) */
142			pci@0,0 {
143				reg = <0x010000 0 0 0 0>;
144
145				#address-cells = <3>;
146				#size-cells = <2>;
147
148				device_type = "pci";
149
150				/* endpoint 02:00.0 */
151				pci@0,0 {
152					reg = <0x020000 0 0 0 0>;
153				};
154			};
155		};
156	};
157
158Note that devices on the PCI bus are dynamically discovered using PCI's bus
159enumeration and therefore don't need corresponding device nodes in DT. However
160if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
161device nodes need to be added in order to allow the bus' children to be
162instantiated at the proper location in the operating system's device tree (as
163illustrated by the optional nodes in the example above).
164