1NVIDIA Tegra PCIe controller 2 3Required properties: 4- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30, 5 "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie". 6 Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where 7 <chip> is tegra132 or tegra210. 8- device_type: Must be "pci" 9- reg: A list of physical base address and length for each set of controller 10 registers. Must contain an entry for each entry in the reg-names property. 11- reg-names: Must include the following entries: 12 "pads": PADS registers 13 "afi": AFI registers 14 "cs": configuration space region 15- interrupts: A list of interrupt outputs of the controller. Must contain an 16 entry for each entry in the interrupt-names property. 17- interrupt-names: Must include the following entries: 18 "intr": The Tegra interrupt that is asserted for controller interrupts 19 "msi": The Tegra interrupt that is asserted when an MSI is received 20- bus-range: Range of bus numbers associated with this controller 21- #address-cells: Address representation for root ports (must be 3) 22 - cell 0 specifies the bus and device numbers of the root port: 23 [23:16]: bus number 24 [15:11]: device number 25 - cell 1 denotes the upper 32 address bits and should be 0 26 - cell 2 contains the lower 32 address bits and is used to translate to the 27 CPU address space 28- #size-cells: Size representation for root ports (must be 2) 29- ranges: Describes the translation of addresses for root ports and standard 30 PCI regions. The entries must be 6 cells each, where the first three cells 31 correspond to the address as described for the #address-cells property 32 above, the fourth cell is the physical CPU address to translate to and the 33 fifth and six cells are as described for the #size-cells property above. 34 - The first two entries are expected to translate the addresses for the root 35 port registers, which are referenced by the assigned-addresses property of 36 the root port nodes (see below). 37 - The remaining entries setup the mapping for the standard I/O, memory and 38 prefetchable PCI regions. The first cell determines the type of region 39 that is setup: 40 - 0x81000000: I/O memory region 41 - 0x82000000: non-prefetchable memory region 42 - 0xc2000000: prefetchable memory region 43 Please refer to the standard PCI bus binding document for a more detailed 44 explanation. 45- #interrupt-cells: Size representation for interrupts (must be 1) 46- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 47 Please refer to the standard PCI bus binding document for a more detailed 48 explanation. 49- clocks: Must contain an entry for each entry in clock-names. 50 See ../clocks/clock-bindings.txt for details. 51- clock-names: Must include the following entries: 52 - pex 53 - afi 54 - pll_e 55 - cml (not required for Tegra20) 56- resets: Must contain an entry for each entry in reset-names. 57 See ../reset/reset.txt for details. 58- reset-names: Must include the following entries: 59 - pex 60 - afi 61 - pcie_x 62 63Required properties on Tegra124 and later (deprecated): 64- phys: Must contain an entry for each entry in phy-names. 65- phy-names: Must include the following entries: 66 - pcie 67 68These properties are deprecated in favour of per-lane PHYs define in each of 69the root ports (see below). 70 71Power supplies for Tegra20: 72- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 73- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 74- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 75 supply 1.05 V. 76- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must 77 supply 1.05 V. 78- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V. 79 80Power supplies for Tegra30: 81- Required: 82 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 83 supply 1.05 V. 84 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must 85 supply 1.05 V. 86 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must 87 supply 1.8 V. 88 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. 89 Must supply 3.3 V. 90- Optional: 91 - If lanes 0 to 3 are used: 92 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 93 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 94 - If lanes 4 or 5 are used: 95 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 96 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 97 98Power supplies for Tegra124: 99- Required: 100 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. 101 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 102 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 103 supply 1.05 V. 104 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. 105 Must supply 3.3 V. 106 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). 107 Must supply 3.3 V. 108 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must 109 supply 2.8-3.3 V. 110 - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must 111 supply 1.05 V. 112 113Power supplies for Tegra210: 114- Required: 115 - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must 116 supply 1.05 V. 117 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output 118 clocks. Must supply 1.8 V. 119 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. 120 - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must 121 supply 1.05 V. 122 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). 123 Must supply 3.3 V. 124 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must 125 supply 1.8 V. 126 127Root ports are defined as subnodes of the PCIe controller node. 128 129Required properties: 130- device_type: Must be "pci" 131- assigned-addresses: Address and size of the port configuration registers 132- reg: PCI bus address of the root port 133- #address-cells: Must be 3 134- #size-cells: Must be 2 135- ranges: Sub-ranges distributed from the PCIe controller node. An empty 136 property is sufficient. 137- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations 138 are: 139 - Root port 0 uses 4 lanes, root port 1 is unused. 140 - Both root ports use 2 lanes. 141 142Required properties for Tegra124 and later: 143- phys: Must contain an phandle to a PHY for each entry in phy-names. 144- phy-names: Must include an entry for each active lane. Note that the number 145 of entries does not have to (though usually will) be equal to the specified 146 number of lanes in the nvidia,num-lanes property. Entries are of the form 147 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. 148 149Examples: 150========= 151 152Tegra20: 153-------- 154 155SoC DTSI: 156 157 pcie-controller@80003000 { 158 compatible = "nvidia,tegra20-pcie"; 159 device_type = "pci"; 160 reg = <0x80003000 0x00000800 /* PADS registers */ 161 0x80003800 0x00000200 /* AFI registers */ 162 0x90000000 0x10000000>; /* configuration space */ 163 reg-names = "pads", "afi", "cs"; 164 interrupts = <0 98 0x04 /* controller interrupt */ 165 0 99 0x04>; /* MSI interrupt */ 166 interrupt-names = "intr", "msi"; 167 168 #interrupt-cells = <1>; 169 interrupt-map-mask = <0 0 0 0>; 170 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 171 172 bus-range = <0x00 0xff>; 173 #address-cells = <3>; 174 #size-cells = <2>; 175 176 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 177 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 178 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 179 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ 180 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ 181 182 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; 183 clock-names = "pex", "afi", "pll_e"; 184 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; 185 reset-names = "pex", "afi", "pcie_x"; 186 status = "disabled"; 187 188 pci@1,0 { 189 device_type = "pci"; 190 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 191 reg = <0x000800 0 0 0 0>; 192 status = "disabled"; 193 194 #address-cells = <3>; 195 #size-cells = <2>; 196 197 ranges; 198 199 nvidia,num-lanes = <2>; 200 }; 201 202 pci@2,0 { 203 device_type = "pci"; 204 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 205 reg = <0x001000 0 0 0 0>; 206 status = "disabled"; 207 208 #address-cells = <3>; 209 #size-cells = <2>; 210 211 ranges; 212 213 nvidia,num-lanes = <2>; 214 }; 215 }; 216 217Board DTS: 218 219 pcie-controller@80003000 { 220 status = "okay"; 221 222 vdd-supply = <&pci_vdd_reg>; 223 pex-clk-supply = <&pci_clk_reg>; 224 225 /* root port 00:01.0 */ 226 pci@1,0 { 227 status = "okay"; 228 229 /* bridge 01:00.0 (optional) */ 230 pci@0,0 { 231 reg = <0x010000 0 0 0 0>; 232 233 #address-cells = <3>; 234 #size-cells = <2>; 235 236 device_type = "pci"; 237 238 /* endpoint 02:00.0 */ 239 pci@0,0 { 240 reg = <0x020000 0 0 0 0>; 241 }; 242 }; 243 }; 244 }; 245 246Note that devices on the PCI bus are dynamically discovered using PCI's bus 247enumeration and therefore don't need corresponding device nodes in DT. However 248if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, 249device nodes need to be added in order to allow the bus' children to be 250instantiated at the proper location in the operating system's device tree (as 251illustrated by the optional nodes in the example above). 252 253Tegra30: 254-------- 255 256SoC DTSI: 257 258 pcie-controller@3000 { 259 compatible = "nvidia,tegra30-pcie"; 260 device_type = "pci"; 261 reg = <0x00003000 0x00000800 /* PADS registers */ 262 0x00003800 0x00000200 /* AFI registers */ 263 0x10000000 0x10000000>; /* configuration space */ 264 reg-names = "pads", "afi", "cs"; 265 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 266 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 267 interrupt-names = "intr", "msi"; 268 269 #interrupt-cells = <1>; 270 interrupt-map-mask = <0 0 0 0>; 271 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 272 273 bus-range = <0x00 0xff>; 274 #address-cells = <3>; 275 #size-cells = <2>; 276 277 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 278 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 279 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 280 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ 281 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 282 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 283 284 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 285 <&tegra_car TEGRA30_CLK_AFI>, 286 <&tegra_car TEGRA30_CLK_PLL_E>, 287 <&tegra_car TEGRA30_CLK_CML0>; 288 clock-names = "pex", "afi", "pll_e", "cml"; 289 resets = <&tegra_car 70>, 290 <&tegra_car 72>, 291 <&tegra_car 74>; 292 reset-names = "pex", "afi", "pcie_x"; 293 status = "disabled"; 294 295 pci@1,0 { 296 device_type = "pci"; 297 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 298 reg = <0x000800 0 0 0 0>; 299 status = "disabled"; 300 301 #address-cells = <3>; 302 #size-cells = <2>; 303 ranges; 304 305 nvidia,num-lanes = <2>; 306 }; 307 308 pci@2,0 { 309 device_type = "pci"; 310 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 311 reg = <0x001000 0 0 0 0>; 312 status = "disabled"; 313 314 #address-cells = <3>; 315 #size-cells = <2>; 316 ranges; 317 318 nvidia,num-lanes = <2>; 319 }; 320 321 pci@3,0 { 322 device_type = "pci"; 323 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 324 reg = <0x001800 0 0 0 0>; 325 status = "disabled"; 326 327 #address-cells = <3>; 328 #size-cells = <2>; 329 ranges; 330 331 nvidia,num-lanes = <2>; 332 }; 333 }; 334 335Board DTS: 336 337 pcie-controller@3000 { 338 status = "okay"; 339 340 avdd-pexa-supply = <&ldo1_reg>; 341 vdd-pexa-supply = <&ldo1_reg>; 342 avdd-pexb-supply = <&ldo1_reg>; 343 vdd-pexb-supply = <&ldo1_reg>; 344 avdd-pex-pll-supply = <&ldo1_reg>; 345 avdd-plle-supply = <&ldo1_reg>; 346 vddio-pex-ctl-supply = <&sys_3v3_reg>; 347 hvdd-pex-supply = <&sys_3v3_pexs_reg>; 348 349 pci@1,0 { 350 status = "okay"; 351 }; 352 353 pci@3,0 { 354 status = "okay"; 355 }; 356 }; 357 358Tegra124: 359--------- 360 361SoC DTSI: 362 363 pcie-controller@1003000 { 364 compatible = "nvidia,tegra124-pcie"; 365 device_type = "pci"; 366 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 367 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 368 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 369 reg-names = "pads", "afi", "cs"; 370 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 371 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 372 interrupt-names = "intr", "msi"; 373 374 #interrupt-cells = <1>; 375 interrupt-map-mask = <0 0 0 0>; 376 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 377 378 bus-range = <0x00 0xff>; 379 #address-cells = <3>; 380 #size-cells = <2>; 381 382 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 383 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 384 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 385 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 386 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 387 388 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 389 <&tegra_car TEGRA124_CLK_AFI>, 390 <&tegra_car TEGRA124_CLK_PLL_E>, 391 <&tegra_car TEGRA124_CLK_CML0>; 392 clock-names = "pex", "afi", "pll_e", "cml"; 393 resets = <&tegra_car 70>, 394 <&tegra_car 72>, 395 <&tegra_car 74>; 396 reset-names = "pex", "afi", "pcie_x"; 397 status = "disabled"; 398 399 pci@1,0 { 400 device_type = "pci"; 401 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 402 reg = <0x000800 0 0 0 0>; 403 status = "disabled"; 404 405 #address-cells = <3>; 406 #size-cells = <2>; 407 ranges; 408 409 nvidia,num-lanes = <2>; 410 }; 411 412 pci@2,0 { 413 device_type = "pci"; 414 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 415 reg = <0x001000 0 0 0 0>; 416 status = "disabled"; 417 418 #address-cells = <3>; 419 #size-cells = <2>; 420 ranges; 421 422 nvidia,num-lanes = <1>; 423 }; 424 }; 425 426Board DTS: 427 428 pcie-controller@1003000 { 429 status = "okay"; 430 431 avddio-pex-supply = <&vdd_1v05_run>; 432 dvddio-pex-supply = <&vdd_1v05_run>; 433 avdd-pex-pll-supply = <&vdd_1v05_run>; 434 hvdd-pex-supply = <&vdd_3v3_lp0>; 435 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; 436 vddio-pex-ctl-supply = <&vdd_3v3_lp0>; 437 avdd-pll-erefe-supply = <&avdd_1v05_run>; 438 439 /* Mini PCIe */ 440 pci@1,0 { 441 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 442 phy-names = "pcie-0"; 443 status = "okay"; 444 }; 445 446 /* Gigabit Ethernet */ 447 pci@2,0 { 448 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 449 phy-names = "pcie-0"; 450 status = "okay"; 451 }; 452 }; 453 454Tegra210: 455--------- 456 457SoC DTSI: 458 459 pcie-controller@1003000 { 460 compatible = "nvidia,tegra210-pcie"; 461 device_type = "pci"; 462 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 463 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 464 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 465 reg-names = "pads", "afi", "cs"; 466 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 467 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 468 interrupt-names = "intr", "msi"; 469 470 #interrupt-cells = <1>; 471 interrupt-map-mask = <0 0 0 0>; 472 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 473 474 bus-range = <0x00 0xff>; 475 #address-cells = <3>; 476 #size-cells = <2>; 477 478 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 479 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 480 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 481 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 482 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 483 484 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 485 <&tegra_car TEGRA210_CLK_AFI>, 486 <&tegra_car TEGRA210_CLK_PLL_E>, 487 <&tegra_car TEGRA210_CLK_CML0>; 488 clock-names = "pex", "afi", "pll_e", "cml"; 489 resets = <&tegra_car 70>, 490 <&tegra_car 72>, 491 <&tegra_car 74>; 492 reset-names = "pex", "afi", "pcie_x"; 493 status = "disabled"; 494 495 pci@1,0 { 496 device_type = "pci"; 497 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 498 reg = <0x000800 0 0 0 0>; 499 status = "disabled"; 500 501 #address-cells = <3>; 502 #size-cells = <2>; 503 ranges; 504 505 nvidia,num-lanes = <4>; 506 }; 507 508 pci@2,0 { 509 device_type = "pci"; 510 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 511 reg = <0x001000 0 0 0 0>; 512 status = "disabled"; 513 514 #address-cells = <3>; 515 #size-cells = <2>; 516 ranges; 517 518 nvidia,num-lanes = <1>; 519 }; 520 }; 521 522Board DTS: 523 524 pcie-controller@1003000 { 525 status = "okay"; 526 527 avdd-pll-uerefe-supply = <&avdd_1v05_pll>; 528 hvddio-pex-supply = <&vdd_1v8>; 529 dvddio-pex-supply = <&vdd_pex_1v05>; 530 dvdd-pex-pll-supply = <&vdd_pex_1v05>; 531 hvdd-pex-pll-e-supply = <&vdd_1v8>; 532 vddio-pex-ctl-supply = <&vdd_1v8>; 533 534 pci@1,0 { 535 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, 536 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 537 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 538 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 539 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 540 status = "okay"; 541 }; 542 543 pci@2,0 { 544 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 545 phy-names = "pcie-0"; 546 status = "okay"; 547 }; 548 }; 549