1NVIDIA Tegra PCIe controller 2 3Required properties: 4- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie" 5- device_type: Must be "pci" 6- reg: A list of physical base address and length for each set of controller 7 registers. Must contain an entry for each entry in the reg-names property. 8- reg-names: Must include the following entries: 9 "pads": PADS registers 10 "afi": AFI registers 11 "cs": configuration space region 12- interrupts: A list of interrupt outputs of the controller. Must contain an 13 entry for each entry in the interrupt-names property. 14- interrupt-names: Must include the following entries: 15 "intr": The Tegra interrupt that is asserted for controller interrupts 16 "msi": The Tegra interrupt that is asserted when an MSI is received 17- pex-clk-supply: Supply voltage for internal reference clock 18- vdd-supply: Power supply for controller (1.05V) 19- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20) 20- bus-range: Range of bus numbers associated with this controller 21- #address-cells: Address representation for root ports (must be 3) 22 - cell 0 specifies the bus and device numbers of the root port: 23 [23:16]: bus number 24 [15:11]: device number 25 - cell 1 denotes the upper 32 address bits and should be 0 26 - cell 2 contains the lower 32 address bits and is used to translate to the 27 CPU address space 28- #size-cells: Size representation for root ports (must be 2) 29- ranges: Describes the translation of addresses for root ports and standard 30 PCI regions. The entries must be 6 cells each, where the first three cells 31 correspond to the address as described for the #address-cells property 32 above, the fourth cell is the physical CPU address to translate to and the 33 fifth and six cells are as described for the #size-cells property above. 34 - The first two entries are expected to translate the addresses for the root 35 port registers, which are referenced by the assigned-addresses property of 36 the root port nodes (see below). 37 - The remaining entries setup the mapping for the standard I/O, memory and 38 prefetchable PCI regions. The first cell determines the type of region 39 that is setup: 40 - 0x81000000: I/O memory region 41 - 0x82000000: non-prefetchable memory region 42 - 0xc2000000: prefetchable memory region 43 Please refer to the standard PCI bus binding document for a more detailed 44 explanation. 45- clocks: Must contain an entry for each entry in clock-names. 46 See ../clocks/clock-bindings.txt for details. 47- clock-names: Must include the following entries: 48 - pex 49 - afi 50 - pll_e 51 - cml (not required for Tegra20) 52- resets: Must contain an entry for each entry in reset-names. 53 See ../reset/reset.txt for details. 54- reset-names: Must include the following entries: 55 - pex 56 - afi 57 - pcie_x 58 59Root ports are defined as subnodes of the PCIe controller node. 60 61Required properties: 62- device_type: Must be "pci" 63- assigned-addresses: Address and size of the port configuration registers 64- reg: PCI bus address of the root port 65- #address-cells: Must be 3 66- #size-cells: Must be 2 67- ranges: Sub-ranges distributed from the PCIe controller node. An empty 68 property is sufficient. 69- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations 70 are: 71 - Root port 0 uses 4 lanes, root port 1 is unused. 72 - Both root ports use 2 lanes. 73 74Example: 75 76SoC DTSI: 77 78 pcie-controller { 79 compatible = "nvidia,tegra20-pcie"; 80 device_type = "pci"; 81 reg = <0x80003000 0x00000800 /* PADS registers */ 82 0x80003800 0x00000200 /* AFI registers */ 83 0x90000000 0x10000000>; /* configuration space */ 84 reg-names = "pads", "afi", "cs"; 85 interrupts = <0 98 0x04 /* controller interrupt */ 86 0 99 0x04>; /* MSI interrupt */ 87 interrupt-names = "intr", "msi"; 88 89 bus-range = <0x00 0xff>; 90 #address-cells = <3>; 91 #size-cells = <2>; 92 93 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 94 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 95 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ 96 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ 97 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ 98 99 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>; 100 clock-names = "pex", "afi", "pll_e"; 101 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>; 102 reset-names = "pex", "afi", "pcie_x"; 103 status = "disabled"; 104 105 pci@1,0 { 106 device_type = "pci"; 107 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 108 reg = <0x000800 0 0 0 0>; 109 status = "disabled"; 110 111 #address-cells = <3>; 112 #size-cells = <2>; 113 114 ranges; 115 116 nvidia,num-lanes = <2>; 117 }; 118 119 pci@2,0 { 120 device_type = "pci"; 121 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 122 reg = <0x001000 0 0 0 0>; 123 status = "disabled"; 124 125 #address-cells = <3>; 126 #size-cells = <2>; 127 128 ranges; 129 130 nvidia,num-lanes = <2>; 131 }; 132 }; 133 134 135Board DTS: 136 137 pcie-controller { 138 status = "okay"; 139 140 vdd-supply = <&pci_vdd_reg>; 141 pex-clk-supply = <&pci_clk_reg>; 142 143 /* root port 00:01.0 */ 144 pci@1,0 { 145 status = "okay"; 146 147 /* bridge 01:00.0 (optional) */ 148 pci@0,0 { 149 reg = <0x010000 0 0 0 0>; 150 151 #address-cells = <3>; 152 #size-cells = <2>; 153 154 device_type = "pci"; 155 156 /* endpoint 02:00.0 */ 157 pci@0,0 { 158 reg = <0x020000 0 0 0 0>; 159 }; 160 }; 161 }; 162 }; 163 164Note that devices on the PCI bus are dynamically discovered using PCI's bus 165enumeration and therefore don't need corresponding device nodes in DT. However 166if a device on the PCI bus provides a non-probeable bus such as I2C or SPI, 167device nodes need to be added in order to allow the bus' children to be 168instantiated at the proper location in the operating system's device tree (as 169illustrated by the optional nodes in the example above). 170