1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX6 PCIe host controller
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11  - Richard Zhu <hongxing.zhu@nxp.com>
12
13description: |+
14  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
16
17properties:
18  compatible:
19    enum:
20      - fsl,imx6q-pcie
21      - fsl,imx6sx-pcie
22      - fsl,imx6qp-pcie
23      - fsl,imx7d-pcie
24      - fsl,imx8mq-pcie
25      - fsl,imx8mm-pcie
26      - fsl,imx8mp-pcie
27
28  reg:
29    items:
30      - description: Data Bus Interface (DBI) registers.
31      - description: PCIe configuration space region.
32
33  reg-names:
34    items:
35      - const: dbi
36      - const: config
37
38  interrupts:
39    items:
40      - description: builtin MSI controller.
41
42  interrupt-names:
43    items:
44      - const: msi
45
46  clocks:
47    minItems: 3
48    items:
49      - description: PCIe bridge clock.
50      - description: PCIe bus clock.
51      - description: PCIe PHY clock.
52      - description: Additional required clock entry for imx6sx-pcie,
53          imx8mq-pcie.
54
55  clock-names:
56    minItems: 3
57    items:
58      - const: pcie
59      - const: pcie_bus
60      - enum: [ pcie_phy, pcie_aux ]
61      - enum: [ pcie_inbound_axi, pcie_aux ]
62
63  num-lanes:
64    const: 1
65
66  fsl,imx7d-pcie-phy:
67    $ref: /schemas/types.yaml#/definitions/phandle
68    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
69      required properties for imx7d-pcie and imx8mq-pcie.
70
71  power-domains:
72    minItems: 1
73    items:
74      - description: The phandle pointing to the DISPLAY domain for
75          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
76          imx8mq-pcie.
77      - description: The phandle pointing to the PCIE_PHY power domains
78          for imx6sx-pcie.
79
80  power-domain-names:
81    minItems: 1
82    items:
83      - const: pcie
84      - const: pcie_phy
85
86  resets:
87    minItems: 2
88    maxItems: 3
89    description: Phandles to PCIe-related reset lines exposed by SRC
90      IP block. Additional required by imx7d-pcie and imx8mq-pcie.
91
92  reset-names:
93    minItems: 2
94    maxItems: 3
95
96  fsl,tx-deemph-gen1:
97    description: Gen1 De-emphasis value (optional required).
98    $ref: /schemas/types.yaml#/definitions/uint32
99    default: 0
100
101  fsl,tx-deemph-gen2-3p5db:
102    description: Gen2 (3.5db) De-emphasis value (optional required).
103    $ref: /schemas/types.yaml#/definitions/uint32
104    default: 0
105
106  fsl,tx-deemph-gen2-6db:
107    description: Gen2 (6db) De-emphasis value (optional required).
108    $ref: /schemas/types.yaml#/definitions/uint32
109    default: 20
110
111  fsl,tx-swing-full:
112    description: Gen2 TX SWING FULL value (optional required).
113    $ref: /schemas/types.yaml#/definitions/uint32
114    default: 127
115
116  fsl,tx-swing-low:
117    description: TX launch amplitude swing_low value (optional required).
118    $ref: /schemas/types.yaml#/definitions/uint32
119    default: 127
120
121  fsl,max-link-speed:
122    description: Specify PCI Gen for link capability (optional required).
123      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
124      requirements and thus for gen2 capability a gen2 compliant clock
125      generator should be used and configured.
126    $ref: /schemas/types.yaml#/definitions/uint32
127    enum: [1, 2, 3, 4]
128    default: 1
129
130  phys:
131    maxItems: 1
132
133  phy-names:
134    const: pcie-phy
135
136  reset-gpio:
137    description: Should specify the GPIO for controlling the PCI bus device
138      reset signal. It's not polarity aware and defaults to active-low reset
139      sequence (L=reset state, H=operation state) (optional required).
140
141  reset-gpio-active-high:
142    description: If present then the reset sequence using the GPIO
143      specified in the "reset-gpio" property is reversed (H=reset state,
144      L=operation state) (optional required).
145    type: boolean
146
147  vpcie-supply:
148    description: Should specify the regulator in charge of PCIe port power.
149      The regulator will be enabled when initializing the PCIe host and
150      disabled either as part of the init process or when shutting down
151      the host (optional required).
152
153  vph-supply:
154    description: Should specify the regulator in charge of VPH one of
155      the three PCIe PHY powers. This regulator can be supplied by both
156      1.8v and 3.3v voltage supplies (optional required).
157
158required:
159  - compatible
160  - reg
161  - reg-names
162  - "#address-cells"
163  - "#size-cells"
164  - device_type
165  - bus-range
166  - ranges
167  - num-lanes
168  - interrupts
169  - interrupt-names
170  - "#interrupt-cells"
171  - interrupt-map-mask
172  - interrupt-map
173  - clocks
174  - clock-names
175
176allOf:
177  - $ref: /schemas/pci/snps,dw-pcie.yaml#
178  - if:
179      properties:
180        compatible:
181          contains:
182            const: fsl,imx6sx-pcie
183    then:
184      properties:
185        clock-names:
186          items:
187            - {}
188            - {}
189            - const: pcie_phy
190            - const: pcie_inbound_axi
191        power-domains:
192          minItems: 2
193        power-domain-names:
194          minItems: 2
195  - if:
196      properties:
197        compatible:
198          contains:
199            const: fsl,imx8mq-pcie
200    then:
201      properties:
202        clock-names:
203          items:
204            - {}
205            - {}
206            - const: pcie_phy
207            - const: pcie_aux
208  - if:
209      properties:
210        compatible:
211          not:
212            contains:
213              enum:
214                - fsl,imx6sx-pcie
215                - fsl,imx8mq-pcie
216    then:
217      properties:
218        clocks:
219          maxItems: 3
220        clock-names:
221          maxItems: 3
222
223  - if:
224      properties:
225        compatible:
226          contains:
227            enum:
228              - fsl,imx6q-pcie
229              - fsl,imx6qp-pcie
230              - fsl,imx7d-pcie
231    then:
232      properties:
233        clock-names:
234          maxItems: 3
235          contains:
236            const: pcie_phy
237
238  - if:
239      properties:
240        compatible:
241          contains:
242            enum:
243              - fsl,imx8mm-pcie
244              - fsl,imx8mp-pcie
245    then:
246      properties:
247        clock-names:
248          maxItems: 3
249          contains:
250            const: pcie_aux
251  - if:
252      properties:
253        compatible:
254          contains:
255            enum:
256              - fsl,imx6q-pcie
257              - fsl,imx6qp-pcie
258    then:
259      properties:
260        power-domains: false
261        power-domain-names: false
262
263  - if:
264      not:
265        properties:
266          compatible:
267            contains:
268              enum:
269                - fsl,imx6sx-pcie
270                - fsl,imx6q-pcie
271                - fsl,imx6qp-pcie
272    then:
273      properties:
274        power-domains:
275          maxItems: 1
276        power-domain-names: false
277
278  - if:
279      properties:
280        compatible:
281          contains:
282            enum:
283              - fsl,imx6q-pcie
284              - fsl,imx6sx-pcie
285              - fsl,imx6qp-pcie
286              - fsl,imx7d-pcie
287              - fsl,imx8mq-pcie
288    then:
289      properties:
290        resets:
291          minItems: 3
292        reset-names:
293          items:
294            - const: pciephy
295            - const: apps
296            - const: turnoff
297    else:
298      properties:
299        resets:
300          maxItems: 2
301        reset-names:
302          items:
303            - const: apps
304            - const: turnoff
305
306unevaluatedProperties: false
307
308examples:
309  - |
310    #include <dt-bindings/clock/imx6qdl-clock.h>
311    #include <dt-bindings/interrupt-controller/arm-gic.h>
312
313    pcie: pcie@1ffc000 {
314        compatible = "fsl,imx6q-pcie";
315        reg = <0x01ffc000 0x04000>,
316              <0x01f00000 0x80000>;
317        reg-names = "dbi", "config";
318        #address-cells = <3>;
319        #size-cells = <2>;
320        device_type = "pci";
321        bus-range = <0x00 0xff>;
322        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
323                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
324        num-lanes = <1>;
325        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
326        interrupt-names = "msi";
327        #interrupt-cells = <1>;
328        interrupt-map-mask = <0 0 0 0x7>;
329        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
330                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
331                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
332                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
333        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
334                <&clks IMX6QDL_CLK_LVDS1_GATE>,
335                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
336        clock-names = "pcie", "pcie_bus", "pcie_phy";
337    };
338...
339