1751ca492SRichard Zhu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2751ca492SRichard Zhu%YAML 1.2 3751ca492SRichard Zhu--- 4751ca492SRichard Zhu$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5751ca492SRichard Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 6751ca492SRichard Zhu 7751ca492SRichard Zhutitle: Freescale i.MX6 PCIe host controller 8751ca492SRichard Zhu 9751ca492SRichard Zhumaintainers: 10751ca492SRichard Zhu - Lucas Stach <l.stach@pengutronix.de> 11751ca492SRichard Zhu - Richard Zhu <hongxing.zhu@nxp.com> 12751ca492SRichard Zhu 13751ca492SRichard Zhudescription: |+ 14751ca492SRichard Zhu This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15751ca492SRichard Zhu and thus inherits all the common properties defined in snps,dw-pcie.yaml. 16751ca492SRichard Zhu 17751ca492SRichard Zhuproperties: 18751ca492SRichard Zhu compatible: 19751ca492SRichard Zhu enum: 20751ca492SRichard Zhu - fsl,imx6q-pcie 21751ca492SRichard Zhu - fsl,imx6sx-pcie 22751ca492SRichard Zhu - fsl,imx6qp-pcie 23751ca492SRichard Zhu - fsl,imx7d-pcie 24751ca492SRichard Zhu - fsl,imx8mq-pcie 2521d5929fSRichard Zhu - fsl,imx8mm-pcie 269be01ee2SRichard Zhu - fsl,imx8mp-pcie 27751ca492SRichard Zhu 28751ca492SRichard Zhu reg: 29751ca492SRichard Zhu items: 30751ca492SRichard Zhu - description: Data Bus Interface (DBI) registers. 31751ca492SRichard Zhu - description: PCIe configuration space region. 32751ca492SRichard Zhu 33751ca492SRichard Zhu reg-names: 34751ca492SRichard Zhu items: 35751ca492SRichard Zhu - const: dbi 36751ca492SRichard Zhu - const: config 37751ca492SRichard Zhu 38751ca492SRichard Zhu interrupts: 39751ca492SRichard Zhu items: 40751ca492SRichard Zhu - description: builtin MSI controller. 41751ca492SRichard Zhu 42751ca492SRichard Zhu interrupt-names: 43751ca492SRichard Zhu items: 44751ca492SRichard Zhu - const: msi 45751ca492SRichard Zhu 46751ca492SRichard Zhu clocks: 47751ca492SRichard Zhu minItems: 3 48751ca492SRichard Zhu items: 49751ca492SRichard Zhu - description: PCIe bridge clock. 50751ca492SRichard Zhu - description: PCIe bus clock. 51751ca492SRichard Zhu - description: PCIe PHY clock. 52751ca492SRichard Zhu - description: Additional required clock entry for imx6sx-pcie, 53751ca492SRichard Zhu imx8mq-pcie. 54751ca492SRichard Zhu 55751ca492SRichard Zhu clock-names: 56751ca492SRichard Zhu minItems: 3 57751ca492SRichard Zhu items: 58751ca492SRichard Zhu - const: pcie 59751ca492SRichard Zhu - const: pcie_bus 60751ca492SRichard Zhu - const: pcie_phy 61*b8a83e60SSerge Semin - enum: [ pcie_inbound_axi, pcie_aux ] 62751ca492SRichard Zhu 63751ca492SRichard Zhu num-lanes: 64751ca492SRichard Zhu const: 1 65751ca492SRichard Zhu 66751ca492SRichard Zhu fsl,imx7d-pcie-phy: 67751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/phandle 68751ca492SRichard Zhu description: A phandle to an fsl,imx7d-pcie-phy node. Additional 69751ca492SRichard Zhu required properties for imx7d-pcie and imx8mq-pcie. 70751ca492SRichard Zhu 71751ca492SRichard Zhu power-domains: 72751ca492SRichard Zhu items: 73751ca492SRichard Zhu - description: The phandle pointing to the DISPLAY domain for 74751ca492SRichard Zhu imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and 75751ca492SRichard Zhu imx8mq-pcie. 76751ca492SRichard Zhu - description: The phandle pointing to the PCIE_PHY power domains 77751ca492SRichard Zhu for imx6sx-pcie. 78751ca492SRichard Zhu 79751ca492SRichard Zhu power-domain-names: 80751ca492SRichard Zhu items: 81751ca492SRichard Zhu - const: pcie 82751ca492SRichard Zhu - const: pcie_phy 83751ca492SRichard Zhu 84751ca492SRichard Zhu resets: 85751ca492SRichard Zhu maxItems: 3 86751ca492SRichard Zhu description: Phandles to PCIe-related reset lines exposed by SRC 87751ca492SRichard Zhu IP block. Additional required by imx7d-pcie and imx8mq-pcie. 88751ca492SRichard Zhu 89751ca492SRichard Zhu reset-names: 90751ca492SRichard Zhu items: 91751ca492SRichard Zhu - const: pciephy 92751ca492SRichard Zhu - const: apps 93751ca492SRichard Zhu - const: turnoff 94751ca492SRichard Zhu 95751ca492SRichard Zhu fsl,tx-deemph-gen1: 96751ca492SRichard Zhu description: Gen1 De-emphasis value (optional required). 97751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 98751ca492SRichard Zhu default: 0 99751ca492SRichard Zhu 100751ca492SRichard Zhu fsl,tx-deemph-gen2-3p5db: 101751ca492SRichard Zhu description: Gen2 (3.5db) De-emphasis value (optional required). 102751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 103751ca492SRichard Zhu default: 0 104751ca492SRichard Zhu 105751ca492SRichard Zhu fsl,tx-deemph-gen2-6db: 106751ca492SRichard Zhu description: Gen2 (6db) De-emphasis value (optional required). 107751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 108751ca492SRichard Zhu default: 20 109751ca492SRichard Zhu 110751ca492SRichard Zhu fsl,tx-swing-full: 111751ca492SRichard Zhu description: Gen2 TX SWING FULL value (optional required). 112751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 113751ca492SRichard Zhu default: 127 114751ca492SRichard Zhu 115751ca492SRichard Zhu fsl,tx-swing-low: 116751ca492SRichard Zhu description: TX launch amplitude swing_low value (optional required). 117751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 118751ca492SRichard Zhu default: 127 119751ca492SRichard Zhu 120751ca492SRichard Zhu fsl,max-link-speed: 121751ca492SRichard Zhu description: Specify PCI Gen for link capability (optional required). 122751ca492SRichard Zhu Note that the IMX6 LVDS clock outputs do not meet gen2 jitter 123751ca492SRichard Zhu requirements and thus for gen2 capability a gen2 compliant clock 124751ca492SRichard Zhu generator should be used and configured. 125751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 126751ca492SRichard Zhu enum: [1, 2, 3, 4] 127751ca492SRichard Zhu default: 1 128751ca492SRichard Zhu 1293e15f623SRichard Zhu phys: 1303e15f623SRichard Zhu maxItems: 1 1313e15f623SRichard Zhu 1323e15f623SRichard Zhu phy-names: 1333e15f623SRichard Zhu const: pcie-phy 1343e15f623SRichard Zhu 135751ca492SRichard Zhu reset-gpio: 136751ca492SRichard Zhu description: Should specify the GPIO for controlling the PCI bus device 137751ca492SRichard Zhu reset signal. It's not polarity aware and defaults to active-low reset 138751ca492SRichard Zhu sequence (L=reset state, H=operation state) (optional required). 139751ca492SRichard Zhu 140751ca492SRichard Zhu reset-gpio-active-high: 141751ca492SRichard Zhu description: If present then the reset sequence using the GPIO 142751ca492SRichard Zhu specified in the "reset-gpio" property is reversed (H=reset state, 143751ca492SRichard Zhu L=operation state) (optional required). 144fba48662SRob Herring type: boolean 145751ca492SRichard Zhu 146751ca492SRichard Zhu vpcie-supply: 147751ca492SRichard Zhu description: Should specify the regulator in charge of PCIe port power. 148751ca492SRichard Zhu The regulator will be enabled when initializing the PCIe host and 149751ca492SRichard Zhu disabled either as part of the init process or when shutting down 150751ca492SRichard Zhu the host (optional required). 151751ca492SRichard Zhu 152751ca492SRichard Zhu vph-supply: 153751ca492SRichard Zhu description: Should specify the regulator in charge of VPH one of 154751ca492SRichard Zhu the three PCIe PHY powers. This regulator can be supplied by both 155751ca492SRichard Zhu 1.8v and 3.3v voltage supplies (optional required). 156751ca492SRichard Zhu 157751ca492SRichard Zhurequired: 158751ca492SRichard Zhu - compatible 159751ca492SRichard Zhu - reg 160751ca492SRichard Zhu - reg-names 161751ca492SRichard Zhu - "#address-cells" 162751ca492SRichard Zhu - "#size-cells" 163751ca492SRichard Zhu - device_type 164751ca492SRichard Zhu - bus-range 165751ca492SRichard Zhu - ranges 166751ca492SRichard Zhu - num-lanes 167751ca492SRichard Zhu - interrupts 168751ca492SRichard Zhu - interrupt-names 169751ca492SRichard Zhu - "#interrupt-cells" 170751ca492SRichard Zhu - interrupt-map-mask 171751ca492SRichard Zhu - interrupt-map 172751ca492SRichard Zhu - clocks 173751ca492SRichard Zhu - clock-names 174751ca492SRichard Zhu 175*b8a83e60SSerge SeminallOf: 176*b8a83e60SSerge Semin - $ref: /schemas/pci/snps,dw-pcie.yaml# 177*b8a83e60SSerge Semin - if: 178*b8a83e60SSerge Semin properties: 179*b8a83e60SSerge Semin compatible: 180*b8a83e60SSerge Semin contains: 181*b8a83e60SSerge Semin const: fsl,imx6sx-pcie 182*b8a83e60SSerge Semin then: 183*b8a83e60SSerge Semin properties: 184*b8a83e60SSerge Semin clock-names: 185*b8a83e60SSerge Semin items: 186*b8a83e60SSerge Semin - {} 187*b8a83e60SSerge Semin - {} 188*b8a83e60SSerge Semin - {} 189*b8a83e60SSerge Semin - const: pcie_inbound_axi 190*b8a83e60SSerge Semin - if: 191*b8a83e60SSerge Semin properties: 192*b8a83e60SSerge Semin compatible: 193*b8a83e60SSerge Semin contains: 194*b8a83e60SSerge Semin const: fsl,imx8mq-pcie 195*b8a83e60SSerge Semin then: 196*b8a83e60SSerge Semin properties: 197*b8a83e60SSerge Semin clock-names: 198*b8a83e60SSerge Semin items: 199*b8a83e60SSerge Semin - {} 200*b8a83e60SSerge Semin - {} 201*b8a83e60SSerge Semin - {} 202*b8a83e60SSerge Semin - const: pcie_aux 203*b8a83e60SSerge Semin - if: 204*b8a83e60SSerge Semin properties: 205*b8a83e60SSerge Semin compatible: 206*b8a83e60SSerge Semin not: 207*b8a83e60SSerge Semin contains: 208*b8a83e60SSerge Semin enum: 209*b8a83e60SSerge Semin - fsl,imx6sx-pcie 210*b8a83e60SSerge Semin - fsl,imx8mq-pcie 211*b8a83e60SSerge Semin then: 212*b8a83e60SSerge Semin properties: 213*b8a83e60SSerge Semin clock-names: 214*b8a83e60SSerge Semin maxItems: 3 215*b8a83e60SSerge Semin 216751ca492SRichard ZhuunevaluatedProperties: false 217751ca492SRichard Zhu 218751ca492SRichard Zhuexamples: 219751ca492SRichard Zhu - | 220751ca492SRichard Zhu #include <dt-bindings/clock/imx6qdl-clock.h> 221751ca492SRichard Zhu #include <dt-bindings/interrupt-controller/arm-gic.h> 222751ca492SRichard Zhu 223751ca492SRichard Zhu pcie: pcie@1ffc000 { 224751ca492SRichard Zhu compatible = "fsl,imx6q-pcie"; 225751ca492SRichard Zhu reg = <0x01ffc000 0x04000>, 226751ca492SRichard Zhu <0x01f00000 0x80000>; 227751ca492SRichard Zhu reg-names = "dbi", "config"; 228751ca492SRichard Zhu #address-cells = <3>; 229751ca492SRichard Zhu #size-cells = <2>; 230751ca492SRichard Zhu device_type = "pci"; 231751ca492SRichard Zhu bus-range = <0x00 0xff>; 232751ca492SRichard Zhu ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, 233751ca492SRichard Zhu <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; 234751ca492SRichard Zhu num-lanes = <1>; 235751ca492SRichard Zhu interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 236751ca492SRichard Zhu interrupt-names = "msi"; 237751ca492SRichard Zhu #interrupt-cells = <1>; 238751ca492SRichard Zhu interrupt-map-mask = <0 0 0 0x7>; 239751ca492SRichard Zhu interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 240751ca492SRichard Zhu <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 241751ca492SRichard Zhu <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 242751ca492SRichard Zhu <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 243751ca492SRichard Zhu clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 244751ca492SRichard Zhu <&clks IMX6QDL_CLK_LVDS1_GATE>, 245751ca492SRichard Zhu <&clks IMX6QDL_CLK_PCIE_REF_125M>; 246751ca492SRichard Zhu clock-names = "pcie", "pcie_bus", "pcie_phy"; 247751ca492SRichard Zhu }; 248751ca492SRichard Zhu... 249