1*751ca492SRichard Zhu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*751ca492SRichard Zhu%YAML 1.2 3*751ca492SRichard Zhu--- 4*751ca492SRichard Zhu$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5*751ca492SRichard Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*751ca492SRichard Zhu 7*751ca492SRichard Zhutitle: Freescale i.MX6 PCIe host controller 8*751ca492SRichard Zhu 9*751ca492SRichard Zhumaintainers: 10*751ca492SRichard Zhu - Lucas Stach <l.stach@pengutronix.de> 11*751ca492SRichard Zhu - Richard Zhu <hongxing.zhu@nxp.com> 12*751ca492SRichard Zhu 13*751ca492SRichard Zhudescription: |+ 14*751ca492SRichard Zhu This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15*751ca492SRichard Zhu and thus inherits all the common properties defined in snps,dw-pcie.yaml. 16*751ca492SRichard Zhu 17*751ca492SRichard ZhuallOf: 18*751ca492SRichard Zhu - $ref: /schemas/pci/snps,dw-pcie.yaml# 19*751ca492SRichard Zhu 20*751ca492SRichard Zhuproperties: 21*751ca492SRichard Zhu compatible: 22*751ca492SRichard Zhu enum: 23*751ca492SRichard Zhu - fsl,imx6q-pcie 24*751ca492SRichard Zhu - fsl,imx6sx-pcie 25*751ca492SRichard Zhu - fsl,imx6qp-pcie 26*751ca492SRichard Zhu - fsl,imx7d-pcie 27*751ca492SRichard Zhu - fsl,imx8mq-pcie 28*751ca492SRichard Zhu 29*751ca492SRichard Zhu reg: 30*751ca492SRichard Zhu items: 31*751ca492SRichard Zhu - description: Data Bus Interface (DBI) registers. 32*751ca492SRichard Zhu - description: PCIe configuration space region. 33*751ca492SRichard Zhu 34*751ca492SRichard Zhu reg-names: 35*751ca492SRichard Zhu items: 36*751ca492SRichard Zhu - const: dbi 37*751ca492SRichard Zhu - const: config 38*751ca492SRichard Zhu 39*751ca492SRichard Zhu interrupts: 40*751ca492SRichard Zhu items: 41*751ca492SRichard Zhu - description: builtin MSI controller. 42*751ca492SRichard Zhu 43*751ca492SRichard Zhu interrupt-names: 44*751ca492SRichard Zhu minItems: 1 45*751ca492SRichard Zhu items: 46*751ca492SRichard Zhu - const: msi 47*751ca492SRichard Zhu 48*751ca492SRichard Zhu clocks: 49*751ca492SRichard Zhu minItems: 3 50*751ca492SRichard Zhu items: 51*751ca492SRichard Zhu - description: PCIe bridge clock. 52*751ca492SRichard Zhu - description: PCIe bus clock. 53*751ca492SRichard Zhu - description: PCIe PHY clock. 54*751ca492SRichard Zhu - description: Additional required clock entry for imx6sx-pcie, 55*751ca492SRichard Zhu imx8mq-pcie. 56*751ca492SRichard Zhu 57*751ca492SRichard Zhu clock-names: 58*751ca492SRichard Zhu minItems: 3 59*751ca492SRichard Zhu items: 60*751ca492SRichard Zhu - const: pcie 61*751ca492SRichard Zhu - const: pcie_bus 62*751ca492SRichard Zhu - const: pcie_phy 63*751ca492SRichard Zhu - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie 64*751ca492SRichard Zhu 65*751ca492SRichard Zhu num-lanes: 66*751ca492SRichard Zhu const: 1 67*751ca492SRichard Zhu 68*751ca492SRichard Zhu fsl,imx7d-pcie-phy: 69*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/phandle 70*751ca492SRichard Zhu description: A phandle to an fsl,imx7d-pcie-phy node. Additional 71*751ca492SRichard Zhu required properties for imx7d-pcie and imx8mq-pcie. 72*751ca492SRichard Zhu 73*751ca492SRichard Zhu power-domains: 74*751ca492SRichard Zhu items: 75*751ca492SRichard Zhu - description: The phandle pointing to the DISPLAY domain for 76*751ca492SRichard Zhu imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and 77*751ca492SRichard Zhu imx8mq-pcie. 78*751ca492SRichard Zhu - description: The phandle pointing to the PCIE_PHY power domains 79*751ca492SRichard Zhu for imx6sx-pcie. 80*751ca492SRichard Zhu 81*751ca492SRichard Zhu power-domain-names: 82*751ca492SRichard Zhu items: 83*751ca492SRichard Zhu - const: pcie 84*751ca492SRichard Zhu - const: pcie_phy 85*751ca492SRichard Zhu 86*751ca492SRichard Zhu resets: 87*751ca492SRichard Zhu maxItems: 3 88*751ca492SRichard Zhu description: Phandles to PCIe-related reset lines exposed by SRC 89*751ca492SRichard Zhu IP block. Additional required by imx7d-pcie and imx8mq-pcie. 90*751ca492SRichard Zhu 91*751ca492SRichard Zhu reset-names: 92*751ca492SRichard Zhu items: 93*751ca492SRichard Zhu - const: pciephy 94*751ca492SRichard Zhu - const: apps 95*751ca492SRichard Zhu - const: turnoff 96*751ca492SRichard Zhu 97*751ca492SRichard Zhu fsl,tx-deemph-gen1: 98*751ca492SRichard Zhu description: Gen1 De-emphasis value (optional required). 99*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 100*751ca492SRichard Zhu default: 0 101*751ca492SRichard Zhu 102*751ca492SRichard Zhu fsl,tx-deemph-gen2-3p5db: 103*751ca492SRichard Zhu description: Gen2 (3.5db) De-emphasis value (optional required). 104*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 105*751ca492SRichard Zhu default: 0 106*751ca492SRichard Zhu 107*751ca492SRichard Zhu fsl,tx-deemph-gen2-6db: 108*751ca492SRichard Zhu description: Gen2 (6db) De-emphasis value (optional required). 109*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 110*751ca492SRichard Zhu default: 20 111*751ca492SRichard Zhu 112*751ca492SRichard Zhu fsl,tx-swing-full: 113*751ca492SRichard Zhu description: Gen2 TX SWING FULL value (optional required). 114*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 115*751ca492SRichard Zhu default: 127 116*751ca492SRichard Zhu 117*751ca492SRichard Zhu fsl,tx-swing-low: 118*751ca492SRichard Zhu description: TX launch amplitude swing_low value (optional required). 119*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 120*751ca492SRichard Zhu default: 127 121*751ca492SRichard Zhu 122*751ca492SRichard Zhu fsl,max-link-speed: 123*751ca492SRichard Zhu description: Specify PCI Gen for link capability (optional required). 124*751ca492SRichard Zhu Note that the IMX6 LVDS clock outputs do not meet gen2 jitter 125*751ca492SRichard Zhu requirements and thus for gen2 capability a gen2 compliant clock 126*751ca492SRichard Zhu generator should be used and configured. 127*751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 128*751ca492SRichard Zhu enum: [1, 2, 3, 4] 129*751ca492SRichard Zhu default: 1 130*751ca492SRichard Zhu 131*751ca492SRichard Zhu reset-gpio: 132*751ca492SRichard Zhu description: Should specify the GPIO for controlling the PCI bus device 133*751ca492SRichard Zhu reset signal. It's not polarity aware and defaults to active-low reset 134*751ca492SRichard Zhu sequence (L=reset state, H=operation state) (optional required). 135*751ca492SRichard Zhu 136*751ca492SRichard Zhu reset-gpio-active-high: 137*751ca492SRichard Zhu description: If present then the reset sequence using the GPIO 138*751ca492SRichard Zhu specified in the "reset-gpio" property is reversed (H=reset state, 139*751ca492SRichard Zhu L=operation state) (optional required). 140*751ca492SRichard Zhu 141*751ca492SRichard Zhu vpcie-supply: 142*751ca492SRichard Zhu description: Should specify the regulator in charge of PCIe port power. 143*751ca492SRichard Zhu The regulator will be enabled when initializing the PCIe host and 144*751ca492SRichard Zhu disabled either as part of the init process or when shutting down 145*751ca492SRichard Zhu the host (optional required). 146*751ca492SRichard Zhu 147*751ca492SRichard Zhu vph-supply: 148*751ca492SRichard Zhu description: Should specify the regulator in charge of VPH one of 149*751ca492SRichard Zhu the three PCIe PHY powers. This regulator can be supplied by both 150*751ca492SRichard Zhu 1.8v and 3.3v voltage supplies (optional required). 151*751ca492SRichard Zhu 152*751ca492SRichard Zhurequired: 153*751ca492SRichard Zhu - compatible 154*751ca492SRichard Zhu - reg 155*751ca492SRichard Zhu - reg-names 156*751ca492SRichard Zhu - "#address-cells" 157*751ca492SRichard Zhu - "#size-cells" 158*751ca492SRichard Zhu - device_type 159*751ca492SRichard Zhu - bus-range 160*751ca492SRichard Zhu - ranges 161*751ca492SRichard Zhu - num-lanes 162*751ca492SRichard Zhu - interrupts 163*751ca492SRichard Zhu - interrupt-names 164*751ca492SRichard Zhu - "#interrupt-cells" 165*751ca492SRichard Zhu - interrupt-map-mask 166*751ca492SRichard Zhu - interrupt-map 167*751ca492SRichard Zhu - clocks 168*751ca492SRichard Zhu - clock-names 169*751ca492SRichard Zhu 170*751ca492SRichard ZhuunevaluatedProperties: false 171*751ca492SRichard Zhu 172*751ca492SRichard Zhuexamples: 173*751ca492SRichard Zhu - | 174*751ca492SRichard Zhu #include <dt-bindings/clock/imx6qdl-clock.h> 175*751ca492SRichard Zhu #include <dt-bindings/interrupt-controller/arm-gic.h> 176*751ca492SRichard Zhu 177*751ca492SRichard Zhu pcie: pcie@1ffc000 { 178*751ca492SRichard Zhu compatible = "fsl,imx6q-pcie"; 179*751ca492SRichard Zhu reg = <0x01ffc000 0x04000>, 180*751ca492SRichard Zhu <0x01f00000 0x80000>; 181*751ca492SRichard Zhu reg-names = "dbi", "config"; 182*751ca492SRichard Zhu #address-cells = <3>; 183*751ca492SRichard Zhu #size-cells = <2>; 184*751ca492SRichard Zhu device_type = "pci"; 185*751ca492SRichard Zhu bus-range = <0x00 0xff>; 186*751ca492SRichard Zhu ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, 187*751ca492SRichard Zhu <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; 188*751ca492SRichard Zhu num-lanes = <1>; 189*751ca492SRichard Zhu interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 190*751ca492SRichard Zhu interrupt-names = "msi"; 191*751ca492SRichard Zhu #interrupt-cells = <1>; 192*751ca492SRichard Zhu interrupt-map-mask = <0 0 0 0x7>; 193*751ca492SRichard Zhu interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 194*751ca492SRichard Zhu <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 195*751ca492SRichard Zhu <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 196*751ca492SRichard Zhu <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 197*751ca492SRichard Zhu clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 198*751ca492SRichard Zhu <&clks IMX6QDL_CLK_LVDS1_GATE>, 199*751ca492SRichard Zhu <&clks IMX6QDL_CLK_PCIE_REF_125M>; 200*751ca492SRichard Zhu clock-names = "pcie", "pcie_bus", "pcie_phy"; 201*751ca492SRichard Zhu }; 202*751ca492SRichard Zhu... 203