1751ca492SRichard Zhu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2751ca492SRichard Zhu%YAML 1.2 3751ca492SRichard Zhu--- 4751ca492SRichard Zhu$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml# 5751ca492SRichard Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 6751ca492SRichard Zhu 7751ca492SRichard Zhutitle: Freescale i.MX6 PCIe host controller 8751ca492SRichard Zhu 9751ca492SRichard Zhumaintainers: 10751ca492SRichard Zhu - Lucas Stach <l.stach@pengutronix.de> 11751ca492SRichard Zhu - Richard Zhu <hongxing.zhu@nxp.com> 12751ca492SRichard Zhu 13751ca492SRichard Zhudescription: |+ 14751ca492SRichard Zhu This PCIe host controller is based on the Synopsys DesignWare PCIe IP 15751ca492SRichard Zhu and thus inherits all the common properties defined in snps,dw-pcie.yaml. 16751ca492SRichard Zhu 17751ca492SRichard ZhuallOf: 18751ca492SRichard Zhu - $ref: /schemas/pci/snps,dw-pcie.yaml# 19751ca492SRichard Zhu 20751ca492SRichard Zhuproperties: 21751ca492SRichard Zhu compatible: 22751ca492SRichard Zhu enum: 23751ca492SRichard Zhu - fsl,imx6q-pcie 24751ca492SRichard Zhu - fsl,imx6sx-pcie 25751ca492SRichard Zhu - fsl,imx6qp-pcie 26751ca492SRichard Zhu - fsl,imx7d-pcie 27751ca492SRichard Zhu - fsl,imx8mq-pcie 28*21d5929fSRichard Zhu - fsl,imx8mm-pcie 29751ca492SRichard Zhu 30751ca492SRichard Zhu reg: 31751ca492SRichard Zhu items: 32751ca492SRichard Zhu - description: Data Bus Interface (DBI) registers. 33751ca492SRichard Zhu - description: PCIe configuration space region. 34751ca492SRichard Zhu 35751ca492SRichard Zhu reg-names: 36751ca492SRichard Zhu items: 37751ca492SRichard Zhu - const: dbi 38751ca492SRichard Zhu - const: config 39751ca492SRichard Zhu 40751ca492SRichard Zhu interrupts: 41751ca492SRichard Zhu items: 42751ca492SRichard Zhu - description: builtin MSI controller. 43751ca492SRichard Zhu 44751ca492SRichard Zhu interrupt-names: 45751ca492SRichard Zhu items: 46751ca492SRichard Zhu - const: msi 47751ca492SRichard Zhu 48751ca492SRichard Zhu clocks: 49751ca492SRichard Zhu minItems: 3 50751ca492SRichard Zhu items: 51751ca492SRichard Zhu - description: PCIe bridge clock. 52751ca492SRichard Zhu - description: PCIe bus clock. 53751ca492SRichard Zhu - description: PCIe PHY clock. 54751ca492SRichard Zhu - description: Additional required clock entry for imx6sx-pcie, 55751ca492SRichard Zhu imx8mq-pcie. 56751ca492SRichard Zhu 57751ca492SRichard Zhu clock-names: 58751ca492SRichard Zhu minItems: 3 59751ca492SRichard Zhu items: 60751ca492SRichard Zhu - const: pcie 61751ca492SRichard Zhu - const: pcie_bus 62751ca492SRichard Zhu - const: pcie_phy 63751ca492SRichard Zhu - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie 64751ca492SRichard Zhu 65751ca492SRichard Zhu num-lanes: 66751ca492SRichard Zhu const: 1 67751ca492SRichard Zhu 68751ca492SRichard Zhu fsl,imx7d-pcie-phy: 69751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/phandle 70751ca492SRichard Zhu description: A phandle to an fsl,imx7d-pcie-phy node. Additional 71751ca492SRichard Zhu required properties for imx7d-pcie and imx8mq-pcie. 72751ca492SRichard Zhu 73751ca492SRichard Zhu power-domains: 74751ca492SRichard Zhu items: 75751ca492SRichard Zhu - description: The phandle pointing to the DISPLAY domain for 76751ca492SRichard Zhu imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and 77751ca492SRichard Zhu imx8mq-pcie. 78751ca492SRichard Zhu - description: The phandle pointing to the PCIE_PHY power domains 79751ca492SRichard Zhu for imx6sx-pcie. 80751ca492SRichard Zhu 81751ca492SRichard Zhu power-domain-names: 82751ca492SRichard Zhu items: 83751ca492SRichard Zhu - const: pcie 84751ca492SRichard Zhu - const: pcie_phy 85751ca492SRichard Zhu 86751ca492SRichard Zhu resets: 87751ca492SRichard Zhu maxItems: 3 88751ca492SRichard Zhu description: Phandles to PCIe-related reset lines exposed by SRC 89751ca492SRichard Zhu IP block. Additional required by imx7d-pcie and imx8mq-pcie. 90751ca492SRichard Zhu 91751ca492SRichard Zhu reset-names: 92751ca492SRichard Zhu items: 93751ca492SRichard Zhu - const: pciephy 94751ca492SRichard Zhu - const: apps 95751ca492SRichard Zhu - const: turnoff 96751ca492SRichard Zhu 97751ca492SRichard Zhu fsl,tx-deemph-gen1: 98751ca492SRichard Zhu description: Gen1 De-emphasis value (optional required). 99751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 100751ca492SRichard Zhu default: 0 101751ca492SRichard Zhu 102751ca492SRichard Zhu fsl,tx-deemph-gen2-3p5db: 103751ca492SRichard Zhu description: Gen2 (3.5db) De-emphasis value (optional required). 104751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 105751ca492SRichard Zhu default: 0 106751ca492SRichard Zhu 107751ca492SRichard Zhu fsl,tx-deemph-gen2-6db: 108751ca492SRichard Zhu description: Gen2 (6db) De-emphasis value (optional required). 109751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 110751ca492SRichard Zhu default: 20 111751ca492SRichard Zhu 112751ca492SRichard Zhu fsl,tx-swing-full: 113751ca492SRichard Zhu description: Gen2 TX SWING FULL value (optional required). 114751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 115751ca492SRichard Zhu default: 127 116751ca492SRichard Zhu 117751ca492SRichard Zhu fsl,tx-swing-low: 118751ca492SRichard Zhu description: TX launch amplitude swing_low value (optional required). 119751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 120751ca492SRichard Zhu default: 127 121751ca492SRichard Zhu 122751ca492SRichard Zhu fsl,max-link-speed: 123751ca492SRichard Zhu description: Specify PCI Gen for link capability (optional required). 124751ca492SRichard Zhu Note that the IMX6 LVDS clock outputs do not meet gen2 jitter 125751ca492SRichard Zhu requirements and thus for gen2 capability a gen2 compliant clock 126751ca492SRichard Zhu generator should be used and configured. 127751ca492SRichard Zhu $ref: /schemas/types.yaml#/definitions/uint32 128751ca492SRichard Zhu enum: [1, 2, 3, 4] 129751ca492SRichard Zhu default: 1 130751ca492SRichard Zhu 1313e15f623SRichard Zhu phys: 1323e15f623SRichard Zhu maxItems: 1 1333e15f623SRichard Zhu 1343e15f623SRichard Zhu phy-names: 1353e15f623SRichard Zhu const: pcie-phy 1363e15f623SRichard Zhu 137751ca492SRichard Zhu reset-gpio: 138751ca492SRichard Zhu description: Should specify the GPIO for controlling the PCI bus device 139751ca492SRichard Zhu reset signal. It's not polarity aware and defaults to active-low reset 140751ca492SRichard Zhu sequence (L=reset state, H=operation state) (optional required). 141751ca492SRichard Zhu 142751ca492SRichard Zhu reset-gpio-active-high: 143751ca492SRichard Zhu description: If present then the reset sequence using the GPIO 144751ca492SRichard Zhu specified in the "reset-gpio" property is reversed (H=reset state, 145751ca492SRichard Zhu L=operation state) (optional required). 146751ca492SRichard Zhu 147751ca492SRichard Zhu vpcie-supply: 148751ca492SRichard Zhu description: Should specify the regulator in charge of PCIe port power. 149751ca492SRichard Zhu The regulator will be enabled when initializing the PCIe host and 150751ca492SRichard Zhu disabled either as part of the init process or when shutting down 151751ca492SRichard Zhu the host (optional required). 152751ca492SRichard Zhu 153751ca492SRichard Zhu vph-supply: 154751ca492SRichard Zhu description: Should specify the regulator in charge of VPH one of 155751ca492SRichard Zhu the three PCIe PHY powers. This regulator can be supplied by both 156751ca492SRichard Zhu 1.8v and 3.3v voltage supplies (optional required). 157751ca492SRichard Zhu 158751ca492SRichard Zhurequired: 159751ca492SRichard Zhu - compatible 160751ca492SRichard Zhu - reg 161751ca492SRichard Zhu - reg-names 162751ca492SRichard Zhu - "#address-cells" 163751ca492SRichard Zhu - "#size-cells" 164751ca492SRichard Zhu - device_type 165751ca492SRichard Zhu - bus-range 166751ca492SRichard Zhu - ranges 167751ca492SRichard Zhu - num-lanes 168751ca492SRichard Zhu - interrupts 169751ca492SRichard Zhu - interrupt-names 170751ca492SRichard Zhu - "#interrupt-cells" 171751ca492SRichard Zhu - interrupt-map-mask 172751ca492SRichard Zhu - interrupt-map 173751ca492SRichard Zhu - clocks 174751ca492SRichard Zhu - clock-names 175751ca492SRichard Zhu 176751ca492SRichard ZhuunevaluatedProperties: false 177751ca492SRichard Zhu 178751ca492SRichard Zhuexamples: 179751ca492SRichard Zhu - | 180751ca492SRichard Zhu #include <dt-bindings/clock/imx6qdl-clock.h> 181751ca492SRichard Zhu #include <dt-bindings/interrupt-controller/arm-gic.h> 182751ca492SRichard Zhu 183751ca492SRichard Zhu pcie: pcie@1ffc000 { 184751ca492SRichard Zhu compatible = "fsl,imx6q-pcie"; 185751ca492SRichard Zhu reg = <0x01ffc000 0x04000>, 186751ca492SRichard Zhu <0x01f00000 0x80000>; 187751ca492SRichard Zhu reg-names = "dbi", "config"; 188751ca492SRichard Zhu #address-cells = <3>; 189751ca492SRichard Zhu #size-cells = <2>; 190751ca492SRichard Zhu device_type = "pci"; 191751ca492SRichard Zhu bus-range = <0x00 0xff>; 192751ca492SRichard Zhu ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, 193751ca492SRichard Zhu <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; 194751ca492SRichard Zhu num-lanes = <1>; 195751ca492SRichard Zhu interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 196751ca492SRichard Zhu interrupt-names = "msi"; 197751ca492SRichard Zhu #interrupt-cells = <1>; 198751ca492SRichard Zhu interrupt-map-mask = <0 0 0 0x7>; 199751ca492SRichard Zhu interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 200751ca492SRichard Zhu <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 201751ca492SRichard Zhu <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 202751ca492SRichard Zhu <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 203751ca492SRichard Zhu clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 204751ca492SRichard Zhu <&clks IMX6QDL_CLK_LVDS1_GATE>, 205751ca492SRichard Zhu <&clks IMX6QDL_CLK_PCIE_REF_125M>; 206751ca492SRichard Zhu clock-names = "pcie", "pcie_bus", "pcie_phy"; 207751ca492SRichard Zhu }; 208751ca492SRichard Zhu... 209