1*b10f8238SRichard Zhu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b10f8238SRichard Zhu%YAML 1.2 3*b10f8238SRichard Zhu--- 4*b10f8238SRichard Zhu$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# 5*b10f8238SRichard Zhu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b10f8238SRichard Zhu 7*b10f8238SRichard Zhutitle: Freescale i.MX6 PCIe Endpoint controller 8*b10f8238SRichard Zhu 9*b10f8238SRichard Zhumaintainers: 10*b10f8238SRichard Zhu - Lucas Stach <l.stach@pengutronix.de> 11*b10f8238SRichard Zhu - Richard Zhu <hongxing.zhu@nxp.com> 12*b10f8238SRichard Zhu 13*b10f8238SRichard Zhudescription: |+ 14*b10f8238SRichard Zhu This PCIe controller is based on the Synopsys DesignWare PCIe IP and 15*b10f8238SRichard Zhu thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. 16*b10f8238SRichard Zhu The controller instances are dual mode where in they can work either in 17*b10f8238SRichard Zhu Root Port mode or Endpoint mode but one at a time. 18*b10f8238SRichard Zhu 19*b10f8238SRichard Zhuproperties: 20*b10f8238SRichard Zhu compatible: 21*b10f8238SRichard Zhu enum: 22*b10f8238SRichard Zhu - fsl,imx8mm-pcie-ep 23*b10f8238SRichard Zhu - fsl,imx8mq-pcie-ep 24*b10f8238SRichard Zhu - fsl,imx8mp-pcie-ep 25*b10f8238SRichard Zhu 26*b10f8238SRichard Zhu reg: 27*b10f8238SRichard Zhu minItems: 2 28*b10f8238SRichard Zhu 29*b10f8238SRichard Zhu reg-names: 30*b10f8238SRichard Zhu items: 31*b10f8238SRichard Zhu - const: dbi 32*b10f8238SRichard Zhu - const: addr_space 33*b10f8238SRichard Zhu 34*b10f8238SRichard Zhu interrupts: 35*b10f8238SRichard Zhu items: 36*b10f8238SRichard Zhu - description: builtin eDMA interrupter. 37*b10f8238SRichard Zhu 38*b10f8238SRichard Zhu interrupt-names: 39*b10f8238SRichard Zhu items: 40*b10f8238SRichard Zhu - const: dma 41*b10f8238SRichard Zhu 42*b10f8238SRichard Zhurequired: 43*b10f8238SRichard Zhu - compatible 44*b10f8238SRichard Zhu - reg 45*b10f8238SRichard Zhu - reg-names 46*b10f8238SRichard Zhu - interrupts 47*b10f8238SRichard Zhu - interrupt-names 48*b10f8238SRichard Zhu 49*b10f8238SRichard ZhuallOf: 50*b10f8238SRichard Zhu - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 51*b10f8238SRichard Zhu - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# 52*b10f8238SRichard Zhu 53*b10f8238SRichard ZhuunevaluatedProperties: false 54*b10f8238SRichard Zhu 55*b10f8238SRichard Zhuexamples: 56*b10f8238SRichard Zhu - | 57*b10f8238SRichard Zhu #include <dt-bindings/clock/imx8mp-clock.h> 58*b10f8238SRichard Zhu #include <dt-bindings/power/imx8mp-power.h> 59*b10f8238SRichard Zhu #include <dt-bindings/reset/imx8mp-reset.h> 60*b10f8238SRichard Zhu #include <dt-bindings/interrupt-controller/arm-gic.h> 61*b10f8238SRichard Zhu 62*b10f8238SRichard Zhu pcie_ep: pcie-ep@33800000 { 63*b10f8238SRichard Zhu compatible = "fsl,imx8mp-pcie-ep"; 64*b10f8238SRichard Zhu reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 65*b10f8238SRichard Zhu reg-names = "dbi", "addr_space"; 66*b10f8238SRichard Zhu clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 67*b10f8238SRichard Zhu <&clk IMX8MP_CLK_HSIO_AXI>, 68*b10f8238SRichard Zhu <&clk IMX8MP_CLK_PCIE_ROOT>; 69*b10f8238SRichard Zhu clock-names = "pcie", "pcie_bus", "pcie_aux"; 70*b10f8238SRichard Zhu assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 71*b10f8238SRichard Zhu assigned-clock-rates = <10000000>; 72*b10f8238SRichard Zhu assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 73*b10f8238SRichard Zhu num-lanes = <1>; 74*b10f8238SRichard Zhu interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 75*b10f8238SRichard Zhu interrupt-names = "dma"; 76*b10f8238SRichard Zhu fsl,max-link-speed = <3>; 77*b10f8238SRichard Zhu power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 78*b10f8238SRichard Zhu resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 79*b10f8238SRichard Zhu <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 80*b10f8238SRichard Zhu reset-names = "apps", "turnoff"; 81*b10f8238SRichard Zhu phys = <&pcie_phy>; 82*b10f8238SRichard Zhu phy-names = "pcie-phy"; 83*b10f8238SRichard Zhu num-ib-windows = <4>; 84*b10f8238SRichard Zhu num-ob-windows = <4>; 85*b10f8238SRichard Zhu }; 86