# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale i.MX6 PCIe Endpoint controller maintainers: - Lucas Stach - Richard Zhu description: |+ This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. The controller instances are dual mode where in they can work either in Root Port mode or Endpoint mode but one at a time. properties: compatible: enum: - fsl,imx8mm-pcie-ep - fsl,imx8mq-pcie-ep - fsl,imx8mp-pcie-ep reg: minItems: 2 reg-names: items: - const: dbi - const: addr_space interrupts: items: - description: builtin eDMA interrupter. interrupt-names: items: - const: dma required: - compatible - reg - reg-names - interrupts - interrupt-names allOf: - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml# unevaluatedProperties: false examples: - | #include #include #include #include pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; reg-names = "dbi", "addr_space"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>; clock-names = "pcie", "pcie_bus", "pcie_aux"; assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; assigned-clock-rates = <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; num-lanes = <1>; interrupts = ; /* eDMA */ interrupt-names = "dma"; fsl,max-link-speed = <3>; power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "apps", "turnoff"; phys = <&pcie_phy>; phy-names = "pcie-phy"; num-ib-windows = <4>; num-ob-windows = <4>; };