1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Reduced Pin Count Interface (RPC-IF)
8
9maintainers:
10  - Sergei Shtylyov <sergei.shtylyov@gmail.com>
11
12description: |
13  Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
14  be accessed via the external address space read mode or the manual mode.
15
16  The flash chip itself should be represented by a subnode of the RPC-IF node.
17  The flash interface is selected based on the "compatible" property of this
18  subnode:
19  - if it contains "jedec,spi-nor", then SPI is used;
20  - if it contains "cfi-flash", then HyperFlash is used.
21
22allOf:
23  - $ref: "/schemas/spi/spi-controller.yaml#"
24
25properties:
26  compatible:
27    oneOf:
28      - items:
29          - enum:
30              - renesas,r8a774a1-rpc-if       # RZ/G2M
31              - renesas,r8a774b1-rpc-if       # RZ/G2N
32              - renesas,r8a774c0-rpc-if       # RZ/G2E
33              - renesas,r8a774e1-rpc-if       # RZ/G2H
34              - renesas,r8a77970-rpc-if       # R-Car V3M
35              - renesas,r8a77980-rpc-if       # R-Car V3H
36              - renesas,r8a77995-rpc-if       # R-Car D3
37              - renesas,r8a779a0-rpc-if       # R-Car V3U
38          - const: renesas,rcar-gen3-rpc-if   # a generic R-Car gen3 or RZ/G2{E,H,M,N} device
39
40      - items:
41          - enum:
42              - renesas,r9a07g044-rpc-if      # RZ/G2{L,LC}
43              - renesas,r9a07g054-rpc-if      # RZ/V2L
44          - const: renesas,rzg2l-rpc-if
45
46  reg:
47    items:
48      - description: RPC-IF registers
49      - description: direct mapping read mode area
50      - description: write buffer area
51
52  reg-names:
53    items:
54      - const: regs
55      - const: dirmap
56      - const: wbuf
57
58  clocks: true
59
60  interrupts:
61    maxItems: 1
62
63  power-domains:
64    maxItems: 1
65
66  resets:
67    maxItems: 1
68
69patternProperties:
70  "flash@[0-9a-f]+$":
71    type: object
72    properties:
73      compatible:
74        contains:
75          enum:
76            - cfi-flash
77            - jedec,spi-nor
78
79required:
80  - compatible
81  - reg
82  - reg-names
83  - clocks
84  - power-domains
85  - resets
86  - '#address-cells'
87  - '#size-cells'
88
89if:
90  properties:
91    compatible:
92      contains:
93        enum:
94          - renesas,rzg2l-rpc-if
95then:
96  properties:
97    clocks:
98      items:
99        - description: SPI Multi IO Register access clock (SPI_CLK2)
100        - description: SPI Multi IO Main clock (SPI_CLK).
101
102else:
103  properties:
104    clocks:
105      maxItems: 1
106
107unevaluatedProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/clock/renesas-cpg-mssr.h>
112    #include <dt-bindings/power/r8a77995-sysc.h>
113
114    spi@ee200000 {
115      compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
116      reg = <0xee200000 0x200>,
117            <0x08000000 0x4000000>,
118            <0xee208000 0x100>;
119      reg-names = "regs", "dirmap", "wbuf";
120      clocks = <&cpg CPG_MOD 917>;
121      power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
122      resets = <&cpg 917>;
123      #address-cells = <1>;
124      #size-cells = <0>;
125
126      flash@0 {
127        compatible = "jedec,spi-nor";
128        reg = <0>;
129        spi-max-frequency = <40000000>;
130        spi-tx-bus-width = <1>;
131        spi-rx-bus-width = <1>;
132      };
133    };
134